ST72561
8-bit MCU with Flash or ROM, 10-bit ADC, 5 timers, SPI, LINSCITM, active CAN
Features
Memories 16K to 60K High Density Flash (HDFlash) or ROM with read-out protection capability. InApplication Programming and In-Circuit Programming for HDFlash devices 1 to 2K RAM HDFlash endurance: 100 cycles, data retention 40 years at 85C Clock, Reset and Supply Management Low power crystal/ceramic resonator oscillators and bypass for external clock PLL for 2x frequency multiplication 5 power saving modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow Interrupt Management Nested interrupt controller 14 interrupt vectors plus TRAP and RESET TLI top level interrupt (on 64-pin devices) Up to 21 external interrupt lines (on 4 vectors) Up to 48 I/O Ports Up to 48 multifunctional bidirectional I/O lines Up to 36 alternate function lines Up to 6 high sink outputs 5 Timers 16-bit timer with 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes 8-bit timer with 1 or 2 input captures, 1 or 2 output compares, PWM and pulse generator modes 8-bit PWM auto-reload timer with 1 or 2 input captures, 2 or 4 independent PWM output channels, output compare and time base interrupt, external clock with event detector
LQFP32 7x7mm
LQFP64 14x14mm
LQFP44 10x10mm
LQ FP64 10x10mm
Main clock controller with real-time base and clock output Window watchdog timer Up to 4 Communications Interfaces SPI synchronous serial interface Master/slave LINSCITM asynchronous serial interface Master-only LINSCITM asynchronous serial interface CAN 2.0B active Analog Peripheral (Low Current Coupling) 10-bit A/D converter with up to 16 inputs Up to 9 robust ports (low current coupling) Instruction Set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction Development Tools Full hardware/software development package
Table 1. Device Summary
Features Program memory - bytes RAM (stack) - bytes Operating Supply CPU Frequency Max. Temp. Range Packages ST72561AR9/ST72561R9/ ST72561J9/ST72561K9 60K 2K (256) ST72561AR7 48K 2K (256) ST72561AR6/ST72561R6/ ST72561AR4/ST72561J4/ ST72561J6/ST72561K6 ST72561K4 32K 1.5K (256) 16K 1K (256)
4.5V to 5.5 V External Resonator Osc. w/ PLLx2/8 MHz -40C to +125C LQFP64 10x10mm (AR), LQFP64 14x14mm (R) LQFP44 10x10mm (J), LQFP32 7x7mm (K)
Rev. 7
October 2008 1/265
1
Table of Contents
1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5 ACTIVE HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.6 AUTO WAKE-UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 265 9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.6 I/O PORT REGISTER CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2/265
2
Table of Contents
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC . . . . . . . . . . . . . . . 59 10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.5 8-BIT TIMER (TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . . 121 10.8 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER ONLY) . . . . . . . . . . . . 152 10.9 BECAN CONTROLLER (BECAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.1010-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6 AUTO WAKEUP FROM HALT OSCILLATOR (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 12.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 12.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12.10CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 12.11TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.12COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 242 12.1310-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 251 14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 14.2 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 15 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.2 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 16.3 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
3/265
ST72561
1 DESCRIPTION
The ST72561 devices are members of the ST7 microcontroller family designed for mid-range applications with CAN (Controller Area Network) and LIN (Local Interconnect Network) interface. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. Figure 1. Device Block Diagram
option
The on-chip peripherals include an A/D converter, a PWM Autoreload timer, 2 general purpose timers, 2 asynchronous serial interfaces, and an SPI interface. For power economy, microcontroller can switch dynamically into WAIT, SLOW, Active-Halt, Auto Wake-up from HALT (AWU) or HALT mode when the application is in idle or stand-by state. Typical applications are consumer, home, office and industrial products.
OSC1 OSC2
PLL x 2
OSC
PWM ART 8-Bit TIMER 16-Bit TIMER
/2
VDD VSS
POWER SUPPLY
PORT A PORT B PORT C PORT D PORT E PORT F SPI LINSCI2 (LIN master) LINSCI1 (LIN master/slave) WINDOW
ADDRESS AND DATA BUS
RESET TLI1
CONTROL 8-BIT CORE ALU
PA7:0 (8 bits)1 PB7:0 (8 bits)1 PC7:0 (8 bits)1 PD7:0 (8 bits)1 PE7:0 (8 bits)1 PF7:0 (8 bits)1
PROGRAM MEMORY (16 - 60 Kbytes)
RAM (1 - 2 Kbytes)
MCC (Clock Control)
WATCHDOG CAN (2.0B ACTIVE)
1On
some devices only (see Device Summary on page 1)
4/265
3
ST72561
2 PIN DESCRIPTION
Figure 2. LQFP 64-Pin Package Pinout
OSC1 OSC2 ARTIC1 / PA0 PWM0 / PA1 PWM1 / (HS) PA2 PWM2 / PA3 PWM3 / PA4 VSS_3 VDD_3 ARTCLK / (HS) PA5 ARTIC2 / (HS) PA6 T8_OCMP2 / PA7 T8_ICAP2 / PB0 T8_OCMP1 / PB1 T8_ICAP1 / PB2 MCO / PB3
64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
PF7 PF6 PD7 / AIN11 PD6 / AIN10 RESET PD5 / LINSCI2_TDO VDD_0 VDDA VSS_0 VSSA PD4 / LINSCI2_RDI PD3 (HS)/ LINSCI2_SCK PF5 TLI PF4 PF3 / AIN9 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ei3 ei3 ei3 47 46 45 44 ei0 43 ei3 42 41 40 39 ei0 38 37 36 35 ei1 34 ei1 ei2 ei1 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PF2 / AIN8 PF1 / AIN7 PF0 PE7 PD0 / SPI_SS / AIN6 VDD_1 VSS_1 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PE6 / AIN5 PE5 PC4 / CAN_TX PC3 / CAN_RX
AIN12 / PE0 AIN13 / PE1 ICCCLK / AIN0 / PB4 AIN14 / PE2 AIN15 / PE3 ICCDATA / AIN1 / PB5 (*)T16_OCMP1 / AIN2 / PB6 VSS_2 VDD_2 (*)T16_OCMP2 / AIN3 / PB7 (*)T16_ICAP1 / AIN4 / PC0 (*)T16_ICAP2 / (HS) PC1 T16_EXTCLK / (HS) PC2 PE4 NC ICCSEL/VPP
(HS) 20mA high sink capability eix associated external interrupt vector
(*) : by option bit: T16_ICAP1 can be moved to PD4 T16_ICAP2 can be moved to PD1 T16_OCMP1 can be moved to PD3 T16_OCMP2 can be moved to PD5
5/265
ST72561
PIN DESCRIPTION (Cont'd) Figure 3. LQFP 44-Pin Package Pinout
OSC1 OSC2 PWM0 / PA1 PWM1 / (HS) PA2 PWM2 / PA3 PWM3 / PA4 ARTCLK / (HS) PA5 ARTIC2 / (HS) PA6 T8_OCMP1 / PB1 T8_ICAP1 / PB2 MCO / PB3
44 43 42 41 40 39 38 37 36 35 34 1 33 ei3 ei3 2 32 ei3 3 31 4 30 5 ei3 29 ei0 6 28 7 27 8 26 9 25 10 ei1 24 ei2 ei1 11 23 12 13 14 15 16 17 18 19 20 21 22 ICCCLK / AIN0 / PB4 ICCDATA / AIN1 / PB5 (*)T16_OCMP1 / AIN2 / PB6 VSS_2 VDD_2 (*)T16_OCMP2 / AIN3 / PB7 (*)T16_ICAP1 / AIN4 / PC0 (*)T16_ICAP2 / (HS) PC1 T16_EXTCLK / (HS) PC2 PE4 ICCSEL/VPP
PD7 / AIN11 PD6 / AIN10 RESET PD5 / LINSCI2_TDO 1 VDD_0 VDDA VSS_0 VSSA PD4 / LINSCI2_RDI PD3 (HS) / LINSCI2_SCK PF5
PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PF2 / AIN8 PF1 / AIN7 PD0 / SPI_SS / AIN6 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PE6 / AIN5 PC4 / CAN_TX PC3 / CAN_RX
(HS) 20mA high sink capability eix associated external interrupt vector
(*) : by option bit: T16_ICAP1 can be moved to PD4 T16_ICAP2 can be moved to PD1 T16_OCMP1 can be moved to PD3 T16_OCMP2 can be moved to PD5
6/265
ST72561
PIN DESCRIPTION (Cont'd) Figure 4. LQFP 32-Pin Package Pinout
OSC1 OSC2 PWM0 / PA1 PWM1 / (HS) PA2 ARTCLK / (HS) PA5 T8_OCMP1 / PB1 T8_ICAP1 / PB2 MCO / PB3
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 ei3 23 ei3 22 21 ei0 20 19 18 ei1 ei2 ei1 17 9 10 11 12 13 14 15 16 ICCCLK / AIN0 / PB4 ICCDATA / AIN1 / PB5 T16_OCMP1 / AIN2 / PB6 T16_OCMP2 / AIN3 / PB7 T16_ICAP1 / AIN4 / PC0 T16_ICAP2 / (HS) PC1 T16_EXTCLK / (HS) PC2 ICCSEL/VPP
RESET PD5 / LINSCI2_TDO VDD_0 VDDA VSS_0 VSSA PD4 / LINSCI2_RDI PD3 (HS) / LINSCI2_SCK1
PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PD0 / SPI_SS / AIN6 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PC4 / CAN_TX PC3 / CAN_RX
(HS) 20mA high sink capability eix associated external interrupt vector
(*) : by option bit: T16_ICAP1 can be moved to PD4 T16_ICAP2 can be moved to PD1 T16_OCMP1 can be moved to PD3 T16_OCMP2 can be moved to PD5
For external pin connection guidelines, refer to "ELECTRICAL CHARACTERISTICS" on page 219.
7/265
ST72561
PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to "ELECTRICAL CHARACTERISTICS" on page 219. Legend / Abbreviations for Table 2: Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger TT= TTL 0.8V / 2V with Schmitt trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt1), ana = analog, RB = robust Output: OD = open drain, PP = push-pull Refer to "I/O PORTS" on page 46 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 2. Device Pin Description
Pin n LQFP64 LQFP44 LQFP32 Type Pin Name Level O u tput Input Port Input float wpu ana int Main function Output (after reset) OD PP
Alternate function
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9 -
O SC1 3 ) O SC2 3 ) PA0 / ARTIC1 PA1 / PWM0 PA2 (HS) / PWM1 PA3 / PWM2 PA4 / PWM3 VSS_3 VDD_3 PA5 (HS) / ARTCLK PA6 (HS) / ARTIC2 PA7 / T8_OCMP2 PB0 /T8_ICAP2 PB1 /T8_OCMP1 PB2 / T8_ICAP1 PB3 / MCO PE0 / AIN12 PE1 / AIN13 PB4 / AIN0 / ICCCLK PE2 / AIN14 PE3 / AIN15
I I/O I/O CT I/O CT I/O CT HS I/O CT I/O CT S S I/O CT HS I/O CT HS I/O CT I/O CT I/O CT I/O CT I/O CT I/O TT I/O TT I/O CT I/O TT I/O TT X X X X X X X X X X X X X X X ei1 X X ei 0 ei0 ei 0 ei1 ei1 ei1 ei1 X X X X X X X RB X RB X RB X RB X RB X e i 1 RB X X X X X X X X X X X X X X X X X X X ei0 ei 0 ei0 ei 0 ei0 X X X X X X X X X X
External clock input or Resonator oscillator inverter input Resonator oscillator inverter output Port A0 Port A1 Port A2 Port A3 Port A4 ART Input Capture 1 ART PWM Output 0 ART PWM Output 1 ART PWM Output 2 ART PWM Output 3
Digital Ground Voltage Digital Main Supply Voltage Port A5 Port A6 Port A7 Port B0 Port B1 Port B2 Port B3 Port E0 Port E1 Port B4 Port E2 Port E3 Port B5 ART External Clock ART Input Capture 2 TIM8 Output Compare 2 TIM8 Input Capture 2 TIM8 Output Compare 1 TIM8 Input Capture 1 Main clock out (fOSC2) ADC Analog Input 12 ADC Analog Input 13 ICC Clock input ADC Analog Input 0
15 10 16 11 17 18 -
19 12 20 21 -
ADC Analog Input 14 ADC Analog Input 15 ICC Data in- ADC Analog put Input 1
22 13 10 PB5 / AIN1 / ICCDATA I/O CT
8/265
ST72561
Pin n LQFP64 LQFP44 LQFP32 Type Pin Name
Level Output Input
Port Input fl oat wpu ana int
OD
PP
Main function Output (after reset)
Alternate function
23 14 11 24 15 25 16 -
PB6 / AIN2 / T16_OCMP1 VSS_2 VDD_2 PB7 /AIN3 / T16_OCMP2 PC0 / AIN4 / T16_ICAP1
I/O CT S S I/O CT I/O CT
X
X
RB X
X
Port B6
TIM16 Output Compare 1
ADC Analog Input 2
Digital Ground Voltage Digital Main Supply Voltage X X X X X X X X ei2 ei2 RB X RB X X X X X X X X X Port B7 Port C0 Port C1 Port C2 Port E4 Flash programming voltage. Must be tied low in user mode. X X X X X X X X X X X X X X X X X X X X X X2 ) X X X X X Port C3 Port C4 Port E5 Port E6 Port C5 Port C6 Port C7 ADC Analog Input 5 SPI Master In/Slave Out SPI Master Out/Slave In SPI Serial Clock CAN Receive Data Input CAN Transmit Data Output TIM16 Output Compare 2 TIM16 Input Capture 1 ADC Analog Input 3 ADC Analog Input 4
26 17 12 27 18 13
28 19 14 PC1 (HS) / T16_ICAP2 I/O CT HS PC2 (HS) / 29 20 15 T16_EXTCLK 30 21 31 P E4 NC I I/O CT I/O CT I/O TT I/O TT I/O CT I/O CT I/O CT S S I/O CT I/O TT I/O TT I/O TT I/O TT I/O CT I/O CT I/O TT I/O TT I CT I/O TT I/O CT HS I/O CT HS I/O TT
TIM16 Input Capture 2 TIM16 External Clock input
Not Connected
32 22 16 VPP 33 23 17 PC3 / CANRX 34 24 18 PC4 / CANTX 35 P E5 PE6 / AIN5 36 25
37 26 19 PC5 /MISO 38 27 20 PC6 / MOSI 39 28 21 PC7 /SCK 40 41 VSS_1 VDD_1
Digital Ground Voltage Digital Main Supply Voltage X X X X X X X X X X X X X X X X X X X X X X X ei3 X X X X ei3 X X X X X X X X X X X X X X X X X X X X X Port D0 Port E7 Port F0 Port F1 Port F2 Port D1 Port D2 Port F3 Port F4 Top level interrupt input pin Port F5 Port D3 LINSCI2 Serial Clock Output ADC Analog Input 7 ADC Analog Input 8 LINSCI1 Receive Data input LINSCI1 Transmit Data output ADC Analog Input 9 SPI Slave Select ADC Analog Input 6
42 29 22 PD0 / SS/ AIN6 43 44 P E7 P F0 PF1 / AIN7 PF2 / AIN8
45 30 46 31
47 32 23 PD1 / SCI1_RDI 48 33 24 PD2 / SCI1_TDO 49 50 51 PF3 / AIN9 P F4 TLI P F5
52 34
53 35 25 PD3 (HS) / SCI2_SCK
9/265
ST72561
Pin n LQFP64 LQFP44 LQFP32 Type Pin Name
Level Output Input
Port Input fl oat wpu ana int
OD
PP
Main function Output (after reset) X X Port D4
Alternate function
54 36 26 PD4 / SCI2_RDI 55 37 27 VSSA 56 38 28 VSS_0 5 7 3 9 2 9 VDDA 58 40 30 VDD_0 59 41 31 PD5 / SCI2_TDO 60 42 32 R ESET 61 43 62 44 63 64 PD6 / AIN10 PD7 / AIN11 P F6 P F7
I/O CT S S I S I/O CT I/O CT I/O CT I/O CT I/O TT I/O TT
X
ei3
LINSCI2 Receive Data input
Analog Ground Voltage Digital Ground Voltage Analog Reference Voltage for ADC Digital Main Supply Voltage X X X X Port D5 LINSCI2 Transmit Data output ADC Analog Input 10 ADC Analog Input 11
Top priority non maskable interrupt. X X X X X X ei3 X X X X X X X X X Port D6 Port D7 Port F6 Port F7 ei3 X
Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. Input mode can be used for general purpose I/O, output mode only for CANTX. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 6 and Section 12.5 "CLOCK AND TIMING CHARACTERISTICS" for more details. 4. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
10/265
ST72561
3 REGISTER AND MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device.
Figure 5. Memory Map
0000h 007Fh 0080h
HW Registers (see Table 3)
0080h
Short Addressing RAM (zero page)
00FFh 0100h
RAM (2048/1024 bytes)
087Fh 0880h 01FFh 0200h
2 5 6 b y t e s St a c k 16-bit Addressing RAM
047Fh or 087Fh
1000h
60 Kbytes
4000h 8000h
Reserved
0FFFh 1000h
48 Kbytes 32 Kbytes
Program Memory (60K, 48K, 32K, 16K)
FFDFh FFE0h FFFFh
C000h
Interrupt & Reset Vectors (see Table 9)
16 Kbytes
FFDFh
Table 3. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Reset Status 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h Remarks R/W 2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2)
Port A
Port B
Port C
Port D
Port E
11/265
ST72561
Address 000Fh 0010h 0011h 0012h to 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h
Block
Register Label PFDR PFDDR PFOR
Register Name Port F Data Register Port F Data Direction Register Port F Option Register Reserved Area (15 bytes)
Reset Status 00h1 ) 00h 00h
Remarks R/W2) R/W2) R/W2)
Port F
SPI FLASH
SPID R SPICR SPICSR FCSR ISPR0 ISPR1 ISPR2 ISPR3 EICR0 EICR1 AWUC SR AWUPR SICS R MCCSR WDG C R WDGWR PWM DCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2 T8CR2 T8CR1 T8CSR T8IC1R T8OC1R T8CTR T8ACTR T8IC2R T8OC2R ADCCSR ADCDRH ADCDRL
SPI Data I/O Register SPI Control Register SPI Control/Status Register Flash Control/Status Register Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register 0 External Interrupt Control Register 1 Auto Wake up f. Halt Control/Status Register Auto Wake Up From Halt Prescaler System Integrity Control / Status Register Main Clock Control / Status Register Watchdog Control Register Watchdog Window Register Pulse Width Modulator Duty Cycle Register 3 PWM Duty Cycle Register 2 PWM Duty Cycle Register 1 PWM Duty Cycle Register 0 PWM Control register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register ART Input Capture Control/Status Register ART Input Capture Register 1 ART Input Capture register 2 Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture 1 Register Timer Output Compare 1 Register Timer Counter Register Timer Alternate Counter Register Timer Input Capture 2 Register Timer Output Compare 2 Register Control/Status Register Data High Register Data Low Register
xxh 0xh 00h 00h FFh FFh FFh FFh 00h 00h 00h FFh 0xh 00h 7Fh 7Fh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h xxh 00h FCh FCh xxh 00h 00h 00h 00h
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only R/W Read Only Read Only Read Only R/W R/W Read Only Read Only
ITC
AW U CKCTRL W WD G
PW M AR T
8-BIT TIMER
ADC
12/265
ST72561
Address 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h
Block
Register Label SCI1ISR SCI1DR SCI1BRR SCI1CR1 SCI1CR2 SCI1CR3 SCI1ERPR SCI1ETPR
Register Name SCI1 Status Register SCI1 Data Register SCI1 Baud Rate Register SCI1 Control Register 1 SCI1 Control Register 2 SCI1Control Register 3 SCI1 Extended Receive Prescaler Register SCI1 Extended Transmit Prescaler Register Reserved Area (1 byte)
Reset Status C0h xxh 00h xxh 00h 00h 00h 00h
Remarks Read Only R/W R/W R/W R/W R/W R/W R/W
LINSCI1 (LIN Master/ Slave)
16-BIT TIMER
T16CR2 T16CR1 T16CSR T16IC1HR T16IC1LR T16OC1HR T16OC1LR T16CHR T16CLR T16ACHR T16ACLR T16IC2HR T16IC2LR T16OC2HR T16OC2LR SCI2SR SCI2DR SCI2BRR SCI2CR1 SCI2CR2 SCI2CR3 SCI2ERPR SCI2ETPR
Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture 1 High Register Timer Input Capture 1 Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture 2 High Register Timer Input Capture 2 Low Register Timer Output Compare 2 High Register Timer Output Compare 2 Low Register SCI2 Status Register SCI2 Data Register SCI2 Baud Rate Register SCI2 Control Register 1 SCI2 Control Register 2 SCI2 Control Register 3 SCI2 Extended Receive Prescaler Register SCI2 Extended Transmit Prescaler Register
00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00h xxh 00h 00h 00h 00h
R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W R/W R/W
LINSCI2 (LIN Master)
13/265
ST72561
Address 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
Block
Register Label CMCR CMSR CTSR CTPR CRFR CIER CDGR CPSR
Register Name CAN Master Control Register CAN Master Status Register CAN Transmit Status Register CAN Transmit Priority Register CAN Receive FIFO Register CAN Interrupt Enable Register CAN Diagnosis Register CAN Page Selection Register PAGE REGISTER 0 PAGE REGISTER 1 PAGE REGISTER 2 PAGE REGISTER 3 PAGE REGISTER 4 PAGE REGISTER 5 PAGE REGISTER 6 PAGE REGISTER 7 PAGE REGISTER 8 PAGE REGISTER 9 PAGE REGISTER 10 PAGE REGISTER 11 PAGE REGISTER 12 PAGE REGISTER 13 PAGE REGISTER 14 PAGE REGISTER 15
Reset Status
Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Active CAN
PAGES
Legend: x = undefined, R/W = read/write
Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
14/265
ST72561
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 MAIN FEATURES
Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 6). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 4. Sectors available in Flash devices
Flash Size (bytes) 4K 8K > 8K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2
3 Flash programming modes: Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection Register Access Security System (RASS) to prevent accidental programming or erasing
4.3 STRUCTURE The Flash memory is organised in sectors and can be used for both code and data storage. Figure 6. Memory Map and Sector Address
4K
1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh
4.3.1 Read-out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List.
8K
10K
16K
24K
32K
48K
60K
FLASH MEMORY SIZE
SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0
15/265
ST72561
FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC INTERFACE ICC (In-Circuit Communication) needs a minimum of four and up to six pins to be connected to the programming tool (see Figure 7). These pins are: RESET: device reset VSS: device power supply ground Figure 7. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) OPTIONAL (See Note 4) ICC CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O
ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) VDD: application board power supply (see Figure 7, Note 3)
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R > 1K or a reset man-
agement IC with open drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
16/265
ICCSEL/VPP
ICCDATA
RESET
ICCCLK
OSC2
OSC1
VDD
VSS
ST72561
FLASH PROGRAM MEMORY (Cont'd) 4.5 ICP (IN-CIRCUIT PROGRAMMING) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 7). For more details on the pin locations, refer to the device pinout description. 4.6 IAP (IN-APPLICATION PROGRAMMING) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI or other type of serial interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/ erase protected to allow recovery in case errors occur during the programming operation. 4.7 RELATED DOCUMENTATION For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.8 REGISTER DESCRIPTION FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 0
This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.
Table 5. Flash Control/Status Register Address and Reset Value
Address (Hex.) 0024h Register Label FC SR Reset Value 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
17/265
ST72561
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES
5.3 CPU REGISTERS The six CPU registers shown in Figure 8 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 8. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
18/265
ST72561
CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
19/265
ST72561
CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 9. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event P USH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 01FFh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
20/265
ST72561
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example, in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11. For more details, refer to dedicated parametric section. Main features Optional PLL for multiplying the frequency by 2 Reset Sequence Manager (RSM) Multi-Oscillator Clock Management (MO) 4 Crystal/Ceramic resonator oscillators System Integrity Management (SI) Main supply Low voltage detection (LVD) Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply Figure 11. Clock, Reset and Supply Block Diagram
/ 8000 8-BIT TIMER
6.1 PHASE LOCKED LOOP If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for applications where timing accuracy is required. See "PLL Characteristics" on page 228. Figure 10. PLL Block Diagram
PLL x 2
fOSC 0 fOSC2 1
/2
PLL OPTION BIT
OSC2 OSC1
MULTIOSCILLATOR (MO)
fOSC PLL (option)
fOSC2
MAIN CLOCK CONTROLLER WITH REALTIME CLOCK (MCC/RTC) SYSTEM INTEGRITY MANAGEMENT
fCPU
RESET SEQUENCE RESET MANAGER (RSM)
AVD Interrupt Request SICSR AVD AVD LVD 0 F RF IE WDG RF
WATCHDOG TIMER (WDG)
0
0
0
LOW VOLTAGE VSS VDD DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
21/265
ST72561
6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by two different source types coming from the multioscillator block: an external source a crystal or ceramic resonator oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in Table 6. Refer to the electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an unsafe/undefined state. The product behavior must therefore be considered undefined when the OSC pins are left unconnected. External Clock Source In external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of five oscillators with different frequency ranges must be done by option byte in order to reduce consumption (refer to Section 14.1 on page 252 for more details on the frequency ranges). The resonator and the load capacitors must be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Table 6. ST7 Clock Sources
Hardware Configuration
External Clock
ST7 OS C1 OSC 2
EX TERNAL SO URCE
Crystal/Ceramic Resonators
ST7 OSC 1 OSC2
CL1
LOA D CAPA CITO RS
CL 2
22/265
ST72561
6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 2: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of three phases as shown in Figure 1: Active Phase depending on the RESET source 256 or 4096 CPU clock cycle delay (selected by option byte) RESET vector fetch The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. The RESET vector fetch phase duration is two clock cycles. Figure 13. Reset Block Diagram Figure 12. RESET Sequence Phases
RESET
Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR
Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. 6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 3). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.
VDD
RO N
RESET
Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET LVD RESET
23/265
ST72561
RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.3.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.3.4 Internal Low Voltage Detector (LVD) RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or VDD < VIT- (falling edge) as shown in Figure 3. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. 6.3.5 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 3. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
Figure 14. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
LVD RESET
EXTERNAL RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH
24/265
ST72561
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. 6.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+(LVD) when VDD is rising VIT-(LVD) when VDD is falling The LVD function is illustrated in Figure 15. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: under full software control in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be selected by option byte. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.
Figure 15. Low Voltage Detector vs Reset
VDD
Vhys VIT+(LVD) VIT-(LVD)
RESET
25/265
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply. The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD function is active only if the LVD is enabled through the option byte. 6.4.2.1 Monitoring the VDD Main Supply If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut Figure 16. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vh y s t
down safely before the LVD resets the microcontroller. See Figure 16. The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles then: If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then two AVD interrupts will be received: The first when the AVDIE bit is set and the second when the threshold is reached. If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached, then only one AVD interrupt occurs.
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
trv VOLTAGE RISE TIME
AVDF bit AVD INTERRUPT REQUES T IF AVDIE bit = 1
0
1
RESET VALUE
1
0
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
26/265
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.3 Low Power Modes
Mode WAIT H ALT Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen.
6.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event AVD event Enable Event Control Flag Bit AVDF AV DIE Exit from Wait Yes Exit from Halt No
27/265
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read / Write Reset Value: 000x 000x (00h) Bits 3:1 = Reserved, must be kept cleared.
7 0 AVD IE A VD F LVD RF 0 0 0 0 WDG RF
Bit 7 = Reserved, must be kept cleared. Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to Figure 16 and to Section 6.4.2.1 for additional details . 0: VDD over VIT+(AVD) threshold 1: VDD under VIT-(AVD) threshold Bit 4 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.
Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LV DRF 0 0 1 WDG R F 0 1 X
Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not. CAUTION: When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application.
28/265
ST72561
7 INTERRUPTS
7.1 INTRODUCTION The ST7 enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 2 non maskable events: RESET, TRAP 1 maskable Top Level Event: TLI This interrupt management is based on: Bit 5 and bit 3 of the CPU CC register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of Figure 17. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TLI Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
each interrupt vector (see Table 6). The processing flow is shown in Figure 17. When an interrupt request has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 7. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 High 1 I0 0 1 0 1
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
29/265
ST72561
INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 18 describes this decision process. Figure 18. Priority Decision Process
PENDING INTERRUPTS
TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 17 as a TLI. Caution: TRAP can be interrupted by a TLI. RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 17). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service routine. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being serviced) will therefore be lost if the clear sequence is executed.
30/265
ST72561
INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 18. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 19. Concurrent Interrupt Management
SOFTW ARE PRIORITY LEVEL IT2 IT1 IT4 IT3 TLI IT0 I1 I0
7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 19 and Figure 20 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 20. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 20. Nested Interrupt Management
SOFTW ARE PRIORITY LEVEL
TLI
IT0
IT2
IT1
IT4
IT3
I1
I0
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
31/265
USED STACK = 20 BY TES
USED STACK = 10 BYTES
ST72561
INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 High 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TLI, TRAP and RESET events can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (Example: previous = CFh, write = 64h, result = 44h) The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
32/265
ST72561
INTERRUPTS (Cont'd)
Table 8. Dedicated Interrupt Instruction Set
Instruction HALT IRET JRM JRNM POP CC RIM SIM TRAP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0 = 11 (level 3) Jump if I1:0 <> 11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Pop CC, A, X, PC I1:0 = 11 ? I1:0 <> 11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
33/265
ST72561
INTERRUPTS (Cont'd) Table 9. Interrupt Mapping
N Source Block RESE T TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 TLI MC C/RTC ei0/AW UFH ei1/A V D ei2 ei3 CAN CAN S PI TIM E R8 TIMER16 LINSCI2 LINSCI1 PWM ART Reset Software interrupt External top level interrupt Main clock controller time base interrupt External interrupt ei0/ Auto wake-up from Halt External interrupt ei1/Auxiliary Voltage Detector External interrupt ei2 External interrupt ei3 CAN peripheral interrupt - RX CAN peripheral interrupt - TX / ER / SC SPI peripheral interrupts 8-bit TIMER peripheral interrupts 16-bit TIMER peripheral interrupts LINSCI2 Peripheral interrupts LINSCI1 Peripheral interrupts (LIN Master/ Slave) 8-bit PWM ART interrupts Description Register Label N/A EICR M CCSR EICR/ AWU CSR EICR/ SICSR EICR EICR CIER CIER SP ICSR T8_TCR1 TCR 1 SCI2CR1 SCI1CR1 PW MCR Lowest Priority no yes3) yes no no no no4) yes yes2) Highest Priority Priority Order Exit from HALT1 ) yes no yes yes Address Vector FFFEh-FFFFh FFFC h-FFFDh FFFA h-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEE h-FFEFh FFEC h -FFEDh FFEA h -FFEBh FFE 8h-FFE9h FFE 6h-FFE7h FFE 4h-FFE5h FFE 2h-FFE3h FFE 0h-FFE1h
Notes: 1. Valid for HALT and ACTIVE HALT modes except for the MCC/RTC interrupt source which exits from ACTIVE HALT mode only. 2. Except AVD interrupt 3. Exit from Halt only when a wake-up condition is detected, generating a Status Change interrupt. See Section 10.8.6 on page 160. 4. It is possible to exit from Halt using the external interrupt which is mapped on the RDI pin.
34/265
ST72561
INTERRUPTS (Cont'd) 7.6 EXTERNAL INTERRUPTS 7.6.1 I/O Port Interrupt Sensitivity The external interrupt sensitivity is controlled by the ISxx bits in the EICR register (Figure 21). This control allows up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: Falling edge Rising edge Figure 21. External Interrupt Control Bits
PORT A [7:0] INTERRUPTS PAOR.0 PADDR.0 PA0 EICR IS00 IS01 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
Falling and rising edge Falling edge and low level To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0] of the EICR.
SENSITIVITY CONTROL
ei0 INTERRUPT SOURCE
PORT B [5:0] INTERRUPTS PBOR.0 PBDDR.0 PB0
EICR IS10 IS11
AWUFH Oscillator
/ AWUPR
To Timer Input Capture 1
PB0 PB1 PB2 PB3 PB4 PB5
SENSITIVITY CONTROL
ei1 INTERRUPT SOURCE
PORT C [2:1] INTERRUPTS PCOR.7 PCDDR.7 PC1
EICR IS20 IS21 PC1 PC2 ei2 INTERRUPT SOURCE
SENSITIVITY CONTROL
PORT D [7:6, 4, 1:0] INTERRUPTS PDOR.0 PDDDR.0 PD0
EICR IS30 IS31 PD0 PD1 PD4 PD6 PD7
SENSITIVITY CONTROL
ei3 INTERRUPT SOURCE
35/265
ST72561
INTERRUPTS (Cont'd) 7.6.2 Register Description EXTERNAL INTERRUPT CONTROL REGISTER 0 (EICR0) Read / Write Reset Value: 0000 0000 (00h)
7 IS31 IS30 IS21 IS20 IS11 IS10 IS01 0 IS00
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 1:0 = IS0[1:0] ei0 sensitivity The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts:
I S 0 1 IS00 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Bits 7:6 = IS3[1:0] ei3 sensitivity The interrupt sensitivity, defined using the IS3[1:0] bits, is applied to the ei3 external interrupts:
I S 3 1 IS30 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). EXTERNAL INTERUPT CONTROL REGISTER 1 (EICR1) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 TLIS 0 TLIE
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 5:4 = IS2[1:0] ei2 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the ei2 external interrupts:
I S 2 1 IS20 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
BIts 7:2 = Reserved Bit 1 = TLIS Top Level Interrupt sensitivity This bit configures the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared. 0: Falling edge 1: Rising edge Bit 0 = TLIE Top Level Interrupt enable This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by software. 0: TLI disabled 1: TLI enabled Notes: A parasitic interrupt can be generated when clearing the TLIE bit. In some packages, the TLI pin is not available. In this case, the TLIE bit must be kept low to avoid parasitic TLI interrupts.
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 3:2 = IS1[1:0] ei1 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei1 external interrupts:
I S 1 1 IS10 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
36/265
ST72561
INTERRUPTS (Cont'd) Table 10. Nested Interrupts Register Map and Reset Values
Address (Hex.) 0025h Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value EICR0 Reset Value EICR1 Reset Value 7 6 5 4 3 CLKM I1_1 1 ei3 I1_5 I0_5 1 1 TIM E R 8 I1_9 I0_9 1 1 ART I1_13 I0_13 1 1 IS11 IS10 0 0 0 0 I1_4 1 I0_1 1 1 ei2 I0_4 1 2 1 TLI 1 0
0026h
0027h
ei1 I1_3 I0_3 1 1 CAN TX/ER/SC I1_7 I0_7 1 1 LINSCI 2 I1_11 I0_11 1 1
ei0 I1_2 I0_2 1 1 CAN RX I1_6 I0_6 1 1 TIMER 16 I1_10 I0_10 1 1
0028h 0029h 002Ah
1 IS31 0 0
1 IS30 0 0
1 IS 21 0 0
1 IS20 0 0
SPI I1_8 I0_8 1 1 LINSCI 1 I1_12 I0_12 1 1 IS01 IS00 0 0 TLIS TLIE 0 0
37/265
ST72561
8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see Figure 22): Slow Wait (and Slow-Wait) Active Halt Auto Wake-up From Halt (AWUFH) Halt After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 22. Power Saving Mode Transitions
MCCSR High RUN SLO W WAIT SLOW WA IT AC TIVE HALT AUTO WAKE-UP FROM HALT HALT Low PO WER CONS UMPTION
NEW SLOW FREQUENCY REQUEST NORMAL RUN MODE REQUEST
8.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: SLOW-WAIT mode is activated by entering WAIT mode while the device is in SLOW mode. Figure 23. SLOW Mode Clock Transitions
fOSC2/2 fCPU fOSC2/4 fOSC2
f OSC2 CP1:0 SMS 00 01
38/265
ST72561
POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 24 Figure 24. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON OFF 10
WFI I N S T R U C T I O N
N RESET N INTE RRUPT Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 10 Y
256 OR 4096 CPU CLOCK CYCLE DELAY
OSCILLATOR ON PERIPHERALS ON CPU ON I[1:0] BITS XX 1 )
FETCH RESET VECTO R OR SERVICE INTER RUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
39/265
ST72561
POWER SAVING MODES (Cont'd) 8.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2 on page 59 for more details on the MCCSR register) and when the AWUEN bit in the AWUCSR register is cleared. The MCU can exit HALT mode on reception of either a specific interrupt (see Table 9, "Interrupt Mapping," on page 34) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 26). When entering HALT mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 10.1 on page 53 for more details). Figure 25. HALT Timing Overview
RUN HA LT 256 OR 4096 CPU CYCLE DELAY R ESET OR INTERR UPT FETC H VECTOR RUN
Figure 26. HALT Mode Flow-chart
H A L T INS T RUCTIO N (M CCSR.OIE = 0) (AW UCSR.AWUE N=0) ENABLE WDGHALT 1) 1 WATCHD OG R ESET OS CILLATOR OFF PERIPHERALS 2) OFF C PU OFF I[1:0] BITS 10 0 W ATCHDOG DISABLE
N RE SET N Y INTERRUPT 3) Y OS CILLATOR ON PERIPHERALS OFF C PU ON I[1:0] BITS XX 4) 256 OR 4096 CPU CLOCK CYCLE D EL AY OS CILLATOR ON PERIPHERALS ON C PU ON I[1:0] BITS XX 4) FE TCH R E SET VE CTOR O R SERVIC E INTERRUP T
HALT INS T RUCTIO N [MCCSR.OIE=0]
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 9, "Interrupt Mapping," on page 34 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
40/265
ST72561
POWER SAVING MODES (Cont'd) Halt Mode Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 8.5 ACTIVE HALT MODE ACTIVE HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when MCC/RTC interrupt enable flag (OIE bit in MCCSR register) is set and when the AWUEN bit in the AWUCSR register is cleared (See "Register Description" on page 45.)
MCCSR OIE bit 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE HALT mode
The MCU can exit ACTIVE HALT mode on reception of the RTC interrupt and some specific interrupts (see Table 9, "Interrupt Mapping," on page 34) or a RESET. When exiting ACTIVE HALT mode by means of a RESET a 4096 or 256 CPU cycle delay occurs (depending on the option byte). After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 28). When entering ACTIVE HALT mode, the I[1:0] bits in the CC register are are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVE HALT mode is provided by the oscillator interrupt. Note: As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.
41/265
ST72561
POWER SAVING MODES (Cont'd) Figure 27. ACTIVE HALT Timing Overview
RUN ACTIVE 256 OR 4096 CYCLE HALT DELAY (AFTER RESET) RUN
R ESET OR HA LT INTERR UPT INS T RUCTIO N (Active Halt enabled)
FETC H VECTOR
Figure 28. ACTIVE HALT Mode Flow-chart
H A L T INSTR UCTIO N (MC C SR. O IE=1) (AW UCSR.AWUEN =0) OSCILLATOR ON PERIPHERALS 2) OFF CPU OFF 10 I[1:0] BITS N RESET N INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON XX 4 ) Y
Notes: 1. This delay occurs only if the MCU exits ACTIVE HALT mode by means of a RESET. 2. Peripheral clocked with an external clock source can still be active. 3. Only the RTC interrupt and some specific interrupts can exit the MCU from ACTIVE HALT mode (such as external interrupt). Refer to Table 9, "Interrupt Mapping," on page 34 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.
256 OR 4096 CPU CLOCK CY CLE DE LAY OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON ON XX 4 )
FETCH RESET VECTO R OR SERVICE INTERRUPT
42/265
ST72561
POWER SAVING MODES (Cont'd) 8.6 AUTO WAKE-UP FROM HALT MODE Auto Wake-Up From Halt (AWUFH) mode is similar to Halt mode with the addition of an internal RC oscillator for wake-up. Compared to ACTIVE HALT mode, AWUFH has lower power consumption because the main clock is not kept running, but there is no accurate realtime clock available. It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set and the OIE bit in the MCCSR register is cleared (see Section 10.2 on page 59 for more details ). Figure 29. AWUFH Mode Block Diagram AWU RC oscillator fAWU_RC to Timer input capture and a 256 or 4096 cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency fAWU_RC and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects fAWU_RC to the ICAP1 input of the 16-bit timer, allowing the fAWU_RC to be measured using the main oscillator clock as a reference timebase. Similarities with Halt mode The following AWUFH mode behavior is the same as normal Halt mode: The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see Section 8.4 "HALT MODE"). When entering AWUFH mode, the I[1:0] bits in the CC register are forced to 10b to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). The compatibility of Watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET.
/64 divider
AWUFH prescaler /1 .. 255
AWUFH interrupt (ei0 source)
As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set by hardware and an interrupt wakes up the MCU from Halt mode. At the same time the main oscillator is immediately turned on Figure 30. AWUF Halt Timing Diagram tAWU RUN MODE
fCPU fAWU_RC
HALT MODE
256 or 4096 tCPU
RUN MODE
Clear by software
AWUFH interrupt
43/265
ST72561
POWER SAVING MODES (Cont'd) Figure 31. AWUFH Mode Flow-chart
H AL T INSTRUCTION (MCCSR.OIE=0) (AWUCSR.AWUEN=1) ENABLE WDGHALT 1) 1 WATCHD OG R ESET AWU RC OSC ON MAIN OSC OFF PERIPHERALS 2) OFF C PU OFF I[1:0] BITS 10 0 W ATCHDOG DISABLE
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 9, "Interrupt Mapping," on page 34 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
N RE SET N Y INTERRUPT 3) Y AWU RC OSC OFF MAIN OSC ON PERIPHER ALS OFF C PU ON I[1:0] BITS XX 4) 256 OR 4096 CPU CLOCK CYCLE D EL AY AWU RC OSC OFF MAIN OSC ON PERIPHER ALS O N C PU ON I[1:0] BITS XX 4) FE TCH RE SET VE CTOR O R SERVIC E INTERRUP T
44/265
ST72561
POWER SAVING MODES (Cont'd) 8.6.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read / Write (except bit 2 read only) Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 AWU AWU A W U F M EN
0: AWUFH (Auto Wake-Up From Halt) mode disabled 1: AWUFH (Auto Wake-Up From Halt) mode enabled AWUFH PRESCALER REGISTER (AWUPR) Read / Write Reset Value: 1111 1111 (FFh)
7 0
Bits 7:3 = Reserved. Bit 2 = AWUF Auto Wake-Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. 0: No AWU interrupt occurred 1: AWU interrupt occurred Bit 1 = AWUM Auto Wake-Up Measurement This bit enables the AWU RC oscillator and connects its output to the ICAP1 input of the 16-bit timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPR register. 0: Measurement disabled 1: Measurement enabled Bit 0 = AWUEN Auto Wake-Up From Halt Enabled This bit enables the Auto Wake-Up From Halt feature: once HALT mode is entered, the AWUFH wakes up the microcontroller after a time delay defined by the AWU prescaler value. It is set and cleared by software. Table 11. AWU Register Map and Reset Values
Address (Hex.) 002Bh 002Ch Register Label 7 6 5
A W U A W U A W U A W U A W U A WU A WU A W U P R7 P R6 P R5 PR4 PR3 PR2 PR1 PR0
Bits 7:0 = AWUPR[7:0] Auto Wake-Up Prescaler These 8 bits define the AWUPR Dividing factor (as explained below:
AW UPR[7:0] 00h 01h ... FEh FFh Dividing factor Forbidden (See note) 1 ... 254 255
In AWU mode, the period that the MCU stays in Halt Mode (tAWU in Figure 30) is defined by
t
AWU
1 = 64 × A W U P R × ------------------------- + t RCSTRT f AWURC
This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically. Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction or the AWUPR remains unchanged.
4
3
2
1
0
A WU C S R AWUF AWUM AWUEN 0 0 0 0 0 Reset Value 0 0 0 A WU P R A W U P R 7 A W U P R 6 A W U P R 5 A W U P R 4 A W U P R 3 A WU P R 2 A W U P R 1 A W U P R 0 Reset Value 1 1 1 1 1 1 1 1
45/265
ST72561
9 I/O PORTS
9.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has two main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: Bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 32 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this might corrupt the DR content for I/Os configured as input. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified. 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VS S VDD Open-drain Vss Floating
9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
46/265
ST72561
I/O PORTS (Cont'd) Figure 32. I/O Port General Block Diagram
ALTERNATE OU TPUT
REGISTER ACCESS
1 0
VDD
P-BUFFER (see table below) PULL-UP (see table below) VDD
ALTERNATE ENA BLE DR
DDR PULL-UP COND ITION If implemented OR SEL N-BUFFER DDR SEL CMO S SCHMITT TRIG GER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERN AL INTERR UPT SOURCE (eix)
Table 12. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS
O u tput
Legend: NI - not implemented Off - implemented not activated On - implemented and activated
DATA BUS
DR SEL
1 0
ALTERNATE INPUT
NI (see note)
Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
47/265
ST72561
I/O PORTS (Cont'd) Table 13. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONDITION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT CONDITION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
OPEN-DRAIN OUTPUT 2)
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT 2)
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
48/265
ST72561
I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33 on page 49. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
Figure 33. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
9.4 LOW POWER MODES
Mode WAIT H AL T Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
9.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx OR x Exit from Wait Exit from Halt
Yes
49/265
ST72561
I/O PORTS (Cont'd) 9.6 I/O PORT REGISTER CONFIGURATIONS The I/O port register configurations are summarized as follows. 9.6.1 Standard Ports PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0
MODE floating input pull-up input open drain output push-pull output D DR 0 0 1 1 OR 0 1 0 1
PA1,3,5,7; PB1,3,5; PC2; PD1,4,7 (without pull-up)
MODE floating input floating interrupt input open drain output push-pull output D DR 0 0 1 1 OR 0 1 0 1
9.6.3 Pull-up Input Port (CANTX requirement) P C4
MO DE pull-up input
9.6.2 Interrupt Ports PA0,2,4,6; PB0,2,4; PC1; PD0,6 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output D DR 0 0 1 1 OR 0 1 0 1
The PC4 port cannot operate as a general purpose output. The CAN peripheral controls it directly when enabled. Otherwise, PC4 is a pull-up input. If DDR = 1 it is still possible to read the port through the DR register.
50/265
ST72561
I/O PORTS (Cont'd) Table 14. Port Configuration
Port Pin name
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PC0 PC1 PC2 PC3 PC4 PC7:5 PD0 PD1 PD3:2 PD4 PD5 PD6 PD7 PE7:0 PF7:0
Input OR = 0 OR = 1
pull-up interrupt (ei0) floating interrupt (ei0) pull-up interrupt (ei0) floating interrupt (ei0) pull-up interrupt (ei0) floating interrupt (ei0) pull-up interrupt (ei0) floating interrupt (ei0) pull-up interrupt (ei1) floating interrupt (ei1) pull-up interrupt (ei1) floating interrupt (ei1) pull-up interrupt (ei1) floating interrupt (ei1) pull-up pull-up interrupt (ei2) floating interrupt (ei2) pull-up pull-up pull-up pull-up interrupt (ei3) floating interrupt (ei3) pull-up floating interrupt (ei3) pull-up pull-up interrupt (ei3) floating interrupt (ei3) pull-up (TTL) pull-up (TTL)
Output OR = 0 OR = 1
Port A
floating
open drain
push-pull
Port B
floating
open drain
push-pull
floating
open drain
push-pull
Port C
floating
controlled by CANTX * open drain push-pull
Port D
floating
open drain
push-pull
Port E Port F
floating (TTL) floating (TTL)
open drain open drain
push-pull push-pull
* Note: When the CANTX alternate function is selected, the I/O port operates in output push-pull mode.
51/265
ST72561
I/O PORTS (Cont'd) Table 15. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Reset Value of all IO port registers 0000h P ADR 0001h P ADDR 0002h P A OR 0003h P BDR 0004h P BDDR 0005h P B OR 0006h P CDR 0007h P CDDR 0008h P C OR 0009h P DDR 000Ah P DDDR 000Bh P D OR 000Ch P EDR 000Dh P EDDR 000Eh P E OR 000Fh P F DR 0010h P F DDR 0011h P F OR
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
52/265
ST72561
10 ON-CHIP PERIPHERALS
10.1 WINDOW WATCHDOG (WWDG) 10.1.1 Introduction The Window Watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window. 10.1.2 Main Features Programmable free-running downcounter Conditional reset Reset (if watchdog activated) when the downcounter value becomes less than 40h Reset (if watchdog activated) if the downFigure 34. Watchdog Block Diagram
RES ET W6 WATCHDOG WINDOW REGISTER (WDGWR) W5 W4 W3 W2 W1 W0
counter is reloaded outside the window (see Figure 4) Hardware/Software Watchdog activation (selectable by option byte) Optional reset on HALT instruction (configurable by option byte) 10.1.3 Functional Description The counter value stored in the WDGCR register (bits T[6:0]), is decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit downcounter (T[6:0] bits) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30s. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated.
comparator = 1 when T6:0 > W6:0 CMP Write WDGCR WATCHDOG CONTROL REGISTER (WDGCR) WDGA T6 T5 T4 T3 T2 T1 T0
MCC/RTC fOSC2
DIV 64
6-BIT DOWNCOUNTER (CNT)
WDG PRESCALER DIV 4 12-BIT MCC RTC COUNTER MS B
11 65
LSB
0
TB[1:0] bits (MC C SR Register)
53/265
ST72561
WINDOW WATCHDOG (Cont'd) The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WDGCR register must be between FFh and C0h (see Figure 2): Enabling the watchdog: When Software Watchdog is selected (by option byte), the watchdog is disabled after a reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be disabled again except by a reset. When Hardware Watchdog is selected (by option byte), the watchdog is always active and the WDGA bit is not used. Controlling the downcounter: This downcounter is free-running: It counts down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see Figure 2. Approximate Timeout Duration). The timing varies
between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 3). The window register (WDGWR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 3Fh. Figure 4 describes the window watchdog process. Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). Watchdog Reset on Halt option If the watchdog is activated and the watchdog reset on halt option is selected, then the HALT instruction will generate a Reset. 10.1.4 Using Halt Mode with the WDG If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
54/265
ST72561
WINDOW WATCHDOG (Cont'd) 10.1.5 How to Program the Watchdog Timeout Figure 2 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If Figure 35. Approximate Timeout Duration 3F 38 30
more precision is needed, use the formulae in Figure 3. Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.
CNT Value (hex.)
28 20 18
10 08 00 1.5 18 34 50 65 82 98 114 128 Watchdog timeout (ms) @ 8 MHz fOSC2
55/265
ST72561
WINDOW WATCHDOG (Cont'd) Figure 36. Exact Timeout Duration (tmin and tmax) W HE RE : tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2 = 8 MHz CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register
TB1 Bit TB0 Bit (MCCSR Reg.) (MCCSR Reg.) 0 0 0 1 1 0 1 1 Selected MCCSR Timebase 2ms 4ms 10ms 25ms MSB 4 8 20 49 L SB 59 53 35 54
To calculate the minimum Watchdog Timeout (tmin):
S IF C N T < M------B ---- --4
T H E N t m i n = t m i n 0 + 16384 × C N T × t o s c 2
NT NT ELSE t m i n = t m i n 0 + 16384 × C N T 4--C--------- + ( 192 + L S B ) × 64 × 4--C---------- ---- -- MSB MSB
× to s c 2
To calculate the maximum Watchdog Timeout (tmax):
S IF C N T M------B ---- --4
THEN t m a x = t m a x 0 + 16384 × C N T × t o s c 2
NT NT ELSE t m a x = t m a x 0 + 16384 × C N T 4--C--------- + ( 192 + L S B ) × 64 × 4--C---------- ---- -- MSB MSB
× to s c 2
Note: In the above formulae, division results must be rounded down to the next integer value. Example: With 2ms timeout selected in MCCSR register
Value of T[5:0] Bits in WDGCR Register (Hex.) 00 3F Min. Watchdog Timeout (ms) tmin 1.496 128 Max. Watchdog Timeout (ms) tmax 2.048 128.552
56/265
ST72561
WINDOW WATCHDOG (Cont'd) Figure 37. Window Watchdog Timing Diagram
T[5:0] CNT downcounter
WDGWR
3Fh
Refresh not allowed Refresh Window
time (step = 16384/fOSC2)
T6 bit Reset
10.1.6 Low Power Modes Mode SLOW WAIT Description No effect on Watchdog: The downcounter continues to decrement at normal speed. No effect on Watchdog: The downcounter continues to decrement.
OIE bit in MCCSR register WDGHALT bit in Option Byte No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. 0 0 If an interrupt is received (refer to interrupt table mapping to see interrupts which can occur in halt mode), the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 0.1.8 below. A reset is generated instead of entering halt mode. No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.
HALT
0
1
ACTIVE HALT
1
x
10.1.7 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Option Byte description.
10.1.8 Using Halt Mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled. Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
57/265
ST72561
WINDOW WATCHDOG (Cont'd) 10.1.9 Interrupts None. 10.1.10 Register Description CONTROL REGISTER (WDGCR) Read / Write Reset Value: 0111 1111 (7F h)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
WINDOW REGISTER (WDGWR) Read/Write Reset Value: 0111 1111 (7Fh)
7 W6 W5 W4 W3 W2 W1 0 W0
Bit 7 = Reserved Bits 6:0 = W[6:0] 7-bit window value These bits contain the window value to be compared to the downcounter.
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB). These bits contain the value of the watchdog counter. It is decremented every 16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Figure 38. Watchdog Timer Register Map and Reset Values
Address (Hex.) 2F 30 Register Label WDG C R Reset Value W D GW R Reset Value 7 W D GA 0 0 6 T6 1 W6 1 5 T5 1 W5 1 4 T4 1 W4 1 3 T3 1 W3 1 2 T2 1 W2 1 1 T1 1 W1 1 0 T0 1 W0 1
58/265
ST72561
ON-CHIP PERIPHERALS (Cont'd) 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC The Main Clock Controller consists of three different functions: a programmable CPU clock prescaler a clock-out signal to supply external devices a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 10.2.1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See Section 8.2 "SLOW MODE" for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MCCSR register: CP[1:0] and SMS. 10.2.2 Clock-out Capability The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC2 clock to drive external devices. It is controlled by the MCO bit in the MCCSR register. 10.2.3 Real Time Clock Timer (RTC) The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on fOSC2 are available. The whole functionality is controlled by 4 bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE HALT mode when the HALT instruction is executed. See Section 8.5 "ACTIVE HALT MODE" for more details.
Figure 39. Main Clock Controller (MCC/RTC) Block Diagram
fOSC2
MCO
RTC COUNTER
TO WATCHDOG TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE MCCSR
OIF MCC/RTC INTERRUPT
DIV 2, 4, 8, 16
fCPU
CPU CLOCK TO CPU AND PERIPHERALS
59/265
ST72561
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) 10.2.4 Low Power Modes Bits 6:5 = CP[1:0] CPU clock prescaler Mode Description These bits select the CPU clock prescaler which is No effect on MCC/RTC peripheral. applied in the different slow modes. Their action is WAIT MCC/RTC interrupt cause the device to conditioned by the setting of the SMS bit. These exit from WAIT mode. two bits are set and cleared by software
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. ACTIVE HALT MCC/RTC interrupt cause the device to exit from ACTIVE HALT mode. MCC/RTC counter and registers are froH ALT zen. and MCC/RTC operation resumes when the AWUF HALT MCU is woken up by an interrupt with "exit from HALT" capability. fCPU in SLOW mode fOSC2 / 2 fOSC2 / 4 fOSC2/ 8 fOSC2 / 16 CP1 0 0 1 1 CP0 0 1 0 1
10.2.5 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Bit OIF OIE Exit from Wait Yes Exit from Halt No1 )
Bit 4 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC2 1: Slow mode. fCPU is given by CP1, CP0 See Section 8.2 "SLOW MODE" and Section 10.2 "MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC" for more details. Bits 3:2 = TB[1:0] Time base control These bits select the programmable divider time base. They are set and cleared by software.
Time Base Counter Prescaler f OSC2 =4 MHz fOSC2=8 MHz 16000 32000 80000 20 0 0 4ms 8ms 20ms 50ms 2ms 4ms 10m s 25m s TB1 0 0 1 1 TB0 0 1 0 1
Note: The MCC/RTC interrupt wakes up the MCU from ACTIVE HALT mode, not from HALT or AWUF HALT mode. 10.2.6 Register Description MCC CONTROL/STATUS REGISTER (MCCS |
