STM690A, STM692A, STM703 STM704, STM802, STM805, STM817/8/9
5 V supervisor with battery switchover
Features
5 V operating voltage NVRAM supervisor for external LPSRAM Chip-enable gating (STM818 only) for external LPSRAM (7 ns max prop delay) RST and RST outputs 200 ms (typ) trec Watchdog timer - 1.6 sec (typ) Automatic battery switchover Low battery supply current - 0.4 A (typ) Power-fail comparator (PFI/PFO) Low supply current - 40 A (typ) Guaranteed RST (RST) assertion down to VCC = 1.0 V Operating temperature: 40C to +85C (industrial grade) RoHS compliance Lead-free components are compliant with the RoHS directive. Device summary
Watchdog Active-low Activehigh RST input RST(1) Manual reset input(1) Battery Power-fail switchcomparator over Chipenable gating Battery freshness seal SSOP8 3 x 3 (DS)(1) SO8 (M)
T
1. Contact local ST sales office for availability.
Table 1.
Part number STM690A STM692A STM703 STM704 STM802L/M STM805L STM817L/M STM818L/M STM819L/M
1. All RST and RST outputs are push-pull.
October 2008
Rev 8
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www.st.com 1
Contents
STM690A/692A/703/704/802/805/817/818/819
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 1.1.9 1.1.10 MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WD I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RS T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 E . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .9 E CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Push-button reset input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . 13 Watchdog input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . 13 Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chip-enable gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chip-enable input (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chip-enable output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-fail input/output (NOT available on STM818) . . . . . . . . . . . . . . . . 16 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Using a SuperCapTM as a backup power source . . . . . . . . . . . . . . . . . . . 17 Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Battery freshness seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . 18
3 4 5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Contents
6 7 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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List of tables
STM690A/692A/703/704/802/805/817/818/819
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . 38 TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 39 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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STM690A/692A/703/704/802/805/817/818/819
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Logic diagram (STM690A/692/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM690A/692A/802/805/817 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM703/704/819 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STM818 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip-enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chip-enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-fail comparator waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-fail comparator waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . . . . 17 Using a SuperCapTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Freshness seal enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VCC-to-VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VBAT -to-VOUT on-resistance vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset comparator propagation delay vs. temperature (other than STM817/818/819) . . . . 21 Reset comparator propagation delay vs. temperature (VBAT = 3.0 V; STM817/818/819) . 22 Power-up tREC vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 E to ECON on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25C). . . . . . . . . . . . . . . . 25 Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25C). . . . . . . . . . . . . . . . 25 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 29 E to ECON propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 E to ECON propagation delay test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing . . . 38 TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline . . . . . . . . . . . . . . 39
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Description
STM690A/692A/703/704/802/805/817/818/819
1
Description
The STM690A/692A/703/704/802/805/817/818/819 supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM703/704/819) as well as a power-fail comparator (except for STM818) to provide the system with an early warning of impending power failure. These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package. Figure 1. Logic diagram (STM690A/692/802/805/817)
1. For STM805, reset output is active-high. Figure 2. Logic diagram (STM703/704/819)
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STM690A/692A/703/704/802/805/817/818/819 Figure 3. Logic diagram (STM818)
Description
Table 2.
Signal names
MR WDI RST RST E(1) Push-button reset input Watchdog input Active-low reset output Active-high reset outpu Chip-enable input Conditioned chip-enable output Supply voltage output Supply voltage Backup supply voltage Power-fail input Power-fail output Ground
ECON
(1)
VOUT VCC VBAT PFI PFO VSS
1. STM81 8
Figure 4.
STM690A/692A/802/805/817 connections
1. For STM805, reset output is active-high.
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Description Figure 5. STM703/704/819 connections
STM690A/692A/703/704/802/805/817/818/819
Figure 6.
STM818 connections
1.1
1.1.1
Pin descriptions
MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused.
1.1.2
WDI
If WDI remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge. The watchdog function can be disabled by allowing the WDI pin to float.
1.1.3
RST
Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high.
1.1.4
RST
Pulses high for trec when triggered, and stays high whenever VCC is above the reset threshold or when MR is a logic high. It remains high for trec after either VCC falls below the reset threshold, the watchdog triggers a reset, or MR goes from high to low.
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STM690A/692A/703/704/802/805/817/818/819
Description
1.1.5
VOUT
When VCC is above the switchover voltage (VSO), VOUT is connected to VCC through a Pchannel MOSFET switch. When VCC falls below VSO, VBAT connects to VOUT.
1.1.6
VBAT
When VCC falls below VSO, VOUT switches from VCC to VBAT. When VCC rises above VSO + hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used.
1.1.7
E
The input to the chip-enable gating circuit. Connect to ground if unused.
1.1.8
ECON
ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is asserted, ECON will remain low for 15 s or until E goes high, whichever occurs first. In the disabled mode, ECON is pulled up to VOUT.
1.1.9
PFI
When PFI is less than VPFI or when VCC falls below 2.4 V (or VSO), PFO goes low; otherwise, PFO remains high. Connect to ground if unused.
1.1.10
PFO
When PFI is less than VPFI, or VCC falls below 2.4 V (or VSO), PFO goes low; otherwise, PFO remains high. Leave open if unused. Output type is push-pull.
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Description
STM690A/692A/703/704/802/805/817/818/819
Table 3.
Pin description
Pin STM690A STM703 STM704 STM819 6 7 1 2 8 4 5 3 6 7 1 2 8 4 5 3 MR WDI RST RST VOUT VCC VBAT E ECON PFI PFO VSS Push-button reset input Watchdog input Active-low reset output Active-high reset output Supply output for external LPSRAM Supply voltage Backup battery input Chip-enable input Conditioned chip-enable output Power-fail input Power-fail output (push-pull) Ground STM805
STM818
STM692A STM802 STM817
Name
Function
6 7 1 2 8 4 5 3
6 7 1 2 8 4 5 3
Figure 7.
Block diagram (STM690A/692A/802/805/817)
1. For STM805, reset output is active-high.
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STM690A/692A/703/704/802/805/817/818/819 Figure 8. Block diagram (STM703/704/819)
Description
Figure 9.
Block diagram (STM818)
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Description Figure 10. Hardware hookup
STM690A/692A/703/704/802/805/817/818/819
1. For STM690A/692A/802/805/817/818. 2. For STM818 only. 3. Not available on STM818. 4. For STM703/704/819. 5. Active high on STM805.
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STM690A/692A/703/704/802/805/817/818/819
Operation
2
2.1
Operation
Reset output
The STM690A/692A/703/704/802/805/817/818/819 Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM805) for 0V < VCC < VRST if VBAT is greater than 1 V. Without a backup battery, RST is guaranteed valid down to VCC =1 V. During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
2.2
Push-button reset input (STM703/704/819)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 41 on page 32) after it returns high. The MR input has an internal 40 k pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 F capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used.
2.3
Watchdog input (NOT available on STM703/704/819)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD(1.6 sec typ), the reset is asserted. The internal watchdog timer is cleared by either: 1. 2. a reset pulse, or by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse is triggered every 1.8 sec (tWD + trec).
The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure 42 on page 32). Note: 1 The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 A and the maximum allowable load capacitance is 200 pF. Input pulses less than 20 ns will be ignored.
2
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Operation
STM690A/692A/703/704/802/805/817/818/819
2.4
Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices automatically switch the SRAM to the backup supply when VCC falls.
Note:
If backup battery is not used, connect both VBAT and VOUT to VCC . Whenever VCC falls below the switchover voltage, VSO, VOUT is connected to VBAT through a 100 switch. VSO is the lesser of VBAT and VRST. Choosing the lesser allows the device to be powered by VCC for as long as possible before switching over thereby maximizing the battery life. Assuming VBAT > 2.0 V, switchover at VSO ensures that battery backup mode is entered before VOUT gets too close to the 2.0 V minimum required to reliably retain data in most external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO point. VOUT is connected to VCC through a 3 PMOS power switch.
Note:
The backup battery may be removed while VCC is valid, assuming VBAT is adequately decoupled (0.1 F typ), without danger of triggering a reset. Table 4. I/O status in battery backup
VOUT VCC PFI PFO E ECON WDI MR RST RST VBAT Connected to VBAT through internal switch Disconnected from VOUT Disabled Logic low High impedance Logic high Watchdog timer is disabled Disabled Logic low Logic high Connected to VOUT
2.5
Chip-enable gating (STM818 only)
Internal gating of the chip-enable (E) signal prevents erroneous data from corrupting the external CMOS RAM in the event of an undervoltage condition. The STM818 uses a series transmission gate from E to ECON (see Figure 11 on page 15). During normal operation (reset not asserted), the E transmission gate is enabled and passes all E transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short propagation delay from E to ECON enables the STM818 to be used with most Ps. If E is low when reset asserts, ECON remains low for typically 15 s (or until E goes high) to permit the current WRITE cycle to complete. Connect E to VSS if unused.
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STM690A/692A/703/704/802/805/817/818/819
Operation
2.6
Chip-enable input (STM818 only)
The chip-enable transmission gate is disabled and E is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC passes the reset threshold, the chip-enable transmission gate disables and E immediately becomes high impedance if the voltage at E is high. If E is low when reset asserts, the chip-enable transmission gate will disable 15 s after reset asserts (see Figure 12 on page 15). This permits the current WRITE cycle to complete during power-down. Any time a reset is generated, the chip-enable transmission gate remains disabled and E remains high impedance (regardless of E activity) for the reset time-out period. When the chip-enable transmission gate is enabled, the impedance of E appears as a 40 resistor in series with the load at ECON. The propagation delay through the chip-enable transmission gate depends on VCC, the source impedance of the drive connected to E, and the loading on ECON. The chip-enable propagation delay is production tested from the 50% point on E to the 50% point on ECON using a 50 driver and a 50 pF load capacitance (see Figure 39 on page 31). For minimum propagation delay, minimize the capacitive load at ECON and use a low-output impedance driver.
2.7
Chip-enable output (STM818 only)
When the chip-enable transmission gate is enabled, the impedance of ECON is equivalent to a 40 resistor in series with the source driving E. In the disabled mode, the transmission gate is off and an active pull-up connects ECON to VOUT (see Figure 11 on page 15). This pull-up turns off when the transmission gate is enabled.
Figure 11. Chip-enable gating
Figure 12. Chip-enable waveform
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Operation
STM690A/692A/703/704/802/805/817/818/819
2.8
Power-fail input/output (NOT available on STM818)
The Power-fail Input (PFI) is compared to an internal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 10 on page 12) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the STM690A/692A/703/704/802/805/817/818/819 Supervisor or before the microprocessor drops below the minimum operating voltage. This provides several milliseconds of advanced warning that power is about to fail. During battery backup, the power-fail comparator turns off and PFO goes (or remains) low (see Figure 13 below and Figure 14 on page 17). This occurs after VCC drops below 2.4 V (or VSO). When power returns, PFO is forced high (STM817/819 only), irrespective of VPFI for the WRITE protect time (trec). At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. PFO may be connected to MR on the STM703/704/818 so that a low voltage on PFI will generate a reset output.
2.9
Applications information
These Supervisor circuits are not short-circuit protected. Shorting VOUT to ground excluding power-up transients such as charging a decoupling capacitor - destroys the device. Decouple both VCC and VBAT pins to ground by placing 0.1 F capacitors as close to the device as possible.
Figure 13. Power-fail comparator waveform (STM817/818/819)
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STM690A/692A/703/704/802/805/817/818/819 Figure 14. Power-fail comparator waveform (STM690A/692A/703/704/802/805)
Operation
2.10
Using a SuperCapTM as a backup power source
SuperCapsTM are capacitors with extremely high capacitance values (e.g., 0.47 F) for their size. Figure 15 shows how to use a SuperCap as a backup power source. The SuperCap may be connected through a diode to the 5 V supply. Since VBAT can exceed VCC while VCC is above the reset threshold, there are no special precautions for using these supervisors with a SuperCap.
2.11
Negative-going VCC transients
The STM690A/692A/703/704/802/805/817/818/819 Supervisors are relatively immune to negative-going VCC transients (glitches). Figure 37 on page 29 shows typical transient duration versus reset comparator overdrive (for which the STM690A/692A/703/704/802/805/817/818/819 will NOT generate a reset pulse). The graph was generated using a negative pulse applied to VCC, starting at VRST + 0.3 V and ending below the reset threshold by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width a negative VCC transient can have without causing a reset pulse. As the magnitude of the transient increases (further below the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive which lies under the curve will NOT generate a reset signal. Typically, a VCC transient that goes 100 mV below the reset threshold and lasts 40 s or less will not cause a reset pulse. A 0.1 F bypass capacitor mounted as close as possible to the VCC pin provides additional transient immunity.
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Operation
STM690A/692A/703/704/802/805/817/818/819
2.12
Battery freshness seal (STM817/818/819)
The battery freshness seal disconnects the backup battery from internal circuitry and VOUT until it is needed. This allows an OEM to ensure that the backup battery connected to VBAT will be fresh when the final product is put to use. To enable the freshness seal: 1. 2. 3. 4. Connect a battery to VBAT Ground PFO Bring VCC above the reset threshold and hold it there until reset is deasserted following the reset timeout period and Bring VCC down again (Figure 16)
Use the same procedure for the STM818, but ground ECON instead of PFO. Once the battery freshness seal is enabled (disconnecting the backup battery from internal circuitry and anything connected to VOUT), it remains enabled until VCC is brought above VRST. Figure 15. Using a SuperCapTM
Figure 16. Freshness seal enable waveform
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STM690A/692A/703/704/802/805/817/818/819
Typical operating characteristics
3
Note:
Typical operating characteristics
Typical values are at TA = 25C.
Figure 17. VCC-to-VOUT on-resistance vs. temperature
Figure 18. VBAT -to-VOUT on-resistance vs. temperature
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Typical operating characteristics Figure 19. Supply current vs. temperature (no load)
STM690A/692A/703/704/802/805/817/818/819
Figure 20. Battery current vs. temperature
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STM690A/692A/703/704/802/805/817/818/819 Figure 21. VPFI threshold vs. temperature
Typical operating characteristics
Figure 22. Reset comparator propagation delay vs. temperature (other than STM817/818/819)
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Typical operating characteristics
STM690A/692A/703/704/802/805/817/818/819
Figure 23. Reset comparator propagation delay vs. temperature (VBAT = 3.0 V; STM817/818/819)
Figure 24. Power-up tREC vs. temperature
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STM690A/692A/703/704/802/805/817/818/819 Figure 25. Normalized reset threshold vs. temperature
Typical operating characteristics
Figure 26. Watchdog time-out period vs. temperature
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Typical operating characteristics Figure 27. E to ECON on-resistance vs. temperature
STM690A/692A/703/704/802/805/817/818/819
Figure 28. PFI to PFO propagation delay vs. temperature
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STM690A/692A/703/704/802/805/817/818/819
Typical operating characteristics
Figure 29. Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25C)
Figure 30. Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25C)
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Typical operating characteristics Figure 31. RST output voltage vs. supply voltage
STM690A/692A/703/704/802/805/817/818/819
Figure 32. RST output voltage vs. supply voltage
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STM690A/692A/703/704/802/805/817/818/819 Figure 33. RST response time (assertion)
Typical operating characteristics
Figure 34. RST response time (assertion)
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Typical operating characteristics
STM690A/692A/703/704/802/805/817/818/819
Figure 35. Power-fail comparator response time (assertion)
Figure 36. Power-fail comparator response time (de-assertion)
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Typical operating characteristics
Figure 37. Maximum transient duration vs. reset threshold overdrive
Figure 38. E to ECON propagation delay vs. temperature
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Maximum ratings
STM690A/692A/703/704/802/805/817/818/819
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5.
Symbol TSTG TSLD(1) VIO VCC/VBAT IO PD
Absolute maximum ratings
Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation Value 55 to 150 260 0.3 to VCC +0.3 0.3 to 6.0 20 320 Unit C C V V mA mW
1. Reflow at peak temperature of 255C to 260C for < 30 seconds (total thermal budget not to exceed 180C for between 90 to 150 seconds).
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STM690A/692A/703/704/802/805/817/818/819
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the measurement conditions summarized in Table 6: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 6. Operating and AC measurement conditions
Parameter VCC/VBAT supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages STM690A/692A/703/704/802/805/ 817/818/819 1.0 to 5.5 40 to 85 5 0.2 to 0.8VCC 0.3 to 0.7VCC Unit V C ns V V
Figure 39. E to ECON propagation delay test circuit
1. CL includes load capacitance and scope probe capacitance.
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DC and AC parameters
STM690A/692A/703/704/802/805/817/818/819
Figure 40. AC testing input/output waveforms
Figure 41. MR timing waveform
1. RST for STM805.
Figure 42. Watchdog timing
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DC and AC parameters
Table 7.
Sym VCC , VBAT(2) ICC
DC and AC characteristics
Alternative Description Operating voltage VCC supply current VCC supply current in battery backup mode VBAT supply current in battery backup mode Test condition(1) TA = 40 to +85C Excluding IOUT (VCC < 5.5 V) Excluding IOUT (VBAT = 2.3 V, VCC = 2.0 V, MR = VCC) Excluding IOUT (VBAT = 3.6 V) IOUT1 = 5 mA(5) VCC 0.03 VCC 0.3 VCC 0.0015 VBAT 0.1 Min 1.2(3) 25 25 0.4 VCC 0.015 VCC 0.15 VCC 0.0006 VBAT 0.034 VBAT 0.14 3 100 4.5 V < VCC < 5.5 V 0 V < VIN < VCC WDI = VCC , time average WDI = GND, time average 4.5 V < VCC < 5.5 V VRST (max) < VCC < 5.5 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 5.5 V VCC = VRST (max), ISINK = 3.2 mA VCC = VRST (max), IOUT = 1.6 mA, E = 0 V ISINK = 50 A, VCC = 1.0 V, VBAT = VCC , TA = 0C to 85C ISINK = 100 A, VCC = 1.2 V, VBAT = VCC 20 2.0 0.7VCC 0.8 0.3VCC 0.3 0.2VCC 0.3 0.3 75 25 125 2 120 15 300 +25 160 4 Typ Max 5.5 60 35 1.0 Unit V A A A V V V V V A nA A A V V V V V V V V
IBAT(4)
VOUT1
VOUT voltage (active)
IOUT1 = 75 mA IOUT1 = 250 A, VCC > 2.5 V(5)
VOUT2
VOUT voltage (battery backup)
IOUT2 = 250 A, VBAT = 2.3 V IOUT2 = 1 mA, VBAT = 2.3 V
VCC to VOUT on-resistance VBAT to VOUT on-resistance Input leakage current (MR) ILI Input leakage current (PFI) Input leakage current (WDI)(6) VIH VIH VIL VIL Input high voltage (MR) Input high voltage (WDI) Input low voltage (MR) Input low voltage (WDI) Output low voltage (PFO, RST, RST) VOL Output low voltage (ECON)
VOL
Output low voltage (RST)
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DC and AC parameters Table 7.
Sym
STM690A/692A/703/704/802/805/817/818/819
DC and AC characteristics (continued)
Alternative Description Output high voltage (RST, RST) Test condition(1) ISOURCE = 1 mA VCC = VRST (max) VCC = VRST (max), IOUT = 1.6 mA, E= VCC ISOURCE = 75 A, VCC = VRST (max) ISOURCE = 4 A, VCC = 1.1 V, VBAT = VCC , TA = 0C to 85C ISOURCE = 4 A, VCC = 1.2 V, VBAT = VCC VOH battery backup (RST, RST) ISOURCE = 100 A, VCC = 0, VBAT = 2.8 V ISOURCE = 75 A, VCC = 0, VBAT = 2.8 V 0.8VBAT 0.8VBAT Min Typ Max Unit
2.4 0.8VCC 0.8VCC 0.8 0.9
V V V V V V V
VOH
Output high voltage (ECON) Output high voltage (PFO)
VOH
Output high voltage
VOHB
VOH battery backup (ECON)
Power-fail comparator (NOT available on STM818) PFI falling (VCC = 5 V) All other versions STM802 tPFD ISC PFI to PFO propagation delay PFO output short to GND current VCC = 5 V, VPFO = 0 V 0.1
1.20 1.225
1.25 1.250 2 0.75
1.30 1.275
V V s
VPFI
PFI input threshold
2.0
mA
Battery switchover Batter y backup switchover voltage(7) (8) (VCC < VBAT & VCC < VRST) Hysteresis Reset thresholds VRST Reset threshold(9) Reset threshold hysteresis VCC to RST delay (from VRST, VCC falling at 10 V/ms) STM817/818/819 STM690A/703, STM8XXL STM692A/704, STM8XXM 4.50 4.25 4.65 4.40 25 4.75 4.50 V V mV Power-down VRST > VBAT VRST < VBAT Power-up VRST > VBAT VRST < VBAT VBAT VRST VBAT VRST 40 V V V V mV
VSO
100
s
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STM690A/692A/703/704/802/805/817/818/819 Table 7.
Sym tREC
DC and AC parameters
DC and AC characteristics (continued)
Alternative Description RST pulse width Test condition(1) Min 140 Typ 200 Max 280 Unit ms
Push-button reset input (STM703/704/819) STM703/704 tMLMH tMR MR pulse width STM819 STM703/704 tMLMR tMRD MR to RST output delay STM819 MR glitch immunity MR pull-up resistor STM819 MR = 0 V, VCC = 5 V 45 120 100 63 85 ns ns k 1 250 s ns 150 ns
Watchdog timer (NOT available on STM703/704/819) tWD Watchdog timeout period WDI pulse width Chip-enable gating (STM818 only) E-to-ECON resistance E-to-ECON propagation delay Reset-to-ECON high delay ECON short circuit current VCC = VRST (max) 4.5 V < VCC < 5.5 V (Power-down) VCC = 5 V, disable mode, E = logic high, ECON = 0 V 0.1 40 2 15 0.75 2.0 150 7 ns s mA VRST (max) < VCC < 5.5 V VRST (max) < VCC < 5.5 V 1.12 50 1.60 2.24 s ns
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 4.75 V to 5.5 V for "L" versions; VCC = 4.5 V to 5.5 V for "M" versions; and VBAT = 2.8 V (except where noted). 2. VCC supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality, state of RST and RST tested at VBAT = 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC (min). Either VCC or VBAT can go to 0 V if the other is greater than 2.0 V. 3. VCC (min) = 1.0 V for TA = 0C to +85C. 4. Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V. 5. Guaranteed by design. 6. WDI input is designed to be driven by a three-state output device. To float WDI, the "high impedance mode" of the output device must have a maximum leakage current of 10 A and a maximum output capacitance of 200 pF. The output device must also be able to source and sink at least 200 A when active. 7. When VBAT > VCC > VRST, VOUT remains connected to VCC until VCC drops below VRST. 8. When VRST > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) 75 mV. 9. For VCC falling.
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Package mechanical data
STM690A/692A/703/704/802/805/817/818/819
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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STM690A/692A/703/704/802/805/817/818/819
Package mechanical data
Figure 43. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing
T
Note:
Drawing is not to scale. able 8. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data
mm Symbol Typ A A1 B C D ddd E e H h L N 1.27 Mi n 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 0 8 Max 1.75 0.25 0.51 0.25 5.00 0.10 4.00 6.20 0.50 0.90 8 Typ 0.050 Min 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.010 0.016 0 8 Ma x 0.069 0.010 0.020 0.010 0.197 0.004 0.157 0.244 0.020 0.035 8 inches
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Package mechanical data
STM690A/692A/703/704/802/805/817/818/819
Figure 44. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
T
Note: able 9.
Symbol
Drawing is not to scale. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data
mm Typ A A1 A2 b c CP D e E E1 L L1 N 0.85 3.00 0.65 4.90 3.00 0.55 0.95 Mi n 0.05 0.75 0.25 0.13 2.90 4.65 2.90 0.40 0 8 Max 1.10 0.15 0.95 0.40 0.23 0.10 3.10 5.15 3.10 0.70 6 Typ 0.034 0.118 0.026 0.193 0.118 0.022 0.037 inches Min 0.002 0.030 0.010 0.005 0.114 0.183 0.114 0.016 0 8 Max 0.043 0.006 0.037 0.016 0.009 0.004 0.122 0.203 0.122 0.030 6
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STM690A/692A/703/704/802/805/817/818/819
Part numbering
7
Part numbering
Table 10.
Example:
Ordering information scheme
STM690A M 6 E
Device type STM690A/692A/703/704/802/805/817/818/819
Threshold voltage STM690A, STM703: blank: VRST = 4.50 V to 4.75 V STM692A, STM704: blank: VRST = 4.25 V to 4.50 V STM8xx: L: VRST = 4.50 V to 4.75 V M: VRST = 4.25 V to 4.50 V
Package M = SO8 DS(1) = TSSOP
Temperature range 6: 40C to 85C
Shipping method E = ECOPACK package, tubes F = ECOPACK package, tape & reel
1. Contact local ST sales ofice for availability
For other options or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Part numbering
STM690A/692A/703/704/802/805/817/818/819
Table 11.
Marking description
Reset threshold 4.65 V 4.40 V 4.65 V 4.40 V 4.65 V 4.40 V 4.65 V 4.65 V TSSOP8 SO8 Package SO8 SO8 SO8 SO8 SO8 SO8 SO8 SO8 Topside marking 690A 692A 703 704 802L 802M 805L 817L
Part number STM690A STM692A STM703 STM704 STM802L STM802M STM805L STM817L
STM817M
4.40 V TSSOP8 SO8
817M
STM818L
4.65 V TSSOP8 SO8
818L
STM818M
4.40 V TSSOP8 SO8
818M
STM819L
4.65 V TSSOP8 SO8
819L
STM819M
4.40 V TSSOP8
819M
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Revision history
8
Revision history
Table 12.
Date Oct-2003 31-Oct-2003 22-Dec-2003 16-Jan-2004 08-Apr-2004 25-May-2004 05-Jul-2004 29-Sep-2004 01-Mar-2005 20-Jan-2006 21-Oct-2008
Document revision history
Revision 1 1.1 2 2.1 2.2 3 4 5 6 7 8 Initial release. Update DC characteristics (Table 7). Reformatted; updated characteristics (cover page, Figure 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, Table 3, 4, 7, 9, 11). Add typical characteristics (Figure 18, 19, 21, 22, 24, 25, 26, 27, 28, 31, 32, 33, 34, 35, 36, 37, 38). Update characteristics (Figure 12, 22, 28, 32, 33, 34, 37; Table 1, 7). Remove references to "open drain" (cover page, 4, 7; Table 2); update characteristics (Table 3, 7). Update package availability, pin description; promote document (cover page, Figure 13, 14; Table 3, 7, 10). Clarify root part numbers, pin descriptions (Figure 10, 12, 39; Table 7, 10). Update characteristics (Figure 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38) Correct marking, update lead-free text (Table 10, 11) Reformatted, minor text changes; updated Table 3, 4, 7, 10, Figure 9, 10, 11, 12, 16, 39, Section 6: Package mechanical data. Changes
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