STL50NH3LL
N-channel 30 V - 0.011 - 13 A - PowerFLATTM (6x5) ultra low gate charge STripFETTM Power MOSFET
Features
Type STL50NH3LL
VDSS 30V
RDS(on) <0.013
ID 13A (4)
Improved die-to-footprint ratio Very low profile package (1 mm max) Very low thermal resistance Very low gate charge Low threshold device
PowerFLATTM( 6x5 )
Applications
Switching application Figure 1. Internal schematic diagram
Description
This application specific Power MOSFET is the latest generation of STMicroelectronics unique "STripFETTM" technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The Chip-scaled PowerFLATTM package allows a significant board space saving, still boosting the performance.
Table 1.
Device summary
Order code STL50NH3LL Marking L50NH3LL Package PowerFLATTM (6x5) Packaging Tape & reel
December 2007
Rev 10
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www.st.com 12
Contents:
STL50NH3LL
Contents:
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . .. . .. . .. . .. . .... 6
3 4 5
Test circuit
. . .. . .. . .. . .. . .. . .. . .. . .. . .... 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STL50NH3LL
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS(1) VGS(2) ID(3) ID(4) IDM ID
(5) (4)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC=100C Drain current (pulsed) Drain current (continuous) at TC = 25C Total dissipation at TC = 25C Total dissipation at TC = 25C Derating factor Value 30 16 18 27 8.1 108 13 4 60 0.03 -55 to 150 Unit V V V A A A A W W W/C C
PTOT (4) PTOT
(3)
TJ Tstg
Operating junction temperature Storage temperature
1. Continuous mode 2. Guaranteed for test time < 15ms 3. The value is rated according Rthj-c and is limited by wire bonding 4. The value is rated according Rthj-pcb 5. Pulse width limited by safe operating area
Table 3.
Symbol Rthj-case Rthj-pcb
(1)
Thermal resistance
Parameter Thermal resistance junction-case (Drain) Thermal resistance junction-ambient Value 2.08 31.3 Unit C/W C/W
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec
Table 4.
Symbol IAV EAS
Avalanche data
Parameter Not-repetitive avalanche current Single pulse avalanche energy (star ting Tj=25C, Id=Iav) Value 7.5 150 Unit A mJ
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Electrical characteristics
STL50NH3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 5.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 25 0A, VGS= 0 VDS = Max rating, VDS = Max rating @125C VGS = 16 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 6.5 A VGS= 4.5 V, ID= 6. 5A 1 0.011 0.012 0.013 0.015 Min. 30 1 10
100
Typ.
Max.
Unit V A A nA V
Table 6.
Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions VDS =10 V, ID = 6.5 A VDS =25 V, f=1 MHz, VGS=0 VDD=15 V, ID = 13 A VGS =4.5 V (see Figure 8) f=1 MHz gate DC bias = 0 test signal level = 20 mV open drain Min. Typ. 32 965 285 38 9 3.7 3 12 Max. Unit S pF pF pF nC nC nC
Gate input resistance
0.5
1.5
2.5
1. Pulsed: pulse duration=300 s, duty cycle 1.5%
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STL50NH3LL
Electrical characteristics
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=15 V, ID= 6.5 A, RG=4.7 , VGS=4.5 V (see Figure 14) Min. Typ. 15 32 18 8.5 Max. Unit ns ns ns ns
Table 8.
Symbol ISD ISDM(1) VSD(2) t rr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD=13 A, VGS=0 ISD=13 A, di/dt = 100 A/s, VDD=20 V, Tj=150 C (see Figure 16) 24 17.4 1.45 Test conditions Min. Typ. Max 13 52 1.3 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300 s, duty cycle 1.5%
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Electrical characteristics
STL50NH3LL
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area Figure 3. Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Transconductance
Figure 7.
Static drain-source on resistance
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STL50NH3LL Figure 8. Gate charge vs. gate-source voltage Figure 9.
Electrical characteristics Capacitance variations
Figure 10. Normalized gate threshold voltage vs. temperature
Figure 11. Normalized on resistance vs. temperature
Figure 12. Source-drain diode forward characteristics
Figure 13. Normalized BVDSS vs. temperature
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Test circuit
STL50NH3LL
3
Test circuit
Figure 15. Gate charge test circuit
Figure 14. Switching times test circuit for resistive load
Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit
Figure 18. Unclamped inductive waveform
Figure 19. Switching time waveform
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STL50NH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STL50NH3LL
PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
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STL50NH3LL
Revision history
5
Revision history
Table 9.
Date 21-Jul-2005 14-Apr-2005 20-Jun-2005 22-Jun-2005 30-Sep-2005 04-Jan-2006 30-Mar-2006 27-Jul-2006 06-Sep-2006 11-Dec-2007
Revision history
Revision 1 2 3 4 5 6 7 8 9 10 First Release Final version Updated mechanical data New Rg value on Table 7 Inser ted ecopack indication New footprint New template Updated Figure 2 New template, no content change Updated EAS value on Table 4: Avalanche data Changes
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STL50NH3LL
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