STP16NK65Z STB16NK65Z-S
N-CHANNEL 650V - 0.38 - 13A TO-220 / I2SPAK Zener - Protected SuperMESHTM MOSFET
Table 1: General Features
TYPE STP16NK65Z STB16NK65Z-S
s s s s s s
Figure 1: Package
ID 13 A 13 A Pw 190 W 190 W
VDSS 650 V 650 V
RDS(on) < 0.50 < 0.50
TYPICAL RDS(on) = 0.38 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY
3 12
3 1 2
TO-220
I²SPAK
DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established stripbased PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR OFF-LINE POWER SUPPLIES
Figure 2: Internal Schematic Diagram
Table 2: Order Codes
SALES TYPE STP16NK65Z STB16NK65Z-S MARKING P16NK65Z B16NK65Z PACKAGE TO-220 I²SPAK PACKAGING TUBE TUBE
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Table 3: Absolute Maximum ratings
Symbol VDS VDGR VGS ID ID IDM (*) PTOT VESD(G-S) dv/dt (1) Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate source EDS (HBM-C=100pF, R=1.5k) Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature Value 650 650 30 13 8.19 52 190 1.51 6000 4.5 -55 to 150 Unit V V V A A A W W/C V V/ns C
(*) Pulse width limited by safe operating area (1) ISD 13 A, di/dt 200 A/s, VDD V(BR)DSS,T j T JMAX
Table 4: Thermal Data
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.66 62.5 300 C/W C/W C
Table 5: Avalanche Characteristics
Symbol IAR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max. Value 13 350 Unit A mJ
Table 6: Gate-Source Zener Diode
Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Condition Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied fromgate to source. In this respect the Zener voltage ia appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20 V VDS = VGS, ID = 100 A VGS = 10V, ID = 6.5 A 3 3.75 0.38 Min. 650 1 50 10 4.5 0.50 Typ. Max. Unit V A A A V
Table 8: Dynamic
Symbol gfs (1) Ciss Coss C rs s Coss eq. (*) td(on) tr td(off) tf Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 6.5 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 12 2750 275 60 188 25 25 68 17 89 18 45 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC
VGS = 0V, VDS = 6.5 V to 520 V VDD = 325 V, ID = 6.5 A RG = 4.7 VGS = 10 V (see Figure 17) VDD = 520 V, ID = 13 A, VGS = 10 V (see Figure 20)
Table 9: Source Drain Diode
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 13 A, VGS = 0 ISD = 13 A, di/dt = 100 A/s, VDD = 100 V, Tj = 25C (see Figure 18) ISD = 13 A, di/dt = 100 A/s, VDD = 100 V, Tj = 150C (see Figure 18) 500 5.2 21 615 7 22.5 Test Conditions Min. Typ. Max. 13 52 1.6 Unit A A V ns C A ns C A
(1) Pulsed: Pulse duration = 300s, duty cycle 1.5% (2) Pulse width limited by safe operating area (*) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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Figure 3: Safe Operating Area Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temp e rat u re
Figure 11: Dource-Drain Diode Forward Characteristics
Figure 14: Normalized BVdss vs Temperature
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Figure 15: Avalanche Energy vs Starting Tj j
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Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform
Figure 17: Switching Times Test Circuit For Resistive Load
Figure 20: Gate Charge Test Circuit
Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times
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In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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I2SPAK MECHANICAL DATA
mm. MIN. 4.40 2.49 0.70 1.14 0.45 1.23 8.95 10.00 4.88 16.7 1.27 13.82 TY P MAX. 4.60 2.69 0.93 1.70 0.60 1.36 9.35 10.4 0 5.28 17.5 1.4 14.4 2 MI N. 0.17 3 0.09 8 0.02 7 0.04 5 0.01 8 0.04 8 0.35 2 0.39 4 0.19 2 0.65 7 0.0 5 0.54 4 inch TYP. MAX. 0.1 81 0.1 06 0.0 37 0.0 67 0.0 24 0.0 53 0.3 68 0.4 09 0.2 08 0.6 89 0.0 55 0.5 68
DIM. A A1 B B2 C C2 D E G L L2 L3
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TO-220 MECHANICAL DATA
DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP M AX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. M AX . 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154
øP
Q
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Table 10: Revision History
Date 06-Aug-2004 02-Sep-2004 06-Sep-2005 Revision 1 2 3 Description of Changes First Release. Complete Version Inserted Ecopack indication
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
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