AN2131 APPLICATION NOTE
HIGH POWER 3-PHASE AUXILIARY POWER SUPPLY DESIGN BASED ON L5991 AND ESBT STC08DE150
1. INTRODUCTION This application note deals with the design of a 3Phase auxiliary power supply for 150W dual output SMPS, using the L5991 PWM driver and the STC08DE150 ESBT as main switch. The combination of these ST's parts aims at obtaining a high efficiency solution for high DC input voltage, typical requirement of any three phase application. The L5991 driver is an upgraded version of the UC384X current mode PWM driver. It boasts some very interesting additional features. The necessity to handle both high output power and wide input voltage leads to design a flyback stage working in mixed operation mode: discontinuous and continuous. The continuous current mode introduces a right half plan zero in the loop-transfer function which makes the feedback stabilization difficult; the study on the frequency response, reported in the present document, has been carried out using MATLAB. Furthermore, the slope compensation is implemented and deeply explained. It is necessary to remove sub-harmonic oscillations when the duty cycle is higher than 50%. Finally the experimental results are analyzed to better understand the benefits given by the use of the ESBT in this application. 2. DESIGN SPECIFICATIONS PRELIMINARY REMARKS. AND triangle which drops to zero before the next turnon. In the continuous mode, shown in figure 3, the primary current iT has a front-end step and the characteristic appearance of a rising ramp on a step. During the transistor off time (figure 3), the secondary current has the shape of a decaying triangle sitting on a step with the current still remaining in the secondary at the instant of the next turn-on. There is, therefore, still some energy left in the secondary at the instant of next turn-on. The two modes show significantly different operating properties and usages. The discontinuous mode responds more rapidly and with a lower transient output voltage spike to sudden changes in load current and input voltage. On the other hand, discontinuous mode provides a secondary peak current in the range of two or three times the continuous mode. This can be easily understood by comparing figure 2 and figure 3. The secondary current average value is equal to the DC load current, as reported in both the above mentioned figures. Assuming also closely equal off time, it is obvious that the triangle in the discontinuous mode must show a much larger peak than the trapezoid of the continuous mode to get the same average value. Therefore, in the discontinuous mode, the larger secondary peak current, at the beginning of turn-off, will cause a greater RFI problem. Secondary rms current in the discontinuous mode can be up to twice that in the continuous mode. This requires larger secondary wire size and output filter capacitors with larger ripple current ratings for the discontinuous mode. Rectifier diodes will also have a higher temperature rise in the discontinuous mode because of the larger secondary rms current. Primary peak currents for the discontinuous mode are about twice those in the continuous mode. As a result, the discontinuous mode requires a higher current rating and possibly a more expensive power transistor. Also, the higher primary current in the discontinuous mode results in a greater RFI problem. Despite all these relative disadvantages, the discontinuous mode is much more used for low
Rev. 1 March 2005 1/27
The table 1 lists the converter specification data and the main parameters fixed for the demo board. If we look at the specs, particularly at the power and at the input voltage range, and after a brief description of the differences between continuous and discontinuous mode, it will soon be clear that it is very difficult and not convenient to design a flyback converter working in discontinuous mode. Figure 1 shows a simplified schematic diagram of a flyback converter. The discontinuous mode, shown in figure 2, has no front-end step in its primary current, iT, and at turn-off, the secondary current iD, is a decaying
AN2131 - APPLICATION NOTE
power applications. This is due to two reasons. Firstly, as mentioned above, the discontinuous mode, with an inherently lower transformer magnetizing inductance, responds more quickly and with a lower transient output voltage spike to rapid changes in output load current or input voltage. Secondly, because the transfer function of the continuous mode has a right half plane zero, the error amplifier bandwidth must be drastically reduced to stabilize the feedback loop. As a consequence, the transient response is much slower. Finally, referring to the power spec of our demo, it is clear that the discontinuous mode cannot be used because it would determine a very high primary and secondary peak current with a higher cost of all the main components involved: power transistor, secondary diode and output capacitor.
Table 1. Converter Specification data and Fixed Parameters Symbol
Vinmin Vinmax Vout1 Vout2 Vaux Pout F F sb Vspike
Description
Rectified minimum Input voltage Rectified maximum Input voltage Output voltage 1 Output voltage 2 Auxiliary Output voltage Maximum Output Power Converter Efficiency Switching frequency Stand-by switching frequency Max over voltage limited by clamping circuit
Values
250 850 24V/6.25A 5V/0.075A 15V/0.01A 150W >75% 90 kHz 35 kHz 200V
Figure 1. Simplified Schematic Diagram of a Flyback Converter
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Figure 2. Discontinuous Mode Flyback Waveforms
Figure 3. Continuous Mode Flyback Waveforms
IT
Ton Ts t
ID
Toff t
Vin+Vfly
VT
t
3. FLYBACK CONTINUOS MODE WITH L5991 The minimization of the power drawn from the mains under light load conditions (Stand-by, Suspend or some other idle modes) is an issue that has recently become of great interest, mainly
because new and more severe standards are coming into force. The key point of this strategy is a low switching frequency. It is well-known that many of the power loss sources in a lightly loaded flyback waste energy proportionally to the switching frequency, hence this should be reduced as much as possible. On the other hand, it is equally well-
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known that a low switching frequency leads to bigger and heavier magnetics and makes filtering more troublesome. It is then advisable to make the system operate at high frequency under nominal load condition and to reduce the frequency when the system works in a low-consumption mode. This requires a special functionality of the controller. It should be able to automatically recognize the condition of light or heavy load and then adequate its operating frequency accordingly. The L5991 PWM controller, with its "Stand-by function", meets exactly this requirement. This application note will deal with the design of a flyback using L5991 PWM driver, while deeper details about the driver itself can be found in the dedicated application note AN1049. The specifications table reports the two values of the switching frequency, 90kHz for normal mode and 35kHz for stand-by mode. 4. FLYBACK STAGE DESIGN The continuous mode operation, as any switching topology, is identified by observing the steady state behavior of the energy storage component. In the flyback topology, the storage element is represented by the magnetization transformer inductance, which is charged by the primary winding during the on time, and discharged by the secondary winding during the off time. The flyback topology will hence be working in continuous mode if the secondary winding current does not reach zero at the end of the off time. As previously said, the mixed mode implies a discontinuous mode operation for low load and/or higher input voltage. The boundary depends on the output power for a given input voltage. The higher is the input voltage the higher is the output power when the continuous mode starts. Theoretically, there isn't any restriction to fix the boundary between continuous and discontinuous mode. It will be given by imposing design equation for others relevant circuit parameters. The maximum duty cycle, that in a discontinuous mode flyback is imposed to prevent the continuous mode operation, in this case must be fixed establishing a good trade-off between primary and secondary side performance. There are two opposite effects: by increasing the duty cycle the rms current at primary side can be reduced, while the rms current at secondary side will be increased. This means that a higher duty cycle imposes a less stressful condition to any parts in the primary path, and a more stressful condition to the secondary path. In the same way, to decrease the duty cycle causes an optimization of secondary side and a deterioration of primary side performances. The higher duty cycle is a further help to easily design the flyback stage for a wide range voltage input. On the other hand, the higher duty cycle implies a higher reflected voltage to promptly demagnetize the flyback transformer. For such a high power flyback stage, an important parameter to monitor is the current ripple at secondary side; it is needed either to lower rms current or to reduce RFI. Further consideration concerns the reflected flyback voltage which is imposed in order not to overcome the maximum breakdown of the power switch. The above consideration plus some cost issues generate a clear figure of how to impose design equations. Moreover, since design specifications imply a high power output only, the following calculation will consider the influence of both low power and auxiliary outputs negligible. In continuous operation mode the relationship between input and output voltage is only dependent on the duty cycle and not on the frequency. The relationship is given by the following formula:
VOut 1 N S1 D = Vin NP 1- D
Eq. 1
Eq. 1 is ideal and does not take into consideration real effects such as the voltage drops on the power switch and on the output diode. Including these two voltage drops it is possible to get the first design equation and calculate the turn ratio between input and the higher power output (Vout1).
Vin - Vcs on NP D = N S1 Vout1 + Vd 1 fw 1 - D
E q. 2
Where, V CSon and Vd1fw are respectively the voltage drop on the power switch and on the secondary side diode. Eq. 2 is valid for any input voltage. The second design equation comes from the maximum power switch breakdown, defining first Vfly, the flyback reflected voltage, and then calculating the maximum switch breakdown voltage.
V fly =
NP (Vout1 + Vd1 fw ) N S1
E q. 3
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Eq. 4 also includes the safe design margin and the allowed voltage spike fixed by clamping network design. By combination of Eq. 3 and Eq. 4, the maximum primary/secondary turn ratio is finally obtained.
BV - Vspike - Vin max - m arg in NP N S1 V Out1 + V d 1 fw
For 150W power output, the proposed power switch is STC08DE150, with BV=1500V. Assuming Vspike=200V, margin=200V and Vd1fw=1V. From Eq. 5 results:
NP 10 N S1
From Eq. 2, imposing Vin=Vinmin=220V, Np/Ns = 10, and considering the normal mode switching frequency, the maximum duty cycle and the maximum on time are:
It is worth noticing that the value of the duty cycle calculated by Eq. 7 is a good trade-off to optimize both primary and secondary side performances. By the way, it must be pointed out that being Dmax>50%, slope compensation may be necessary. This subject will be deeply analyzed in paragraph 7. Once fixed the turn ratio between input and the higher power output, the flyback reflected voltage is fixed by Eq. 3 as well.
V fl y =
NP (Vout1 + Vd 1 fw ) = 250V N S1
It is now possible to calculate the two turn ratios referred to the slave Vout2 and to the auxiliary out put s .
NP Vfly = = 33 N S2 Vout 2 + Vd fw
Dmax = 52.8%
Ton max = 5.87 s
V fly BV - V spike - Vin max - m arg in
E q. 5
E q. 6
The next transformer design step is to fix the primary and/or secondary magnetization inductances. There are several criteria: the first one is to select the primary inductance in order to ensure continuous mode operation from full load to minimum load. This method, since a bigger primary magnetization inductance is requested, assures a very low output current ripple, increasing transformer primary turns. Furthermore, it makes the RHP zero lower, so that the loop stabilization will be more complicated. The second alternative criterion is to calculate primary and secondary inductances by defining maximum secondary ripple current. This last method fixes a limit for the rms current and does not require such a high primary magnetization inductance, but it may lead to a transition mode operation.
E q. 7
Eq. 8
E q. 9
BV = V fly + V spike + Vin max + m arg in
E q. 4
NP Vf ly = 15.8 = N aux Vaux + Vd fw
Eq. 10
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Figure 4. Waveforms and Nomenclature of the Continuous Mode Flyback Design
Ipcs Ips
Ip
Ton
Is1
VT
Figure 4 reports the most significant waveforms and relevant nomenclature to further proceed in the flyback design. From figure 4, we define IPCS the primary average current value and IPS the primary current variation during the on time, I S1CS the secondary average current value and IS1 the secondary current variation during the off time and IOut1 the secondary average current. By adopting the second design method, we now fix the maximum secondary ripple current s% in the following equations:
I S 1 max = 2 I S I S 1CS = 2 I S
I Out1 max Eq. 11 1 - Dmax
where s1max is the maximum secondary current variation and s is the ripple current. Therefore we have:
LS 1
(V =
Out1
- Vd fw ) (TS - TON max ) I S !max
Eq. 12
where L S1 is the secondary magnetization inductance. Imposing s%= 30% from Eq. 11 and Eq. 12 results:
L S 1 = 16.17 H
Eq. 13
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NP LP = N S1
2
LS1 = 1617 H
Eq. 14
= 1.08 A
= D max Ip pk Ipcs -
Eq. 18
while the primary magnetization inductance is:
Ts
Is1
t
Is1cs Iout1
Toff
Vin+Vfly
t
t
Once fixed turn ratios and the primary inductance value, some extra calculation is needed to choose either the transformer or the external components for flyback stage. Since design specifications request one high power output only, while the slave and the auxiliary outputs need a very small power, for designing the transformer we can only consider a single output. Based on this supposition the relevant design parameters are here below reported. Fixed N p/N s = 10 and Lp = 1.6 mH. Primary Winding:
I p =
(Vin min - Vcs o n ) * Ton max = 0.8 A Eq. 15 Lp
Po max = 1.48 A Eq. 16 - Vcson ) D max
Ipcs =
(Vin min
Ip pk = Ipcs +
Ip rms =
Ip = 1.88 A 2
Eq. 17
I P I 1 + Ip pk - Ipcs - P 2 3 2
2
=
AN2131 - APPLICATION NOTE
Master Secondary Winding: Figure 5. The Proportional Driving Schematic and its Equivalent Circuit Eq. 19
Is1CS =
I Out1 max = 13.24 A 1 - D max
Is1 =
(Vout1 + Vd FW ) (T - TON max ) = 9.7 A Eq. 20 Ls1
Is1pk = Is1CS +
Is1 = 18.9 A 2
Eq. 21
Is1rms =
=
Is1 pk Is1cs -
= 9.29 A
Above calculation have been made considering a continuous mode operation. This condition is assured by imposing Is%< 100%. According to the reported design parameters, the transformer has been designed by Cramer and all remaining power parts have been chosen as reported in ST's application note AN1889. The driving network guarantees a zone with fixed IC/IB ratio that results imposed once the current transformer turn ratio has been chosen. From the ESBT STC08DE150 datasheet, and in particular looking at the storage time characterization, it is clear that a turn ratio equal to 5 is a good value to ensure the right saturation of ESBT at I c = 2A, so that in the current transformer we can fix at first:
5. BASE DRIVING CIRCUIT DESIGN In practical applications, such as SMPS, where the load is variable, the collector current is variable as well. As a consequence, it is very important to provide a base current to the device which is related to the collector one. In this way, it is possible to avoid the device over saturation at low load and to optimize the performance in terms of power dissipation. The best and simplest way to do this is the proportional driving method provided by the current transformer, in figure 5. At the same time, as already stated, it is very useful to provide a short pulse to the base to make the turn-on as fast as possible and to reduce the dynamic saturation phenomenon. The pulse is achieved by using the capacitor and the zener in figure 5.
(1 - Dmax )
Eq. 22
I s1 I 1 + Is1 pk - Is1cs - s1 2 3 2
2
=
NP 1 = NS 5
Eq. 23
The core magnetic permeability of the current transformer has to be as high as possible in order to minimize the magnetization current Im (that is not transferred to the secondary side but only drives the core into saturation). On the contrary, too high a permeability core may lead the core into saturation even with a very small magnetization current. To avoid that it is necessary to increase the number of primary turns and the size of the core as well. On the other hand, if a core with a very small magnetic permeability is chosen, it is possible to reduce the number of primary turns and the core size, but if the permeability is too small we may not have current on the secondary side because almost all the collector current
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becomes magnetization current. As a compromise a ferrite material with a relative permeability in the range of 4500 ÷ 7000 is the best choice. When a ferrite ring with some diameter has been selected, the minimum primary turns is determined to avoid the core saturation from the preliminarily fixed turn ratio N with 0.2. By applying the Faraday's law and imposing the maximum flux Bmax equals to Bsat/2: adjusted to get the desired IC/IB ratio according to the equation below:
N eff =
I P I C max - I M max = IC IB 5
Eq. 28
Where, Bsat is the saturation flux of the core and it depends on the magnetic permeability. During the conduction time, the junction baseemitter of ESBT can be seen as a forward biased diode. To complete the secondary side load loop the voltage drop on both diode D and resistor RB must be added in series with the base of the ESBT. The equivalent secondary side voltage source is given by:
V S = V BEon + V D + V RB 2.5V
Since the magnetization inductance cannot be neglected, only IP, a fraction of the total collector current, will be transferred to the secondary. As a result, the magnetization current has to be first as low as possible. Meanwhile, the value of the magnetization inductance must be taken into account for a proper calculation of transformer primary turns and turns ratio. The magnetization voltage drop, that is, the voltage at the primary of the current transformer, can be now easily calculated:
V1 = VS N1T 1 = 2.5 = 0.5 N 2T 5
[V ]
The magnetization current will be:
I M max =
V1TON max LTP
The number of primary turns should be increased if I Mmax is relatively high. But the core must have window area enough to hold all primary and secondary windings. Otherwise it is necessary to choose a bigger core size. Once both core material and size are fixed, the turn ratio must be
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V1 = N TP
d B N TP Ae dt t
N TP = 2
V1 Ton max Ae Bsat
Eq. 24
where I Mmax is the maximum magnetization current. The insulation between primary and secondary should be considered since the voltage on the primary side during the off time can overstep 1500V . Next step is to select the zener diode, the capacitor C b and the resistor Rb. The turn-on performance of ESBT is related to the initial base peak current and its duration tpeak that is approximately given by:
t peak = 3 Rb Cb
Eq. 29
Eq. 25
A suitable value for R b is 0.56. It can eliminate the ringing on the base current after the peak, and at the same time, it generates negligible power dissipation. The value t peak can be determined once the minimum on time is set based on the operation frequency. Bear in mind that in practical applications it should never be lower than 200ns. The value of Cb can be counted since the values of tpeak and Rb are known. Ipeak must be limited in order to avoid an extra saturation of the device. This action is made by the zener diode Dz that clamps the voltage across the small capacitor Cb. The zener must be chosen according to the following empirical formulas and inside the range of VZmin and V Zmax:
VZ max = 2 I peak Rb + 1
VZ min = 2 I peak Rb
(
)
Eq. 30
Eq. 26
(
)
Eq. 27
The base peak current will be higher with higher clamp voltage (Dz) or smaller capacitance (Cb), which in turn will lead to a shorter duration of the peak time. The higher and longer the base peak current, the lower the power dissipation during turn-on. But you need to limit the Ib peak both in terms of amplitude and time duration otherwise at low load a very high saturation level may result. If the device is over-saturated the storage time is too long with higher power dissipation during turn-off. Moreover a long storage time can also cause output oscillation especially at high input voltage.
AN2131 - APPLICATION NOTE
To overcome the above mentioned problems it is recommended to fix the peak duration to 1/3 the minimum duty cycle. 6. CONTINUOS STABILIZATION CURRENT MODE LOOP impossible to compensate and therefore must be kept well beyond the closed-loop bandwidth. As a result, the transient response of such system will be not extremely fast. Considering now, the transfer function in the following form:
G1 ( s) =
v out1 ( s) = k1 v comp ( s)
1-
1-
v ( s) N R (1 - D ) = G1 ( s) = out1 vcomp ( s) 3 RS (1 + D) N R(1 - D ) sCR 1+ 1+ D
2 2
1-
s p11
where N = N p/N s, R is the load, RC is the electrolytic capacitor series resistance. It is worth noticing that the transfer function has one pole and two zeros, whose one on the right half plane. The RHP zero is very difficult if not
(1 + sCRC ) 1 -
sL p D
Eq. 31 Substituting the values of this design in case of low input voltage (worst case), we obtain the frequency response reported in the following figure 6. Poles and zeros are reported in the below equations: P11= -202/rad=-32.1Hz Z11= -23Krad/s=-3.79KHz Z12= 88Krad/s=14.1KHz Eq. 33
It is well known from literature that the transfer function of the continuous current mode (CCM) flyback converter is given by:
s z11
s z12
Eq. 32
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Figure 6. Flyback Frequency Response at Minimum Input Voltage
A good line and load regulation implies a high DC gain, thus the open loop gain should have a pole at the origin. Normally, in this case we need a feedback network like the one in figure 7. Its transfer function is given by:
To properly design the feedback loop, let us consider first the following transfer function and its bode plots (figure 8):
G1 (s )
G2 ( s) =
vcomp ( s ) v out ( s )
=
CTRmax RCOMP 1 1 + s (RH + R F )C F RB R H C F s 1 + sRCOMP C comp
Eq. 34
1 s
Eq. 36
or:
1-
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s v c om p ( s ) z 21 1 G2 (s) = = k2 s v ou t ( s ) s 1- p 21
Eq. 35
It is preferable that the RHP zero is well beyond the closed loop cut off frequency. To make it, first of all, a gain is needed. Then, from figure 8, a 90 degrees phase margin could be achieved fixing both zero and pole of G2 to cancel respectively pole p11 and zero z21 of G1. In this case, we ideally get a phase margin of 90 degrees with a well defined gain. Observe that a high phase margin, making the system response quite slow, could help avoid undesired frequency changes. By the way, to assure a not too slow transient response, it is advisable to choose about 60 degrees phase margin. Referring to this real case, we can fix both zero and pole in order not to exactly cancel p 11 and z21.
AN2131 - APPLICATION NOTE
According to the previous argument we fix the pole and zero as Eq. 37. P21 = -11.1krad/s = -1.77kHz Z21 = -245rad/s = -39Hz Figure 10 reports the overall open loop transfer function G1*G2. Phase margin is very close to the desired value and it assures a good stability and quite fast Figure 7. Converter Feedback Network Eq. 37 transient response. Finally, it is interesting to check the loop stability for the highest input voltage and maximum output load. Under this condition, the frequency response of the system is shown in figure 11. From figure 12, as expected, the phase margin is higher and hence the system stability margin is improved.
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Figure 8. Flyback Frequency Response at Vinmin Adding a Pole at the Origin
Figure 9. Frequency Response of the Feedback-transfer Function
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Figure 10. Stabilized Open Loop-transfer Function at Minimum Input Voltage
Figure 11. Flyback Frequency Response at Maximum Input Voltage
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Figure 12. Stabilized Open Loop-transfer Function at Maximum Input Voltage
7. SLOPE COMPESATION SUB HARMONIC S SUPPRESSION
FOR
Eq. 38
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The L5991, as many PWM drivers for SMPS, applies a current mode control. This control method keeps the power transistor current peak constant at the needed level to supply the DC load with DC output voltage dictated by the voltage error amplifier. This is equal to keep constant the current peak at secondary side winding. The average current at secondary side is the DC load current and, however, to keep the current peak constant does not mean to keep the average current constant. Because of this, in the unmodified current mode scheme, changes in the DC input voltage will cause momentary changes in the DC output voltage. The output voltage change will be corrected by the voltage error amplifier outer feedback loop, as this is the loop which ultimately sets the output voltage. Again, however, the inner loop, while keeping peak inductor current constant, does not supply the correct average current and output voltage changes again. The effect is then an oscillation which commences at every change in input
voltage and which may continue for some time. The mechanism can be better understood from an examination of the upslope and downslope of the output inductor currents. In figure 13, it can be seen that the average primary side current at low DC input is higher than the high DC input case. This can be seen quantitatively as:
m2 t off dI 2 = Ip -( )= 2 2 m (T - t on ) m2 t o n m 2T = Ip - 2 = Ip - + 2 2 2 I av = I p -
AN2131 - APPLICATION NOTE
Figure 13. Average Primary Side Current at Low and High DC Input Figure 15. Current Disturbance Effects at Duty Cycle >50%
Since the voltage feedback loop keeps the product of Vdcton constant, at lower DC input voltage, where the on time is higher, the average output inductor current Iav is higher, as can be seen from equation 38 and figure 13. Furthermore, since the DC output voltage is proportional to the average, not to the peak, inductor current, as DC input goes down, DC output voltage will go up. DC output voltage will then be corrected by the outer feedback loop and a seesaw action or oscillation will occur. A second problem which generates oscillation in current mode is shown in figures 14 and 15. From these figures, it can be seen that, at a fixed DC input voltage, if for some reason there is an initial current disturbance I1, after a first downslope the current will be displaced by an amount of I2. Figure 14. Current Disturbance Effects at Duty Cycle <50%
Furthermore, if the duty cycle is less than 50% (m2m1) as in figure 15, the output disturbance after one cycle is greater than the input disturbance. This can be seen quantitatively from figure 14. For a small current displacement I1, the current reaches the original peak value earlier in time by an amount dt where dt = I1/m1. On the inductor downslope, at the end of the on time, the current is lower than its original value by an amount I2 where
I 2 = m2 dt = I 1
m2 m1
Eq. 39
Now with m2 greater than m1, the disturbances will continue to grow but eventually will decay, causing an oscillation. Both current-mode problems mentioned above can be corrected as shown in figure 16, where the original, unmodified output of the error amplifier is shown as the horizontal voltage level OP. The scheme for correcting the previous problems (slope compensation) consists of adding a negative voltage slope of magnitude m to the output of the error amplifier. By a proper selection of m in the way discussed below, the inductor average DC current can be made independent of the power transistor on time. This corrects the problems indicated in both equations 38 and 39. Figure 17 shows the upslope m1 and the downslope of the output inductor current. Remember that in current mode, the power transistor on time starts at every clock pulse and ends at the instant the output of the PWM comparator reaches equality with the output of the voltage error amplifier as shown in figure 16.
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Figure 16. PWM with Current Mode Control
Figure 17. Implementation of Slope Compensation
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In slope compensation, a negative voltage slope of magnitude m=dVea/dt starting at clock time is added to the error amplifier output. The magnitude of m is, therefore, calculated. In figure 17, the error-amplifier output at any time ton after a clock pulse is This, then, corrects the two above mentioned problems arising from the fact that without compensation, current mode maintains the peak constant, and not the average, output inductor current. The same effect is obtained by adding a positivegoing ramp to the output of the current-sensing resistor V i and leaving the error-amplifier output voltage unmodified. Adding the positive-going ramp to Vi is simple and is the most usual approach. Let us suppose that the slope of the ramp is dV/dt. When the PWM driver finds the equality of its two inputs, the output terminates the on time. Then Vi+(dV/dt)ton=Vea0 substitute Vi from eq. 41:
V ea = V ea 0 - m t o n
Eq. 40
where V ea0 is the error amplifier output at ton equal to zero. The peak voltage V i across the primary currentsensing resistor R i in figure 16 is
Vi = I pp Ri = I sp
where Ipp and Isp are the primary and secondary currents respectively. But Isp=Isa + dI2/2, where I sa is the average secondary or average output inductor current and dI2, in figure 13, is the inductor current change during the off time (m2toff). Then
Then
I sp = I sa +
Then
m 2 t off 2
= I sa +
m2 (T - t on ) Eq. 42 2
Ns N m Ri I sa + s Ri 2 T + Np Np 2 + t on m dV N s - Ri 2 = Vea 0 dt N p 2
Equating eq. 40 and 41, which is what the PWM comparator does, we obtain
Ns Ns m Ri I sa = Vea 0 + t on Ri 2 - m - Np Np 2 -
Ns m Ri 2 T Np 2
It can be seen in this relation that if
Ns dV m Ri 2 = m = ea 2 Np dt
then the coefficient of the ton term is zero and the average output inductor current is independent of the on time.
Vi =
Ns m Ri I sa + 2 (T - t on ) Np 2
Eq. 43
From the above, it can be seen that if the slope dV/ dt of the voltage added to Vi is equal to (Ns/ Np)Rim2/2, the terms involving ton in the preceding relation vanish and the secondary average voltage Isa is independent of the on time. In the L5991 chip, a positive going ramp starting at every clock pulse is available at the top of the time capacitor (pin 2 in figure 18). The voltage at that pin is:
Eq. 44
Vosc =
V t on t
where V = 2V and t = 0.693*RtCt.
Eq. 45
Ns Ri Np
Eq. 41
Ns m dV t o n = Ve a 0 Ri I sa + 2 (T - t on ) + 2 dt Np
Eq. 46
Eq. 47
Eq. 48
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Figure 18. Slope Compensation by Simple Resistance
As seen in figure 18, a fraction of that voltage whose slope is V/t is added to Vi (the voltage across the current-sensing resistor). That slope is set at (N s/Np)Ri(m2/2) by the R cs, Rslope resistors. Thus in figure 18, since Ri is much less than Rcs, the voltage delivered to the current sensing terminal (pin 13) is:
Figure 19. Slope Compensation by Emitter Follower Stage
Vi +
RCS RCS V Vosc = Vi + t on RCS + R slope RCS + R slope t
Eq. 49
and setting the slope of that added voltage equal to (N s/N p)Ri(m2/2), we obtain
RCS (N / N P )Ri (m2 / 2 ) =S RCS + Rslope V / t
Eq. 50
where V/t = 2/(0.693RtCt). Since R CS + Rslope drain current off the top of the timing capacitor, the operating frequency changes. Then either R CS + Rslope is made large enough so that the frequency change is small or an emitter follower is interposed between pin 2 and the resistors as shown in figure 19.
We choose the second option for two reasons: the first one is due to the fact that it is difficult to avoid frequency changes with typical RCS values. The second reason, related to the L5991 characteristics, is a little bit more complicated and it will be now explained. In our design, after choosing RCS = 1k we have:
RCS (N / N P )Ri (m2 / 2 ) 6.9k =S RCS + Rsl ope V / t
Eq. 51
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AN2131 - APPLICATION NOTE
The closest value available is R slope = 6.8k. Therefore, first of all, to keep the frequencies established originally, the oscillator resistors can be chosen accordingly, and more important, since the valley value of the oscillator is about 1V, we have a voltage shift of: uncertainty when switching from low to high frequency and vice-versa. As explained in the AN1049 the two values can be referred to the current sensing (pin 13) voltage. The upper level is 0.867V while the lower level is 0.367V. If a simple resistance is used to make the slope compensation, a voltage shift is also introduced and its value computed in eq.52 is too high. In fact, to make the system work at low frequency it is necessary to undergo 0.367V and it may happen that the lower frequency is never reached. With the emitter follower of figure 19, besides avoiding any alteration in the oscillator functionality, we get about 0.5V voltage shift respect to pin2, and hence a consequent reduction of the Vi previously calculated. To obtain Vi = 0 and assure the correct behavior of the PWM driver in the SMPS a diode in series with the emitter has been introduced as shown in figure 20.
Vi =
RCS 1 1V = 1V = 128mV RCS + Rslope 1 + 6.8 Eq. 52
As already stated in the previous paragraphs, the PW M driver used in our design has a special feature. We can externally fix two different operating frequencies in order to improve the system power efficiency. As mentioned in both AN1049 and L5991datasheet, the level at which the operating frequency changes is established by Vcomp, the error amplifier output voltage. Two thresholds are used to guarantee a hysteresis, avoiding Figure 20. Final Slope Compensation Schematic
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6 .8 nF /1 25 0V
Vi n 25 0 VD C to 85 0V D C
-t
1
4
1N4 148 T3 4 836 R15 8k2 U1 R16 1 s ync St-b y 22 1k R24 R23 dc -lim dis isen H1 sgn d pgn d ou t vc C8 9 4 70 p F 10 11 12 13 R25 0.56 R26 0 .56 14 15 r ct dc vr ef vfb c omp ss vcc L 59 91A 2 2 R19 + C7 47u F 50V 16 2 1 2k 3 4 5 6 7 8 S TC 08 D E15 0 0.56 R22 Q1 R18
5k6 6k8 R17
3 .9V 3
C1 0 6
8. PROTOTYPE IMPLEMENTATION AND EXPERIMENTAL RESULTS
U2B
4
3
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H2 C13 T1 CSM 39-071B 16 15 D5 3 1.5KE 0 0A 4 D6 7 10 9 S TT H 10 8 STTH10 8 R6 910 k R9 4 D4 C11 + 47u F 25V 5 C12 12 47u F 25V + C16 GND STTH10 2 14 Vin Vout 100 nF C1 7 240 k 0.5 W + C2 220 uF 400 V R8 820 k S TTH 102 T2 D2 .2 2u F D3 1 nF/Y1 R7 820 k 2 40 k 0. 5W R10 1N4 148 D10 STTH10 2 D8 U3 L78 L05 J3 1 2 D7 STTH30 0 2CT 100 0 uF 50V 100 0uF 50V + C14 + C15 D9 J2 1 2 1 0.5W 22 R27 1nF
2 4V @ 6.25A
Figure 21. Prototype Schematic
R2 2 40k 0. 5W + C1 220 uF 400 V R5 910 k R21 47k 2W R3 2 40 k 0 .5W
R4 910 k C9
R20 47k 2W
AN2131 - APPLICATION NOTE
J1
2 1
5V @ 0.05A
R2 8 4k7 1 U2A 2 PC817 1 50 nF U4 TL4 31 AC C18 R29 1 8k R31 2 4k
F1 T1A 10/3 .7A R11 5 6k
R1
D1 R14
NU
R30 2k7
R13 6k8
Q2
PN2222 A
4 70
R12
C3
C4
C5
C6
PC817
1 0nF 1 00nF
3 .3n F
NU
AN2131 - APPLICATION NOTE
The theoretical design has been further improved by bench verification getting the final schematic reported in figure 21. The board has been successfully tested according to design specifications previously reported and additional features have been also verified. D6 Snubber Circuit This topology works both in discontinuous and continuous mode. The output diode turns off at zero current when operating in discontinuous mode after the core is discharged. In continuous mode the diode turns off when Q1 is turned on. At that time there is still current flowing through it and therefore forces a hard turn-off which causes ringing on the reverse recovery. By adding a snubber based on a capacitance higher than the diode junction capacitance and a resistor tuned to the ringing of the leakage inductance and the diode capacitance, the peak reverse voltage spike and the ringing can be minimized. The ringing often causes EMI issues and adds noise to sensitive PWM circuits. Figure 22 shows the diode at 6 amps. The blue waveform is the diode recovery without snubbing, while the green one is the diode recovery after adding the snubber. The resistor dissipates 0.23 watts in this example.
Figure 22. D6 Diode Recovery Time Effects with and without Snubber
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AN2131 - APPLICATION NOTE
Short Circuit During an output overload or short circuit, the primary current ramps up higher and higher. This current is sensed by R8 which is turned into a voltage, filtered by R17 and C10 and fed to pin 13 of U1 (I sense). When this voltage reaches 1 volt the pulse is terminated. This is known as pulse by pulse current limit. The unit is protected against overstressing the main switch and output diode. In other words by choosing R8 we can limit the power of the unit. During short circuit the output power is limited to this value. Depending on the transformer coupling an output short should reflect a lower voltage to the auxiliary voltage supplying the L5991. When this voltage falls below the under voltage lockout of 8.4 volts, the L5991 shuts down and initiates a restart. In most cases because of the insulation in a transformer, it is difficult to achieve such results. As shown in figure 23, when the output is overloaded the transformer voltage falls to about 3 to 4 volts due to the drop of the diode traces and the output inductor. The 24 volts winding has 10 turns and the Vcc one has 6, so the voltage at the transformer pin of Vcc should be around 2.2 volts. The problem is the leakage inductance causing spikes and ringing whose peak charge the Vcc cap. as seen in figure 23 (violet waveform).
Figure 23. Output Waveforms without Short Circuit Protection
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AN2131 - APPLICATION NOTE
By adding a 22uH inductor in series with the Vcc winding and D3 we are able to filter out the spike and ringing to achieve Vcc to collapse below the under-voltage shutdown and re-initiate a start up. In this mode the high-cup mode is reached dissipating less power and keeping the thermal stresses low. By adding a 22uH inductor in series with the Vcc winding and D3 we are able to filter out the spike and ringing to achieve Vcc to collapse below the under-voltage shutdown and re-initiate a start up. In this mode the high-cup mode is reached dissipating less power and keeping the thermal stresses low. The shutdown is shown in the Figure 25 at 300V input. The hiccup mode duty cycle is 45ms on and 370ms off. As the input voltage is increased, the start up through resistors R25 becomes faster decreasing the off time. At 850 volt in the duty cycle is decreased to 50% protecting the power devices. The most meaningful waveforms at different load and input conditions are reported in figures 26, 27, 28, 29.
Figure 24. Output Waveforms with Short Circuit Protection
Figure 25. Hiccup Mode with Short Circuit Protection
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AN2131 - APPLICATION NOTE
Figure 26. Steady State Vin=850V Pout=150W Figure 29. Steady State Vin=250V Pout=150W
Figure 27. Steady State Vin=850V Pout=150W
Figure 28. Steady State Vin=250V Pout=150W
Figure 26, 27, 28, and 29 show the prototype steady state behavior, by reporting the gate voltage (violet waveform), the base current (blue waveform), and the collector current (yellow waveform) signals. The collector voltage signal has been not caught under maximum load condition because the probe parasitic capacitance generates an inner loop noise causing some undesirable oscillations. Of course, safe operation for the ESBTTM in terms of maximum voltage spike on the collector has been also verified. The switching frequency under maximum load condition is about 85Khz. The base current waveform highlights as the ESBTTM storage time is about 600ns, indicating the correct device saturation level and hence its optimal working condition. Next waveforms will show the low load condition where the switching frequency is appreciably reduced to optimize, even in this condition, the power supply efficiency.
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AN2131 - APPLICATION NOTE
Figure 30. Steady State Vin=850V Pout=25W Figure 33. Steady State Vin=250V Pout=25W
Figure 31. Steady State Vin=850V Pout=25W
Figure 30, 31, 32 and 33 show the steady state behavior for the low load condition. In this case the sw itching frequency is about 37KHz, and the collector voltage signal (green waveform) has been added since in this less stressful condition the probe doesn't affect the system stability. From figure 31 is possible to see the very high voltage applied on the collector (1184V) during a normal working condition.
Figure 32. Steady State Vin=250V Pout=25W
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AN2131 - APPLICATION NOTE
9. PCB LAYOUT Figure 34. Prototype PCB Layout
The printed circuit board is reported in figure 34, while the relevant bill of material is listed in the schematic of figure 21. REFERENCES: - STMicroelectronics application note AN1889 "ESBT STC03DE170 IN 3-PHASES AUXILIARY POWER SUPPLY" - STMicroelectronics application note AN1049 "MIN IMIZE POWER LOSSES OF LIGHTLY LOADED FLYBACK CONVERTERS WITH THE L5991 PWM CONTROLLER"
- STMicroelectronics L5991 datasheet - STMicroelectronics STC08DE150 datasheet - Abraham I. Pressman, "Switching Power Supply Design", McGraw-Hill, Inc.
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AN2131 - APPLICATION NOTE
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. T he ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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