TDA2030
14W Hi-Fi AUDIO AMPLIFIER
DESCRIPTION The TDA2030 is a monolithic integrated circuit in Pentawatt package, intended for use as a low frequency class AB amplifier. Typically it provides 14W output power (d = 0.5%) at 14V/4; at 14V or 28V, the guaranteed output power is 12W on a 4 load and 8W on a 8 (DIN45500). The TDA2030 provides high output current and has very low harmonic and cross-over distortion. Fur ther the device incorporates an original (and patented) short circuit protection system comprising an arrangement for automatically limiting the dissipated power so as to keep the working point of the output transistors within their safe operating area. A conventional thermal shut-down system is also included. ABSOLUTE MAXIMUM RATINGS
Symbol Vs Vi Vi Io Ptot Tstg, Tj Supply voltage Input voltage Differential input voltage Output peak current (internally limited) Power dissipation at Tcase = 90C Stoprage and junction temperature Parameter
Pentawatt
ORDERING NUMBERS : TDA2030H TDA2030V
Value 18 (36) Vs 15 3.5 20 -40 to 150
Unit V V A W C
TYPICAL APPLICATION
June 1998
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PIN CONNECTION (top view)
+VS OUTPUT -VS INVERTING INPUT NON INVERTING INPUT
TEST CIRCUIT
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THERMAL DATA
Symbol Rth j-case Parameter Thermal resistance junction-case max Value 3 Unit C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs = 14V , Tamb = 25C unless otherwise specified) for single Supply refer to fig. 15 Vs = 28V
Symbol Vs Id Ib Vos Ios Po Parameter Supply voltage Quiescent drain current Input bias current Input offset voltage Input offset current Output power d = 0.5% Gv = 30 dB f = 40 to 15,000 Hz RL = 4 RL = 8 d = 10% f = 1 KHz RL = 4 RL = 8 d Distor tion Gv = 30 dB 18 11 W W Vs = 18V (Vs = 36V) Test conditions Min. 6 12 40 0.2 2 20 Typ. Max. 18 36 60 2 20 200 Unit V mA A mV nA
12 8
14 9
W W
Po = 0.1 to 12W Gv = 30 dB RL = 4 f = 40 to 15,000 Hz Po = 0.1 to 8W Gv = 30 dB RL = 8 f = 40 to 15,000 Hz
0.2
0.5
%
0.1 10 to 140,000 0.5 5 90
0.5
% Hz M dB
B Ri Gv Gv eN iN SVR
Power Bandwidth (-3 dB) Input resistance (pin 1) Voltage gain (open loop) Voltage gain (closed loop) Input noise voltage Input noise current Supply voltage rejection
Gv = 30 dB Po = 12W
RL = 4
f = 1 kHz B = 22 Hz to 22 KHz
29.5
30 3 80
30.5 10 200
dB V pA dB
RL = 4 Gv = 30 dB Rg = 22 k Vripple = 0.5 Veff fripple = 100 Hz Po = 14W Po = W RL = 4 RL = 8
40
50
Id
Drain current
900 500
mA mA
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Figure 1. Output power vs. supply voltage Figure 2. Output power vs. supply voltage F i g u r e 3. Distortion vs. output power
F i g u r e 4. Di s t o r t i o n vs. output power
F i g u r e 5. Distor t i o n vs. output power
F i g u r e 6. Distortion vs. frequency
F i g u r e 7. Distor t i o n vs. frequency
F i g u r e 8. Frequency response with different values of the rolloff capacitor C8 (see fig. 13)
Figure 9. Quiescent current vs. supply voltage
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Figure 10. Supply voltage rejection vs. voltage gain F i g u re 11. Power dissipation and efficiency vs. output power Figure 12. Maximum power dissipation vs. supply voltage (sine wave operation)
APPLICATION INFORMATION Figure 13. Typical amplifier with split power supply Figure 14. P.C. board and component layout for the circuit of fig. 13 (1 : 1 scale)
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APPLICATION INFORMATION (continued)
Figure 15. Typical amplifier with single power supply
Figure 16. P.C. board and component layout for the circuit of fig. 15 (1 : 1 scale)
Figure 17. Bridge amplifier configuration with split power supply (Po = 28W, Vs = 14V)
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PRACTICAL CONSIDERATIONS Printed circuit board The layout shown in Fig. 16 should be adopted by the designers. If different layouts are used, the ground points of input 1 and input 2 must be well decoupled from the ground return of the output in which a high current flows. Assembly suggestion N o electrical isolation is needed between the package and the heatsink with single supply voltage configuration. Application suggestions The recommended values of the components are those shown on application circuit of fig. 13. Different values can be used. The following table can help the designer.
Component R1 R2 R3 R4
Recomm. value 22 k 680 22 k 1
Purpose Closed loop gain setting Closed loop gain setting Non inverting input biasing Frequency stability
Larger than recommended value Increase of gain Decrease of gain (*) Increase of input impedance Danger of osccilat. at high frequencies with induct. loads Poor high frequencies attenuation
Smaller than recommended value Decrease of gain (*) Increase of gain Decrease of input impedance
R5 C1 C2 C3, C4 C5, C6 C7 C8 D1, D2
3 R2 1 F 22 F 0.1 F 100 F 0.22 F 1 2 B R1 1N4001
Upper frequency cutoff Input DC decoupling Inverting DC decoupling Supply voltage bypass Supply voltage bypass Frequency stability Upper frequency cutoff
Danger of oscillation Increase of low frequencies cutoff Increase of low frequencies cutoff Danger of oscillation Danger of oscillation Danger of oscillation
Smaller bandwidth
Larger bandwidth
To protect the device against output voltage spikes
(*) Closed loop gain must be higher than 24dB
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SINGLE SUPPLY APPLICATION
Component R1 R2 R3 R4 Recomm. value 150 k 4.7 k 100 k 1 Purpose Closed loop gain setting Closed loop gain setting Non inverting input biasing Frequency stability Larger than recommended value Increase of gain Decrease of gain (*) Increase of input impedance Danger of osccilat. at high frequencies with induct. loads Power Consumption Increase of low frequencies cutoff Increase of low frequencies cutoff Danger of oscillation Danger of oscillation Danger of oscillation Smaller bandwidth Larger bandwidth Smaller than recommended value Decrease of gain (*) Increase of gain Decrease of input impedance
RA/RB C1 C2 C3 C5 C7 C8 D1, D2
100 k 1 F 22 F 0.1 F 100 F 0.22 F 1 2 B R1 1N4001
Non inverting input Biasing Input DC decoupling Inverting DC decoupling Supply voltage bypass Supply voltage bypass Frequency stability Upper frequency cutoff
To protect the device against output voltage spikes
(*) Closed loop gain must be higher than 24dB
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SHORT CIRCUIT PROTECTION The TDA2030 has an original circuit which limits the current of the output transistors. Fig. 18 shows that the maximum output current is a function of the collector emitter voltage; hence the output transistors work within their safe operating area (Fig. 2). This function can therefore be considered as being peak power limiting rather than simple current limiting. It reduces the possibility that the device gets damaged during an accidental short circuit from AC output to ground.
Fi g u r e 1 8 . Maximum o u t p u t c u r r e n t vs. vo l tag e [VCEsat] across each output transistor
Figure 19. Safe operating area and c o l l e c t o r characteristics of the protected power transistor
THERMAL SHUT-DOWN The presence of a thermal limiting circuit offers the following advantages: 1. An overload on the output (even if it is permanent), or an above limit ambient temperature can be easily supported since the Tj cannot be higher than 150C. 2. The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There is no possibility of device damage due to high junction temperature. If for any reason, the junction temperature increases up to 150C, the thermal shut-down simply reduces the power dissipation at the current consumption. The maximum allowable power dissipation depends upon the size of the external heatsink (i.e. its thermal resistance); fig. 22 shows this dissipable power as a function of ambient temperature for different thermal resistance.
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Figure 20. Output power and d r a i n cu r r e n t vs. case temperature (RL = 4) Figure 21. Output power and d r a i n c u r r e n t vs. ca s e temperature (RL = 8) Figure 22. Maximum allowable power dissipation vs. ambient temperature
Figure 23. Example of heat-sink
Dimension : suggestion. The following table shows the length that the heatsink in fig. 23 must have for several values of Ptot and Rth.
Ptot (W) Length of heatsink (mm) Rth of heatsink ( C/W) 12 60 8 40 6 30
4.2
6.2
8.3
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PENTAWATT PACKAGE MECHANICAL DATA
DIM. MIN. A C D D1 E E1 F F1 G G1 H2 H3 L L1 L2 L3 L4 L5 L6 L7 L9 M M1 V4 Dia mm TYP. MAX. 4.8 1.37 2.8 1.35 0.55 1.19 1.05 1.4 3.6 7 10.4 10.4 18.15 15.95 21.6 22.7 1.29 3 15.8 6.6 4.75 4.25 40 (typ.) 3.65 3.85 0.144 0.152 MIN. inch TYP. MAX. 0.189 0.054 0.110 0.053 0.022 0.047 0.041 0.055 0.142 0.276 0.409 0.409 0.715 0.628 0.850 0.894 0.051 0.118 0.622 0.260 0.187 0.167
2.4 1.2 0.35 0.76 0.8 1 3.2 6.6 10.05 17.55 15.55 21.2 22.3 2.6 15.1 6 4.23 3.75
3.4 6.8
0.094 0.047 0.014 0.030 0.031 0.039 0.126 0.260 0.396 0.691 0.612 0.831 0.878 0.102 0.594 0.236 0.167 0.148
0.134 0.268
17.85 15.75 21.4 22.5
0.703 0.620 0.843 0.886
0.2 4.5 4
0.008 0.177 0.157
L L1 L8 V V1 V R R A B C D1 L5 L2 L3 D R V4 H2
F E V4 E1
V3 E M1 V V
M
H3 H1 Dia. L7 L6 RESIN BETWEEN LEADS F1 H2 F
G G1
V4 L9
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1998 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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