STD55NH2LL STD55NH2LL-1
N-channel 24V - 0.010 - 40A - DPAK/IPAK Ultra low gate charge STripFETTM Power MOSFET
General features
Type STD55NH2LL-1 STD55NH2LL VDSS 24V 24V RDS(on) <0.011 <0.011 ID 40A(1) 40A(1)
2 1 3
1 3
1. Value limited by wire bonding
RDS(ON) * Qg industry's benchmark Conduction losses reduced Switching losses reduced Low threshold device
iPAK
DPAK
Description
The STD55NH2LL is based on the latest generation of ST's proprietary STripFETTM technology. An innovative layout enables the device to also exhibit extremely low gate charge for the most demanding requirements as highside switch in high-frequency DC-DC converters. It's therefore ideal for high-density converters in Telecom and Computer applications.
Internal schematic diagram
Applications
Switching application
Order codes
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Part number
Marking D55NH2LL D55NH2LL
Package IPAK DPAK
Packaging Tube Tape & reel
STD55NH2LL-1
STD55NH2LLT4
July 2006
Rev 5
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www.st.com 16
Contents
STD55NH2LL - STD55NH2LL-1
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . .. . .. . .. . .. . ..... 6
3 4 5 6 7
Test circuit
. . .. . .. . .. . .. . .. . .. . .. . .. . .... 8
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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STD55NH2LL - STD55NH2LL-1
Electrical ratings
1
Electrical ratings
Table 1.
Symbol Vspike (1) VDS VDGR VGS ID(2) ID(2) IDM
(3)
Absolute maximum ratings
Parameter Drain-source voltage rating Drain-source voltage (VGS = 0) Drain-gate voltage (RGS = 20 k) Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating Factor Value 30 24 24 16 40 28 160 60 0.4 600 Unit V V V V A A A
Ptot EAS (4) Tstg Tj
Single pulse avalanche energy Storage temperature Max. operating junction temperature
1. Garanted when external Rg=4.7 and tf < tfmax. 2. Value limited by wire bonding 3. Pulse width limited by safe operating area. 4. Starting Tj = 25 C, ID = 20A, VDD = 15V
Table 2.
Rthj-case Rthj-amb TJ
Thermal data
Thermal resistance junction-case max
Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose
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-55 to 175
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W/C mJ C
W
2.5 100 275
C/W C/W C
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Electrical characteristics
STD55NH2LL - STD55NH2LL-1
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 25mA, VGS =0 VDS = max rating VDS = max rating TC = 125C VGS = 16V VDS = VGS, ID = 250A VGS = 10V, ID = 20A VGS = 4.5V, ID = 20A 1 0.010 0.012 Min. 24 1 10 100 Typ. Max. Unit V A A nA V
I DSS
IGSS VGS(th) RDS(on)
Table 4.
Symbol gfs (1) Ciss Coss Crss
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Test conditions VDS = 10V, ID = 10A
RG
Gate Input Resistance
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td(on) tr td(off) tf Qg Qgs Qgd
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Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge Gate-source charge Gate-drain charge Output charge
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0.011 0.0135
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S
Typ. 18 990 385 40
Max.
Unit
VDS = 25V, f = 1MHz, VGS = 0 f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain VDD = 10V, ID = 20A RG = 4.7 VGS = 4.5V (see Figure 13) 0.44V VDD 10V, ID = 40A, VGS = 4.5V, RG = 4.7 (see Figure 14)
pF pF pF
1.3
15 56 13 10 8.7 4.2 2.4 7.6 11
ns ns ns ns nC nC nC nC
Qoss(2)
VDS= 16 V, VGS= 0 V
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Qoss = Coss* Vin , Coss = Cgd + Cds . See Chapter 4: Appendix A
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STD55NH2LL - STD55NH2LL-1
Electrical characteristics
Table 5.
Symbol ISD ISDM (1) VSD (2) t rr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 20A, VGS = 0 32.5 28 1.7 Test conditions Min. Typ. Max. 40 160 1.3 Unit A A V ns nC A
Reverse recovery time ISD = 40A, di/dt = 100A/s, Reverse recovery charge VDD = 15V, Tj = 150C Reverse recovery current (see Figure 15)
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %
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Electrical characteristics
STD55NH2LL - STD55NH2LL-1
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
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Static drain-source on resistance
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STD55NH2LL - STD55NH2LL-1 Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
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Figure 12. Normalized breakdown voltage vs temperature
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Test circuit
STD55NH2LL - STD55NH2LL-1
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
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Figure 18. Switching time waveform
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STD55NH2LL - STD55NH2LL-1
Appendix A
4
Appendix A
Figure 19. Buck converter: power losses estimation
The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature.
The low side (SW2) device requires:
Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses
Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; The high side (SW1) device requires:
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Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate Small Qg to have a faster commutation and to reduce gate charge losses Low RDS(on) to reduce the conduction losses.
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Appendix A
STD55NH2LL - STD55NH2LL-1
Table 6.
Power losses calculation
High side switching (SW1) Low side switch (SW2)
Pconduction
R DS(on)SW1 * I 2 * L
R DS(on)SW2 * I 2 * (1 - ) L
IL Ig
Pswitching
Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *
Zero Voltage Switching
Recover y
(1)
Not applicable
Vin * Q rr(SW2) * f
Pdiode Conductio n Not applicable
Vf(SW2) * I L * t deadtime * f Q gls(SW2)
Pgate(QG)
Q g(SW1) * Vgg * f
PQoss
Vin * Q oss(SW1) * f 2
1. Dissipated by SW1 during turn-on
Table 7.
Paramiters meaning
Parameter d Qgsth Qgls Duty-cycle
Post threshold gate charge
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Pconduction Pswitching Pdiode Pgate PQoss
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Third quadrant gate charge On state losses
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Vin * Q oss(SW2) * f 2
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Meaning
On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses
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STD55NH2LL - STD55NH2LL-1
Package mechanical data
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STD55NH2LL - STD55NH2LL-1
TO-251 (IPAK) MECHANICAL DATA
DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033
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A1
0.031
Pr
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0.031
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0.244
0.260
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0.181
0.641 0.370
0.047 0.039
A
L2
L
A3 2
L1
1
=
=
0068771-E
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STD55NH2LL - STD55NH2LL-1
Package mechanical data
DPAK MECHANICAL DATA
mm. DIM. MIN. A A1 A2 B b4 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 5.1 6.4 4.7 2.28 4.4 9.35 1 2.8 0.8 0.6 0.2 0 8 1 0.023 4.6 10.1 0.173 0.368 0.039 6.6 0.252 0.185 0.090 TYP MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.200 0.260 TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 inch
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0.181 0.397
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0.039
0068772-F
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Packing mechanical data
STD55NH2LL - STD55NH2LL-1
6
Packing mechanical data
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM. A
TAPE MECHANICAL DATA
DIM. A0 B0 D E F B1 mm MIN. 6. 8 10.4 1. 5 MAX . 7 10. 6 1.6 inch
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D1 K0 P0 P1 P2 R
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MIN.
0.267 0.275 0.409 0.417 0.476 0.059 0.063 0. 059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1. 574
0.618 0.641
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mm MIN. 1. 5 12.8 20.2 16.4 50
MAX . 330
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MIN. 0. 059 0. 795 1. 968
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MAX. 12. 992
i n ch
13. 2 18. 4 22. 4
0.504 0.520 0.645 0.724 0.881 BULK QTY 2500
BASE QTY 2500
MAX .
12. 1
1. 5 1. 85 7.6 2. 75 4.1 8.1 2.1
16.3
1.65 7. 4 2.55 3. 9 7. 9 1. 9 40
15.7
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STD55NH2LL - STD55NH2LL-1
Revision history
7
Revision history
Table 8.
Date 22-Jun-2004 21-Jul-2005 13-Jun-2006 16-Jul-2006
Revision history
Revision 2 3 4 5 Preliminary datasheet Complete version Packing mechanical data inserted New template, no content change Changes
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STD55NH2LL - STD55NH2LL-1
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