LNBH2 1
LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
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C OMPLETE INTERFACE BETW EEN LNB AND I2CTM BUS BUILT-IN DC/DC CONTROLLER FOR SINGLE 12V SUPPLY OPERATION AND H IGH EFFICIENCY (Typ. 94% @ 750mA) TWO SELECTABLE OUTPUT CURRENT LIMIT (450mA / 750mA) BOTH COMPLIANT W ITH EUTELSAT AND D IRECT OU TPUT VOLTAGE SPECIFIC ATION ACCUR ATE BUILT-IN 22KHz TONE OSCILLATOR SUITS W IDELY ACCEPTED STAND ARDS FAST OSC ILLATOR START-UP FACILITATES D iSEqCTM ENCODING BUILT-IN 22KHz TONE DETECTOR SUPPORTS BI-DIRECTIONAL DiSEqCTM2.0 SEMI-LOWDROP POST REGULATOR AND H IGH EFFICIENCY STEP-UP PWM FOR LOW POWER LOSS: Typ. 0.56W @ 125mA TWO OUTPUT PINS SUITABLE TO BYPASS THE OUTPUT R-L FILTER AND AVOID ANY TONE DISTORSION (R-L FILTER AS PER D iSEqC 2.0 SPECs, see application circuit on pag. 5 ) C ABLE LENGTH DIGITAL COMPENSATION OVERLOAD AND OVER-TEMPERATURE INTERNAL PROTEC TIONS
PowerSO-20
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OVERLOAD AND OVER -TEMPERATURE I2C D IAGNOSTIC BITs LNB SHORT CIRCUIT SOA PROTECTION W ITH I2C DIAGNOSTIC BIT +/- 4KV ESD TOLERANT ON INPUT/ OUTPUT POWER PINS
DESCRIPTION Intended for analog and digital satellite STB receivers/SatTV, sets/PC cards, the LNBH21 is a monolithic voltage regulator and interface IC, assembled in POWER SO-20, specifically designed to provide the 13/18V pow er supply and the 22KHz tone signalling to the LNB downconverter in the antenna or to the multiswitch box. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I2CTM standard interfacing.
B L OC K D I A GR A M
Gate
LNBH21
Step-up PWM Control ler Vu p-Feedb ack
Sense
VoTX
Vup VoRX Vcc Byp
Preregu l.+ U.V.lockou t +P.ON re s. L inear Post-reg +Mod ulator +Protec tions
ISEL EXTM
SDA SCL
V Select I²C in terf. Enabl e
Diag nostics
ADDR
TEN 22KHz Os cill .
Tone Detec tor
DETIN DSQOUT
DSQIN
April 2004
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LNBH21
ORDERING CODES
TYPE LNBH21 PowerSO-20 (Tube) LNBH21PD PowerSO-20 (Tape & Reel) LNBH21PD-TR
AB SOLUTE MAXIMUM RATINGS
Symbol VCC VUP IO VOTX/RX VI VDETIN VOH IGATE VSENSE Tstg Top DC Input Voltage DC Input Voltage Output Current DC Output Pins Voltage Logic Input Voltage (SDA, SCL, DSQIN, ISEL) Detector Input Signal Amplitude Logic High Output Voltage (DSQOUT) Gate Current Current Sense Voltage Storage Temperature Range Operating Junction Temperature Range Parameter Value -0.3 to 16 -0.3 to 25 Internally Limited -0.3 to 25 -0.3 to 7 -0.3 to 2 -0.3 to 7 400 -0.3 to 1 -0.3 to 7 -40 to +150 -40 to +125 Unit V V mA V V VPP V mA V V C C
VADDRESS Address Pin Voltage
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
THERMA L DATA
Symbol Rthj-case Parameter Thermal Resistance Junction-case Value 2 Unit C/W
PIN CONFIGUA RATION (top view)
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LNBH21
TABLE A: PIN CONFIGURATIONS
PIN N 18 17 16 19 SYMBOL VCC GATE SENSE VUP NA M E Supply Input External Switch Gate Current Sense Input Step-up Voltage FUNCTION 8V to 15V IC supply. A 220F bypass capacitor to GND with a 470nF (ceramic) in parallel is recommended External MOS switch Gate connection of the step-up converter DC/DC Current Sense comparator input. Connected to current sensing resistor Input of the linear post-regulator. The voltage on this pin is monitored by internal step-ut controller to keep a minimum dropout across the linear pass transistor RX Output to the LNB in DiSEqC 2.0 application. See truth tables for voltage selections on page 8 and description on page 5. Bidirectional data from/to I2C bus. Clock from I2C bus. When the TEN bit of the System Register is LOW, this pin will accept the DiSEqC code from the main controller. The LNBH21 will use this code to modulate the internally generated 22kHz carrier. Set to GND this pin if not used. 22kHz Tone Detector Input. Must be AC coupled to the DiSEcQ 2.0 bus. Open drain output of the tone Detector to the main controller for DiSEcQ 2.0 data decoding. It is LOW when tone is detected. External Modulation Input acts on VOTX. Needs DC decoupling to the AC source. If not used, can be left open. Pins Connected to Ground. Needed for internal preregulator filtering Set high or floating for Iout<=750mA, connect to ground for IOUT 450mA. 4 7 VOTX ADDR Output Port during 22KHz Tone TX Address Setting Output of the linear post-regulator/modulator to the LNB. See truth tables for voltage selections. Four I2C bus addresses available by setting the Address Pin level voltage. See address pin characteristics table.
2 12 13 14
VORX S DA S CL DSQIN
Output Port during 22KHz Tone RX Serial Data Serial Clock DiSEqC Input
9 15 5 1, 6, 10, 11, 20 8 3
DETIN
Tone Detector Input
DSQOUT DiSEqC Output EXTM G ND BYP ISEL External Modulator Ground Bypass Capacitor Current Limit Select
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LNBH21
TYPICAL APPLICATION CIRCUITS Application Circuit for DiSEqC 1.x and Output Current < 450 mA
D1 1N4 001
Ferrite Bead Filter
F1 suggeste d part number:
MURATA BL01RN1 -A62 Pana sonic EXCELS A35
IC1
F1
Vup 19 3
ISEL
C2 220F IC2
C9 100F
STS4DN FS30L
C3(***) 470nF Ceramic
2
VoRX
Set TTX=1
to LNB
17 G ATE 4
VoTX
LNBH21
L1=22H
Rsc 0.1 16 SENSE C4(***) 470nF Ceramic 18 Vin 12V C1 220F SDA SCL DSQIN(**) 12 13 14 Tone Enable GND 5 7 9
C8(***) 10nF (**) DETIN
D 2(***) B AT43
B yp 8
C5 470nF
EXTM Address
0
15
DSQOU T
Full Application Circuit for Bi-directional DiSEqC 2.0 and Output Current up to 750mA
F1 suggested part number: MURATA BL01RN1-A62 Panasonic EXCELS A35 D 2 1N 4001
Axial Ferrite Bead Filter
IC1
Floating or V >3.3V
F1
Vup C2 220F D1 1N5821 or STPS3L40A C9 100F C3(***) 470 nF Ceramic ISEL
Hi gher c urrent limit Low er current limit
GND
VoTX C8 (***) 1 00nF D4(***) BAT43 27 0H Gate
MOS STN4NF03L VoRX
to L NB
LNBH21
L1=22H
Rsc 0.05 Byp Vcc Vin 12V C1 220F C4(***) 470 nF Ceramic Sense (**) DETIN
C7(***) 100nF
D3(***) B AT43
1 5 ohm
(*) see no te
C6 10nF
C5 470nF
SD A S CL DSQIN (**) G ND
EXTM AD DRESS DSQ OUT
0
22 KHz Tone Enabl e
(*) Filter to be used according to EUTELSAT recommendation to implement the DiSEqCTM 2.0, (see DiSEqCTM implementation on page 8). If bidirectional DiSEqCTM 2.0 is not implemented it can be removed both with C8 and D4. (**) Do not leave these pins floating if not used. (***) To be soldered as close as possible to relative pins. -C8 and D3,4 are needed only to protect the output pins from any negative voltage spikes during high speed voltage transitions.
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LNBH21
APPLICATION INFORMATION This IC has a built in DC/DC step-up controller that, from a single supply source ranging from 8 to 15V, generates the voltages (VUP) that let the linear post-regulator to work at a minimum dissipated power of 1.65W typ. @ 750mA load (the linear regulator drop voltage is internally kept at: VUP-VO=2.2V typ.). An UnderVoltage Lockout circuit will disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7V typically). The internal 22KHz tone generator is factory trimmed in accordance to the standards, and can be controlled either by the I2CTM interface or by a dedicated pin (DSQIN) that allows immediate DiSEqCTM data encoding (*). When the TEN (Tone ENable) I2C bit it is set to HIGH , a continuous 22KH z tone is generated on the output regardless of the DSQIN pin logic status. The TEN bit must be set LOW when the DSQIN pin is used for DiSEqCTM encoding. The fully bi-directional DiSEqCTM 2.0 interfacing is completed by the built-in 22KHz tone detector. Its input pin (DETIN) must be AC coupled to the DiSEqCTM bus, and the extracted PWK data are available on the D S Q O U T p i n ( *) . To comply to the bi-directional DiSEqCTM 2.0 bus hardware requirements an output R-L filter is needed. The LNBH21 is provided with two output pins: the VOTX to be used during the tone transmission and the VORX to be used when the tone is received. This allows the 22KHz Tone to pass without any losses due to the R -L filter impedance (see DiSeqC 2.0 application circuit on page 5). In DiSeqC 2.0 applications during the 22KHz transmission activated by D SQIN pin (or TEN I2C bit), the VOTX pin must be preventively set ON by the TTX I2C bit and, both the 13/18V power supply and the 22KHz tone, are provided by mean of VOTX output. As soon as the tone transmission is expired, the VOTX must be set to OFF by setting the TTX I2C bit to zero and the 13/18V power supply is provided to the LNB by the VORX pin through the R-L filter. W hen the LNBH21 is used in DiSeqC 1.x applications the R-L filter is not required (see D iSeqC 1.x application circuit on pag.5), the TTX I2C bit must be kept always to HIGH so that, the VOTX output pin can provide both the 13/18V power supply and the 22KHz tone, enabled by DSQIN pin or by TEN I2C bit. All the functions of this IC are controlled via I2C TM bus by w riting 6 bits on the System Register (SR, 8 bits). The same register can be read back, and two bits will report the diagnostic status. W hen the IC is put in Stand-by (EN bit LOW), the pow er blocks are disabled. When the regulator blocks are active (EN bit HIGH ), the output can be logic controlled to be 13 or 18 V by mean of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the LNBH21 is provided with the LLC I2C bit that increase the selected voltage value (+1V when VSEL=0 and +1.5V when VSEL=1) to compensate for the excess voltage drop along the coaxial cable (LLC bit HIGH). By mean of the LLC bit, the LNBH21 is also compliant to the American LNB power supply standards that require the higher output voltage level to 19.5V (typ.) (instead of 18V), by simply setting the LLC=1 when VSEL=1. In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. Also in this case, the VOTX output must be set ON during the tone transmission by setting the TTX bit high. When external modulation is not used, the relevant pin can be left open. The current limitation block is SOA type and it is possible to select two current limit thresholds, by the dedicated ISEL pin. The higher threshold is in the range of 750mA to 1A if the ISEL is left floating or connected a voltage > 3.3V. The lower threshold is in the range of 450mA to 700mA when the ISEL pin is connected to ground. W hen the output port is shorted to ground, the SOA current limitation block limits the short circuit current (ISC) at typically 400mA or 200mA respectively for VO 13V or 18V, to reduce the power dissipation. Moreover, it is possible to set the Short Circuit Current protection either statically (simple current clamp) or dynamically by the PCL bit of the I2C SR; when the PCL (Pulsed Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically, as soon as an overload is detected, the output is shut-down for a time TOFF, typically 900ms. Simultaneously the OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time TON=1/10TOFF (typ.). At the end of TON, if the overload is still detected, the protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical TON+TOFF time is 990ms and it is determined by an internal timer. This dynamic operation can greatly reduce the pow er dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions.
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LNBH21
However, there could be some cases in which an highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW ) after a chosen amount of time. W hen in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared. This IC is also protected against overheating: w hen the junction temperature exceeds 150C (typ.), the step-up converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH . Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 140C (typ.).
(*): External components are needed to comply to bi-directional DiSEqCTM bus hardware requirements. Full compliance of the whole application with DiSEqCTM specifications is not implied by the use of this IC
I2C BUS INTERFACE Data transmission from main P to the LNBH21 and viceversa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). DA TA VALIDITY As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW . START AND STOP CONDITIONS As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. BYTE FORMAT Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. A C K N OW L E D GE The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 3). The peripheral (LNBH21) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH21 won't generate the acknowledge if the VCC supply is below the Undervoltage Lockout threshold (6.7V typ.). TRANSMISSION W ITHOUT ACKNOWLEDGE Avoiding to detect the acknowledge of the LNBH21, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 1 : DATA VALIDITY ON THE I2C BUS
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LNBH21
Figure 2 : TIMING DIAGRAM ON I2C BUS
Figure 3 : ACKNOWLEDGE ON I2C BUS
LNBH21 SOFTWARE DESC RIPTION INTERFACE PROTOCOL The interface protocol comprises: - A start condition (S) - A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission) - A sequence of data (1 byte + acknowledge) - A stop condition (P)
CHIP ADDRESS MSB 0 LSB MSB R/W ACK DATA LSB A CK P
S
0
0
1
0
0
0
ACK= Acknowledge; S = Start ; P = Stop; R/W = Read/Write
SYSTEM REGISTER (SR, 1 BYTE)
MS B R, W PCL R, W TTX R, W TEN R, W LLC R, W VSEL R, W EN R OTF LSB R OLF
R,W = read and write bit; R = Read-only bit All bits reset to 0 at Power-On
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LNBH21
TRANSMITTED DA TA (I2C BUS WRITE MODE) W hen the R/W bit in the chip address is set to 0, the main P can write on the System Register (SR) of the LNBH21 via I2C bus. Only 6 bits out of the 8 available can be written by the P, since the remaining 2 are left to the diagnostic flags, and are read-only.
PCL TT X TEN LLC VSEL 0 0 1 1 0 1 0 1 0 1 X X 0 1 0 1 EN 1 1 1 1 1 1 1 1 1 1 0 OTF X X X X X X X X X X X OLF X X X X X X X X X X X Function VO = 13.25 V, VUP = 15.25 V VO = 18V, VUP=20 V VO = 14.25 V, VUP = 16.25 V VO = 19.5 V, VUP = 21.5 V 22KHz is controlled by DSQIN pin 22KHz tone is ON, DSQIN pin disabled VORX output is ON, output voltage controlled by VSEL and LLC VOTX output is ON, 22KHz controlled by DSQIN or TEN, output voltage level controlled by VSEL and LLC Pulsed (dynamic) current limiting is selected Static current limiting is selected Power blocks disabled
X
X
X
X
X= don't care. Values are typical unless otherwise specified
RECEIVED DATA (I2C bus READ MODE) The LNBH21 can provide to the Master a copy of the SYSTEM REGISTER information via I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, the LNBH21 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: - acknowledge the reception, starting in this way the transmission of another byte from the LNBH21; - no acknowledge, stopping the read mode communication. W hile the whole register is read back by the P, only the two read-only bits OLF and OTF convey diagnostic informations about the LNBH21. Values are typical unless otherwise specified.
PCL TT X TEN LLC VSEL EN OTF 0 These bits are read exactly the same as they were left after last write operation
Values are typical unless otherwise specified
OLF
Function TJ<140C, normal operation TJ>150C, power block disabled
1 0 1
IOUTIOMAX, overload protection triggered
POWER-ON I2C INTERFACE RESET The I2C interface built in the LNBH21 is automatically reset at power-on. As long as the VCC stays below the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I2C command and the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the VCC rises above 7.3V typ, the I2C interface becomes operative and the SR can be configured by the main P. This is due to 500mV of hysteresis provided in the U VL threshold to avoid false retriggering of the Power-On reset circuit. AD DRESS PIN Connecting this pin to GND the Chip I2C interface address is 0001000, but, it is possible to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 10).
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LNBH21
DiSEqCTM IMPLEMENTATION The LNBH 21 helps the system designer to implement the bi-directional (2.0) DiSEqC protocol by allowing an easy PWK modulation/demodulation of the 22KHz carrier. The PWK data are exchanged between the LNBH21 and the main P using logic levels that are compatible with both 3.3 and 5V microcontrollers. This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships between the PW K data and the PWK modulation as accurate as possible. These two pins should be directly connected to two I/O pins of the P, thus leaving to the resident firmw are the task of encoding and decoding the PWK data in accordance to the DiSEqC protocol. Full compliance of the system to the specification is thus not implied by the bare use of the LNBH21. The system designer should also take in consideration the bus hardware requirements; that can be simply accomplished by the R-L termination connected on the VO pins of the LN BH21, as shown in the Typical Application Circuit on page 4. To avoid any losses due to the R-L impedance during the tone transmission, the LN BH21 has dedicated output (VOTX) that, in a DiSEqC 2.0 application, is connected after the filter and must be enabled by setting the TTX SR bit HIGH only during the tone transmission (see DiSEqC 2.O operation description on page 2). Unidirectional (1.x) DiSEqC and non-DiSEqC systems normally don't need this termination, and the VOTX pin can be directly connected to the LNB supply port of the Tuner (see DiSeqC 1.x application circuit on pag.4). There is also no need of Tone Decoding, thus DETIN and DSQOUT pins can be left unconnected and the Tone is provided by the VOTX.
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LNBH21
ELECTRICAL CHARACTERISTICS FOR LNBP SERIES (TJ = 0 to 85C, EN =1, TTX=0/1, DSQIN=LOW, LLC=TEN=PC L=VSEL=0, VIN=12V, IO=50mA, unless otherwise specified. See software description section for I2C access to the system register).
Symbol VIN II VO VO VO VO IMAX ISC tOFF tON fTONE ATONE DTONE tr, tf VEXTM ZEXTM fSW fDETIN VDETIN ZDETIN V OL IOZ VIL VIH IIH IOBK TSHDN Parameter Supply Voltage Supply Current Output Voltage Output Voltage Line Regulation Load Regulation Output Current Limiting Output Short Circuit Current Dynamic Overload protection OFF Time Dynamic Overload protection ON Time Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise and Fall Time External Input Voltage External Modulation Impedance DC/DC Converter Switching Frequency Tone Detector Frequency Capture Range Tone Detector Input Amplitude Tone Detector Input Impedance DSQOUT Pin Logic LOW DSQOUT Pin Leakage Current DSQIN Input Pin Logic LOW DSQIN Input Pin Logic HIGH DSQIN Pins Input Current Output Backward Current PCL=0 PCL=0 TEN=1 TEN=1 TEN=1 TEN=1 VOUT/VEXTM, AC Coupling f = 10Hz to 50KHz 260 220 0.4Vpp sinewave fIN=22kHz sinewave 18 0.2 150 Tone present Tone absent IOL=2mA VOH = 6V 0.3 0.5 10 0.8 2 VIH = 5V EN=0, VOBK = 18V 15 -6 150 15 -15 24 1.5 f = 10Hz to 50KHz Output Shorted Output Shorted 20 0.55 40 5 Test Conditions IO = 750 mA TEN=VSEL=LLC=1 EN=TEN=VSEL=LLC=1, NO LOAD EN=0 IO = 750 mA VSEL=1 LLC=0 LLC=1 IO = 750 mA VSEL=0 LLC=0 LLC=1 VIN1= 8 to 15V VSEL=0 VSEL=1 VSEL=0 or 1, IO = 50 to 750mA ISEL = Floating or V > 3.3V ISEL = GND VSEL=0 VSEL=1 Min. 8 20 3.5 18 19.5 13.25 14.25 5 5 Typ. Max. 15 40 7 18.7 20.3 13.75 14.75 40 60 200 1000 700 300 200 900 tOFF/10 22 0.72 50 8 6 400 mVPP kHz kHz VPP k V A V V A mA C C 24 0.9 60 15 Unit V mA V V mV mV mA mA ms ms KHz VPP % s
17.3 18.7 12.75 13.75
750 450
GEXTM External Modulation Gain
Temperature Shutdown Threshold TSHDN Temperature Shutdown Hysteresis 10/20
LNBH21
GATE AND SENSE ELECTRICA L CHARACTERISTICS (TJ = 0 to 85C, VIN = 12V)
Symbol Parameter Test Conditions IGATE= -100mA IGATE= 100mA Min. Typ. 4.5 4.5 200 Max. Unit mV RDSON-L Gate LOW RDSON RDSON-H Gate HIGH RDSON VSENSE Current Limit Sense Voltage
I2C ELECTRICAL C HARACTERISTICS (TJ = 0 to 85C , VI = 12V)
Symbol VIL VIH II V OL fMAX Parameter LOW Level Input Voltage HIGH Level Input Voltage Input Current Low Level Output Voltage SDA, SCL SDA, SCL SDA, SCL, VI = 0.4 to 4.5V SDA (open drain), IOL = 6mA 500 2 -10 10 0.6 Test Conditions Min. Typ. Max. 0.8 Unit V V A V KHz
Maximum Clock Frequency SCL
AD DRESS PIN CHARACTERISTICS (TJ = 0 to 85C, VIN=12V)
Symbol Parameter Test Conditions Min. 0 1.3 2.3 3.3 Typ. Max. 0.7 1.7 2.7 5 Unit V V V V VADDR-1 "0001000" Addr Pin Voltage VADDR-2 "0001001" Addr Pin Voltage VADDR-3 "0001010" Addr Pin Voltage VADDR-4 "0001011" Addr Pin Voltage
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LNBH21
THERMAL DESIGN NOTES During normal operation, the LNBH21 device dissipates some power. At maximum rated output current (750mA), the voltage drop on the linear regulator lead to a total dissipated power that is typically 1.65W. The heat generated requires a suitable heatsink to keep the junction temperature below the over temperature protection threshold. Assuming a 45C temperature inside the Set-Top-Box case, the total Rthj-amb has to be less than 48C/W. W hile this can be easily achieved using a through-hole power package that can be attached to a small heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous copper area of the GND layer to dissipate the heat coming from the IC body. Given an Rthj-case equal to 2C/W, a maximum of 46C/W are left to the PCB heatsink. This figure is achieved if a minimum of 6.5cm2 copper area is placed just below the IC body. This area can be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side where the IC is placed. In figure 4, it is shown a suggested layout for the PSO-20 package with a dual layer PC B, where the IC exposed pad connected to GN D and the square dissipating area are thermally connected through 32 vias holes, filled by solder. This arrangement, when L=25mm, achieves an Rthc-amb of about 32C /W. Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to design a dissipating area having a shape as square as possible and not interrupted by other copper t r ac es . Figure 4 : PowerSO-20 SUGGESTED PCB HEATSINK LAYOUT
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LNBH21
TYPICAL CHARAC TERISTICS (unless otherwise specified Tj = 25C ) Figure 5 : Output Voltage vs Temperature Figure 8 : Load Regulation vs Temperature
Figure 6 : Output Voltage vs Temperature
Figure 9 : Load Regulation vs Temperature
Figure 7 : Output Voltage vs Temperature
Figure 10 : Supply C urrent vs Temperature
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LNBH21
Figure 11 : Supply C urrent vs Temperature Figure 14 : Dynamic Overload Protection OFF Time vs Temperature
Figure 12 : Supply C urrent vs Temperature
Figure 15 : Output Current Limiting vs T em perat ure
Figure 13 : Dynamic Overload Protection ON Time vs Temperature
Figure 16 : Output Current Limiting vs T em perat ure
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LNBH21
Figure 17 : Tone Frequency vs Temperature Figure 20 : Tone Rise Time vs Temperature
Figure 18 : Tone Amplitude vs Temperature
Figure 21 : Tone Fall Time vs Temperature
Figure 19 : Tone Duty Cycle vs Temperature
Figure 22 : Undervoltage Lockout Threshold vs T em perat ure
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LNBH21
Figure 23 : Output Backward Current vs T em perat ure Figure 26 : 22kHz Tone Waveform
VCC=12V, IO=50mA, EN=TEN=1
Figure 24 : DC/DC Converter Efficiency vs T em perat ure
Figure 27 : DSQIN Tone Enable Transient Response
VCC=12V, IO=50mA, EN=1, T one enabled by DSQIN Pin
Figure 25 : Current Limit Sense Voltage vs T em perat ure
Figure 28 : DSQIN Tone Enable Transient Response
VCC=12V, IO=50mA, EN=1, T one enabled by DSQIN Pin
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LNBH21
Figure 29 : DSQIN Tone Disable Transient Response
VCC=12V, IO=50mA, EN=1, T one enabled by DSQIN Pin
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LNBH21
PowerSO-20 MECHANICAL DATA
DIM. A a1 a2 a3 b c D (1) E e e3 E1 (1) E2 G h L N S T 0 10.0 0.80 0 10.90 0 0.40 0.23 15.80 13.90 1.27 11.43 11.10 2.90 0.10 1.10 1.10 0.0314 0 0.3937 0.0000 0.4291 0.10 mm. MIN. TYP MAX. 3.60 0.30 3.30 0.10 0.53 0.32 16.00 14.50 0 0.0157 0.0090 0.6220 0.547 2 0.0500 0.4500 0.4370 0.1141 0.0039 0.0433 0.0433 10 8 0.0039 MIN. inch TYP. MAX. 0.1417 0.0118 0.1299 0.0039 0.0209 0.0013 0.630 0.5710
10
8
(1) "D and E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006")
N
N a2 A
R
c a1 DETAIL B E
b DETAIL A D e3
e
led a
DETAIL A
20
11
a3 DETAIL B E2 T E1
Gage Plan e 0.35
slug
- C-
S
L
SEATI G PLANE N GC (COPLANARITY)
1
1
0
PSO20MEC
h x 45
0056635
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LNBH21
Tape & Reel PowerSO-20 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P W 15.1 16.5 3.8 3.9 23.9 23.7 12.8 20.2 60 30.4 15.3 16.7 4.0 4.1 24.1 24.3 0.594 0.650 0.149 0.153 0.941 0.933 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.602 0.658 0.157 0.161 0.949 0.957 MIN. TYP. MAX. 12.99 2 0.519 inch
19/20
LNBH21
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