| No. 0, July 2003 - Art. 5 |
| |
| A Power Modeling and Estimation Framework for VLIW-based Embedded Systems |
|
 |
by
L. Benini, D. Bruni (Università degli Studi di Bologna), M. Chinosi, R. Zafalon (STMicroelectronics), C. Silvano (Università degli Studi di Milano), V. Zaccaria (Politecnico di Milano)
Copyright
© STMicroelectronics, Università degli Studi di Bologna, Università degli Studi di Milano, Politecnico di Milano, 2001 - Reprinted,with permission, from:L.Benini, D.Bruni M.Chinosi,C.Silvano,V.Zaccaria,R.Zafalon,"A Power Modeling and Estimation Framework for VLIW-based Embedded Systems", Proceedings of Power and Timing Modeling,Optimization and Simulation 11th International Workshop,Yverdon Les Bains,Switzerland,Sept.2001 |
|
| |
Abstract
In this paper, we propose a framework for modeling and estimation of the system-level power consumption for embedded VLIW (Very Long Instruction Word) architectures. We have developed power macro-models for the main components of the system, namely the core, the register file, instruction and data caches, all of which we have integrated, at several abstraction levels, within a hierarchy of dynamic power estimation engines. Our main goal is to define a system level simulation framework (i) to profile dynamically the power behavior during software execution and (ii) to provide a break-out of the power contributions due to the single components of the system. We have applied the proposed methodology to an industrial case study: the Lx family of scalable embedded VLIW processors, designed for multimedia and signal processing applications. We have carried out an extensive validation of the proposed methodology over a set of multimedia benchmarks for embedded applications. Our experimental results have demonstrated an average accuracy of 5% of the instruction-level estimation engine with respect to the RTL engine, with an average speed-up of four orders of magnitude. |
| |
| |
|
|
|
