| Vol. 1, No. 2, September 2004 - Art. 1 |
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| A Multi-Level Computing Architecture for Embedded Multimedia Applications |
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by
Faraydon Karim, Alain Mellan (STMicroelectronics), Utku Aydonat, Tarek Abdelrahman, Anh Nguyen (University of Toronto)
Copyright
Copyright © IEEE, 2004 - Reprinted, with permission, from A Multi-Level Computing Architecture for Embedded Multimedia Applications, by Faraydon Karim, Alain Mellan (STMicroelectronics), Utku Aydonat, Tarek Abdelrahman, Anh Nguyen, University of Toronto, IEEE Micro, March 2004, Vol. 24, Issue3, pages 55-66. |
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Abstract
We describe and evaluate a template architecture for SoC systems intended for multimedia applications. The architecture is a 2-level hierarchy that consists at the bottom level of several processing units (PUs), controlled at the top level by a control processor. The main characteristic of our architecture is that it exploits in hardware parallelism among tasks executing on different PUs in the same way a superscalar processor exploits instruction level parallelism.
This hardware support for task-level parallelism gives rise to a natural programming model that relieves programmers from explicitly synchronizing tasks and communicating data. We describe a number of code transformations to port and improve performance; these transformations are based on well-known compiler analyses, and thus can be incorporated into a compiler for this architecture. We use simulation, two realistic multimedia applications and the proposed code transformations to explore the performance vs. resources trade-off.
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