| Vol. 1, No. 2, September 2004 - Art. 4 |
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| Balancing Code Size and Performance for ST100 Processor Cores |
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by
Mark Leair (STMicroelectronics)
Copyright
© STMicroelectronics, 2004 |
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Abstract
This experience paper demonstrates performance and code size balancing features in STCC, a high performance ANSI C/C99 and C++/EC++ compiler targeting the ST100 family of embedded processor cores from STMicroelectronics. When emphasizing performance in an application, code size often increases due to compiler optimizations like function inlining, loop unrolling, and software pipelining. Because cost ultimately drives the production of embedded systems, the fastest and typically the largest application is not always the best solution for a given product. We apply the STCC tool chain to a commercial Micro-Control Unit (MCU) application. Optimizing only for code size, the application can be compiled to 2502 bytes with a speed of 58.26 Kcycles. Optimizing only for performance, the application achieves a peak performance of 33.49 Kcycles at 3748 bytes. While the version optimized for code size is 33.2% smaller, it is 74% slower. With STCC Profile Feedback, a programmer can easily balance performance and code size requirements in the application. For example, after applying Profile Feedback, a version of the MCU application that is 22.5% smaller and only 6.8% slower than the fast version is realized with STCC. |
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