| Vol. 3, No. 2, December 2006 - Art. 6 |
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| A 565 Mbps Multi-Rate IP-core Decoder of Structured
LDPC Codes |
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by
Massimo Rovini, Nicola E. L’Insalata, Francesco Rossi,
Luca Fanucci, Department of Information Engineering, University
of Pisa
Copyright
Copyright © IEEE, 2005.Reprinted, with permission, from:
"VLSI Design of a High-Throughput Multi-Rate Decoder
for Structured LDPC Codes", by M. Rovini, N.E. L’Insalata,
F. Rossi, L. Fanucci, Proceedings of the Euromicro Symposium
on Digital System Design (DSD), Oporto, 2005, pages 202-209
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| | | Abstract
This paper presents the top-down design flow of an IP-core for a
decoder of structured low-density parity-check codes. After an analysis
of the system performance in finite-precision arithmetic, an overview
of the state–of–the–art solutions is reported
along with the implementation details of the elementary modules.
The proposed architecture exploits the peculiar code definition
to support multiple code rates with no significant hardware overhead.
Moreover, the adoption of an architecture with memory paging allows
the decoder to reach remarkable useful throughput (up to 565.1 Mbps)
and to contain the latency within 6.0 µs, irrespectively of
the code-rate. The synthesis of the whole decoder on 0.18 µm
standard cells CMOS technology using 5 bits for inputs and extrinsic
messages showed a complexity of about 468 Kgates with an implementation
loss of only 0.2 dB down to BER =10-8. |
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