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New Chip Technology from STMicroelectronics Eliminates "Soft Error" Threat To Electronic Systems |
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 Geneva,
December 15, 2003 - STMicroelectronics (NYSE: STM), one of the world's
leading semiconductor manufacturers, has announced a new semiconductor
technology that virtually eliminates a potential problem that has been
increasingly haunting electronic equipment manufacturers in recent years:
the growing vulnerability of silicon chips to so-called "soft errors".
These soft errors are caused by ever-present nuclear particles that make up the earth's low intensity background radiation. Originating from the cosmic rays from space or from tiny traces of radioactive elements that occur in all materials, the particles are not dangerous by themselves but they can potentially disrupt the operation of silicon chips and the electronic equipment that depends on them. ST's new technology, called rSRAM, developed at the Company's Central R&D site at Crolles, France, delivers greatly increased immunity to the effects of stray atomic particles without incurring significant cost or performance penalties. The semiconductor devices that power products such as mobile phones, PCs, or the sophisticated computers that route Internet and other communications traffic are typically so-called System-on-Chip (SoC) devices. These devices contain tens or hundreds of millions of tiny transistors, fabricated and interconnected on silicon chips about the size of a fingernail. Many of these transistors are used to form embedded SRAM (Static Random Access Memory) - a type of electronic memory that allows data to be stored and retrieved at very high speed. Following a path called Moore's Law after the engineer who first observed it, each new generation of silicon-chip technology, developed about every 18 to 24 months, halves the size of the transistors, making the new chips faster, smaller, and cheaper. However, the smaller the transistors are made, the more susceptible they become to the effects of stray ionizing particles. Within the chips, information is usually stored inside transistors as electrical charges. A nuclear particle such as a neutron or an alpha particle passing through the silicon chip can change the charge stored on a nearby transistor. Changes to the charge caused by a ionizing particle gives rise to a "soft error" i.e. the chip is not physically damaged but may temporarily contain erroneous data. This soft error may cause the device to malfunction temporarily, even though subsequent testing will show a perfectly working device. Compounding the problem While the shrinking individual transistors in the embedded SRAM are becoming increasingly vulnerable to background radiation, the amount of embedded SRAM in chips is also increasing exponentially: currently it accounts for over 50% of the transistors in a typical silicon chip. According to the ITRS (International Technology Roadmap for Semiconductors), this percentage is expected to reach 90% by the end of the decade. Embedded SRAM is becoming a larger portion of SoCs because storing program code and data in the chip's embedded SRAM results in higher performance. "With the technologies that are in volume production today, soft errors do not usually cause many serious problems," says Dr. Jean-Pierre Schoellkopf, Director, Advanced Design and Tools, in ST's Central R&D Group. "The issue for electronic equipment manufacturers is that the continuing trend towards smaller transistors and larger on-chip SRAM memories, which they need in order to maintain their market momentum, make it inevitable that worst-case scenarios such as computer crashes or lost or misrouted data would happen with increasing frequency. We therefore decided to develop a more robust embedded SRAM technology, one that could provide immunity to background radiation without incurring significant cost or performance penalties." In fact, ST's patented solution meets both of these key requirements: by redesigning the structure of the basic SRAM memory cell used in System-on-Chip semiconductor devices, ST has developed a new technology that is substantially as fast and cost-effective as conventional SoC technologies but is also virtually immune to the effects of stray nuclear particles. "The rSRAM is an exciting breakthrough because it allows electronic equipment manufacturers to have confidence that they can receive the price/performance advantages delivered by new silicon technology generations without the danger of increasing soft error vulnerability," notes Dr. Schoellkopf. ST's solution is particularly ingenious because it does not significantly increase the silicon area occupied by the integrated circuit. The manufacture of a silicon chip requires many complex processing stages to build up the three-dimensional structure that forms the final integrated electronic circuit. These circuits are always manufactured in parallel, with as many circuits as possible fitted onto a thin wafer of silicon, typically 200mm in diameter (currently moving to 300mm). Increasing the chip area reduces the number of chips that can be processed on a wafer, which in turn increases the chip manufacturing cost. The modification ST has made to the standard SRAM memory cell adds additional components called capacitors which are integrated into the cell structure in the vertical dimension, so that the chip area - and therefore the manufacturing cost - is not significantly affected. The effect of these capacitors is to increase the amount of charge required to "flip" a memory cell, thus reducing the number of soft errors in any given time interval. ST has fabricated test chips in 120nm technology (which will be the next technology generation to enter mass production) using the new rSRAM cells and subjected them to aggressive testing, which involves bombarding them with high levels of artificial radiation and measuring the resulting soft error rate. These tests (performed at the Los Alamos Neutron Science Centre) have confirmed that ST's rSRAM cells are around 250 times more resistant to soft errors than conventional SRAM cells - the cells are completely immune to alpha particles and almost completely immune to neutron-induced errors. About STMicroelectronics STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2002, the Company's net revenues were $6.32 billion and net earnings were $429.4 million. Further information on ST can be found at http://www.st.com. Notes for Editors. * Alpha particles, discovered by Ernest Rutherford in 1899, consist of two protons and two neutrons i.e. they are essentially atoms of helium minus the helium atom's two electrons, which gives the alpha particle a positive charge. Alpha particles are emitted by certain radioactive atoms such as Uranium-238, Radium-226 and Radon-222 that occur naturally, in minute quantities, in the environment. Although alpha particle emitters have important industrial uses such as cancer treatments, smoke detectors and the reduction of static electricity in paper mills, the presence of alpha particles inside a silicon chip can cause soft errors. . * ST's test chips included rSRAM blocks, standard SRAM, and standard SRAM supported by additional Error Correction circuitry, as well as logic (non-memory) circuits, allowing the soft error rates (SER) of all of them to be measured under identical conditions. . * The test chips underwent comprehensive "accelerated" testing i.e. they were tested under radiation levels many orders of magnitude greater than are encountered under normal operating conditions. Testing for alpha particle immunity was performed using Americium 231 and Thorium 232 radioactive sources at ST's facilities in Crolles, France, and Carrollton, USA. The test chips exhibited complete immunity to soft errors caused by alpha particles. Testing for neutron-induced soft errors was performed at the Los Alamos Neutron Science Centre, USA, where one hour's exposure to the neutron beam is equivalent to 15,753 years of normal operation at sea-level. All tests were fully compliant with the JEDEC JESD89 standard.
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