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Frequently Asked Questions on STE100P
1 What is the 7-wire GPSI and is this supported by the STE100P?
2 What is the list of vendors for the transformers that are tested by ST while using the STE100P?
3 The transformer that I plan to use has an insertion loss of 1.2dB Max. Is this a problem for STE100P? Is there a way to increase the drive in the ST part to compensate for a higher insertion loss. If so how?
4 Does the STE100P use the MII interface? Does it have support for RMII / SMII?
5 We want to develop a software driver, which we can initialize as we want the physical layer registers. I need to remove, as possible, any switch or jumper options, due to board constraints. What is the best default value for config pins (mf[4:0], fde,cfg[1:0]) knowing that the values will be hardwired?
6 We use the Transpower RJ626 part with 4 resistors integrated with transformer + RJ45 connector.
At pins 4,5 & 7,8 of RJ45 connector, 75ohms resistors are integrated. Looking at your application note, it is understood that one must adapt with 2x50ohms resistors. Is 100ohms a standard impedance for an Ethernet cable? Is it Ok with 2x75ohms resistors? "Is RJ626 compatible with STE100P?"
7 What are the TX and RX transformer turns ratio required?
8 On the STE100P reference design schematic, switches SW3,4,5,6,7, values of resistances are specified. Can we choose values of resistors with tolerance 5%?
9 To reduce the board size, is there a way to reduce the number of switches?
10 Does the STE100P have an AUI interface?
11 Is the STE100P pin-to-pin compatible with any of the competition PHYs?
12 How do you bring the STE100P back from the Isolate mode?
13 What are the steps to follow to make sure that the PHY is working correctly in the 100Mbps mode?
 

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