STE10/100A - Drivers |
| 1 |
What is the 7-wire GPSI and is this supported by the STE100P?
The 7-wire GPSI (General Purpose Serial Interface) is an older interface used for 10Mbps interface from MAC to PHY. GPSI, consisting of 7 pins (TxData, TxCLK, TxEN, RxData, RxCLK, COL, & CRS), uses single serial receive and transmit data pins clocked at 10MHz. It is not a 100Mbps interface, and does not support 100Mbps operation. MII on the other hand uses a 4-bit wide data path and is clocked at 2.5MHz for 10 Mbps and 25MHz for 100Mbps operation. The 7-wire GPSI interface is not supported by the STE100P. The MAC to PHY interface supported by the STE100P is standard MII or optionally 5B Symbol mode. |
| 2 |
What is the list of vendors for the transformers that are tested by ST while using the STE100P?
ST has tested the following list of transformers:
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Belfuse: S558-5999-U7 |
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Halo: TG110-SO55N2 |
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Tyco/Transpower Technologies:
Part # HB626-1, HB726, 1605000-1 |
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Pulse Engineering: Part # H1102,
H1117, H1012, J1035, J0011D21B |
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Midcom: 000-7160-30R |
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| 3 |
The transformer that I plan to use has an insertion loss of 1.2dB Max. Is this a problem for STE100P?
Is there a way to increase the drive in the ST part to compensate for a higher insertion loss. If so how?
The substitution of 1.1dB insertion loss transformer with a 1.2dB one can reduce the amplitude of the transmitter output signal by ~1.2% for the worst case. The standard allows amplitude tolerance +-5% for 100BASE-TX mode and +-10% for 10BASE-T mode. Thus, using this transformer, you should verify that the overall tolerance does not exceed +- 5%. |
| 4 |
Does the STE100P use the MII interface?
Does it have support for RMII / SMII?
The standard is MII, and it is implemented on STE100P, the single channel PHY device. RMII and SMII are not supported as is the case of most of the single PHYs in the market. MII is a 4-bit interface, RMII is a 2-bit interface at 2x clock rate of MII, and SMII is a 1-bit interface at 4x clock rate of MII. RMII and SMII were developed to allow multi-channel PHY devices to use less pins to interface to the multi-channel MAC controllers or Switch devices. Furthermore, SMII is just a de-facto standard that is not yet formally specified by any standards body. |
| 5 |
We want to develop a software driver, which we can initialize as we want the physical layer registers. I need to remove, as possible, any switch or jumper options, due to board constraints. What is the best default value for config pins (mf[4:0], fde,cfg[1:0]) knowing that the values will be hardwired?
The best default value for config pins (mf[4:0], fde,cfg[1:0]) that is recommended is:
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mf0 = 1 |
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mf1 = 1 |
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mf2 = 1 |
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mf3 = 0 |
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mf4 = 1 |
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fde = 1 |
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cfg0 = 1 |
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cfg1 = 1 |
This will enable Auto-Negotiation for full duplex 100Mbps operation if supported by the other end equipment, otherwise it will negotiate to the highest possible operation supported by both ends. |
| 6 |
We use the Transpower RJ626 part with 4 resistors integrated with transformer + RJ45 connector. At pins 4,5 & 7,8 of RJ45 connector, 75ohms resistors are integrated. Looking at your application note, it is understood that one must adapt with 2x50ohms resistors. Is 100ohms a standard impedance for an Ethernet cable?
Is it Ok with 2x75ohms resistors?
"Is RJ626 compatible with STE100P?"
The resistors in the Transpower RJ626 are okay since they are just used to terminate the unused pairs of the CAT5 cable. Although the termination scheme they use (2x75 ohms) is slightly different from that used in our STE100P reference design, it should work okay. The values that are more critical are the 50-ohm resistors that should be connected from the TX+ and TX- pins of the device to AVddT, and to pins 10 and 11 of the Transpower RJ626 part. This is important because 100 ohms is a standard impedance for an Ethernet cable. |
| 7 |
What are the TX and RX transformer turns ratio required?
Both the TX and RX transformer turns ratio required is 1:1. |
| 8 |
On the STE100P reference design schematic, switches SW3,4,5,6,7, values of resistances are specified. Can we choose values of resistors with tolerance 5%?
For the PHY Address selection switches (SW 3-7) you can use available 5% tolerance resistors that are close to the values shown on the schematic. The purpose of these resistors is mainly to pull the pin to the appropriate logic level and to limit the LED current flow. In fact, unless you will need to be changing PHY Address values, you can remove these DIP switches and just configure the LED connection to select the fixed address you want for the PHY. This will also require only 2 resistors per LED (1 in series with the LED, and 1 in parallel). Since the STE100P has 5V tolerant I/O, the level applied to the LED pins for PHY address selection of "one" may be 3.3V or 5V. We used 5V on our board to reduce the requirements for the 3.3V voltage regulator. |
| 9 |
To reduce the board size, is there a way to reduce the number of switches?
With the exception of Reset, the functions selected by DIP switch SW8 and SW9 can also be selected via the MII interface to the internal registers of the device. So if you implement a separate reset switch, you can just use pull-up or pull down resistors to all of the other option select pins (MF0-4, CFG0-1, FDE, & PWRDWN) to select the default power-up mode, and then you can change modes via the MII interface. The only reason we added all of the DIP switches is because there is an evaluation board for the device, and we wanted to be able to have full access to all of the features of the device, including the configuration with pins or registers, but not draw any extra power from the pull-up resistors. |
| 10 |
Does the STE100P have an AUI interface?
No, The STE100P does not have an AUI interface because this is a 10Mbps feature only and it is not used in any applications that support 10/100Mbps. |
| 11 |
Is the STE100P pin-to-pin compatible with any of the competition PHYs?
No, the STE100P is not pin-to-pin compatible with any of the competition PHYs available at the time of writing. |
| 12 |
How do you bring the STE100P back from the Isolate mode?
After power up in isolate mode, write 0x3100 to PHY register 0 (to clear bit 10, ISOEN, and enable Auto negotiation), and write 0x01C0 to register PR19 (to clear the ISOTX bit). |
| 13 |
What are the steps to follow to make sure that the PHY is working correctly in the 100Mbps mode?
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Write 0x8000 to register PR0 to reset the PHY |
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Write 0x6100 to register PR0 to enable 100Mbps FD and loopback mode |
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Verify that the chip is in 100Mbps mode |
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Verify that you can transmit and receive data from the MAC to and from the PHY |
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If this works okay, then write 0x2100 to PRO to enable 100Mbps full duplex |
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Verify that TxCLK is 25Mhz and MLT3 signal is present on TX+ / TX-outputs |
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Connect CAT5 cable from PHY RJ45 to 100Mbps Hub/Switch |
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Both sides should indicate link-up and 100Mbps data transmission should be possible |
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If not, then it is necessary to check signal levels, jitter, noise, frequency, etc |
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