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STR71x hardware development getting started

Application Note

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Last Updated: 04/03/2008

Pages: 27

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AN1775 APPLICATION NOTE
STR71x Hardware Development Getting Started
Introduction
This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the STR71x product family and describes the minimum hardware resources required to develop an STR71x application. Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes.

October 2005

Rev 3 1/27
www.st.com 27

AN1775

Contents
1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power management block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 Clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 USB clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 4 5

Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Boot management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 5.2 ICE debug tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 JTAG / ICE connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6

Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.1 6.1.2 6.1.3 6.1.4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 6.3 6.4 6.5 6.6

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 USB full speed interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RS232 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6.1 6.6.2 SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C EEPROM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.7 6.8

JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/27

AN1775 6.9 6.10 6.11 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LCD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Conclusions and recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7

Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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1 Power management

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1
1.1

Power management
Overview
The chip is powered by an external 3V3 supply(V33: 2.7 to 3.6 V, AVDD: 3.0 to 3.6 V). All I/Os are 3V3-capable. An internal Voltage Regulator generates the supply voltage for core logic (~=1.8V). The two V18 pins must be connected to external stabilization capacitors. The following figure indicates the recommended configuration for the power supply pins: Figure 1. STR71x power supply pins
3V3 STR71x V33 V33IO-PLL V18
33nF 10F

GND V18BKP

VSSIO-PLL VSS VSSBKP GND

1F

GND

1.2

Power management block
The following figure describes the power management block implemented on the STR71x devices. Figure 2. Power Management Block
3V3 3.3 V V33
Main Voltage Regulator (MVR) Low Power Voltage Regulator (LPVR)

I/O circuitry

V18
33nF 10F

1.8 V

CORE

GND

V18BKP
1F

switch see note 1

Backup block

GND

The STR71x power management block has two regulators:

The Main Voltage Regulator MVR. The Low Power Voltage Regulator LPVR. Both regulators can be switched-off by software

Note the following remarks about the two regulators:

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1 Power management

V18 can be used to supply an externally regulated 1.8V, but V33 must supply the IOs V18BKP pin can be used to externally supply the backup logic, but V33 must supply the IOs The switch in Figure 2, opened only during STANDBY mode, disconnects the V18 domain from the V18BKP domain

It is possible to switch-off the MVR and keep LPVR on when the device is in low-power mode (SLOW, WFI, LPWFI, STOP or STANDBY). The LPVR has a different design from the main VR and generates a non-stabilized and non-thermally-compensated voltage of approximately 1.6V. In STANDBY mode the Low Power VR can be switched off when an external regulator provides a 1.8V supply to the chip through the V18BKP pin for use by RTC and Wake-Up block. In this case we must to keep the 3.3V on pin V33 even if the two regulators are switch off to keep stable state on the I/Os. Remark:The PLL is automatically disabled (PLL off) when the MVR is switched off and the maximum allowed operating frequency is 1 MHz. This is due to the limitation imposed by the LPVR which is not able to generate sufficient current to operate in run mode. The MAIN DEVICE CORE is powered from an external 3V3 power supply pin (V33) through the main regulator. For more details on the power regulators, refer to the STR71x Reference Manual.

5/27

2 Clock management

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2

Clock management
The STR71x offers a flexible way for selecting core and peripherals clocks, the devices have up to 3 external clock sources:

The PRCCU generates the internal clocks for the CPU and for the on-chip peripherals. The PRCCU may be driven by an external pulse generator, connected to the CK pin. The Real time Clock 32kHz oscillator is connected to the internal CK_AF signal (if present on the application), and this clock source may be selected when low power operation is required. USB clock source available only with devices with USB feature.

2.1

Clock control unit
The STR71x clock control unit must be driven by an external oscillator, connected to the CK pin, at a frequency of up to 16 MHz. It generates the clocks for the CPU and for the on-chip peripherals. A range of available multiplication and division factors allows for a large number of operating clock frequencies to be driven from the input frequency. However, great care must be taken to respect the recommendations for allowed frequency limits. For more details on allowed operating frequencies for each clock, refer to the Reference Manual. The following diagram shows the basic implementation of the main external clock. Figure 3. Main clock oscillator
OSCILLATOR

STR71x
33

CK
10K

VSS GND GND

3V3

The following table gives frequency range examples of the Main clock for some input clock values:
Input Clock 4 MHz 8 MHz 16 MHz MCLK (Main Clock) Range [15625 Hz, 50 MHz] [31250 Hz, 50 MHz] [62500 Hz, 50MHz]

2.2

Real Time Clock
The Real Time Clock operates at a speed of 32 kHz. This clock must be provided by an external resonator circuitry. The RTC is used to generate a time base, and can be selected when low power operation is needed. Refer to the Reference Manual for more details.

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AN1775
Figure 4. RTC oscillator
STR71x
32kHz CRYSTAL

2 Clock management

RTCXTI RTCXTO
15pF*

15pF*

VSS GND GND
* these values are given only as examples, refer to the crystal manufacturer for more details

2.3

USB clock
STR710 and STR711 series microcontrollers contain a USB 2.0 Full Speed device module interface that operates at a precise frequency of 48 MHz. This clock is usually provided by an external oscillator connected to the USB clock pin USBCLK. However, to save the board's space and cost, the 48MHz USB clock can also be generated by the internal PLL2 using one single external oscillator for both system and USB module. This part of the application note describes the hardware and software reference implementation. USB Full Speed signal quality and jitter results can be measured using a single external oscillator to generate not only the System PLL clock and Peripheral's clocks, but also the 48MHz USB clock.

2.3.1

Hardware implementation
The hardware implementation guidelines are described in the figure below.

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2 Clock management

AN1775
USB clock and pins implementation
V33

Figure 5.

47K
USB Indicate

56K BC547E 56K ST R710/STR 711 GND

GPIO
1K5

GND GND 0 Ohm 15pF

GPIO DP DM

Vbus D+
USB connector

D0 Ohm 15pF GND GND VSS

V33
56K

USB CLK

48MHz Oscillator

GND

USB full speed interface device supported via type B connector. The USB clock uses a separate 48 MHz oscillator. Transistor circuit used to indicate the cable status (Cable connected USB/IND pin = 0 logic, Cable deconnected = USB/IND pin = 1 logic).

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AN1775

3 Reset management

3

Reset management
Both the Main Voltage Regulator and the Low Power Voltage Regulator contain an LVD. They keep the device under reset when the corresponding controlled voltage value (V18 or V18BKP falls below 1.35V10%). The LVDs do not monitor V33 which supplies the I/O and analog parts of the device.

Note:

During power-on, a reset must be provided externally. At power on, the nRSTIN pin must be held low by an external reset circuit until V33. Figure 6 gives an example of the hardware implementation of the RESET circuit for STR71x devices.

The STM1001 low-power CMOS microprocessor supervisory circuit is used to assert a reset signal whenever the V33 voltage falls below a preset threshold or a manual reset is asserted. Hardware reset implementation
STR71x V33
nRSTIN
Reset_PB

Figure 6.

+3V3

+3V3
+3V08 STM1001T

+3V3
2 3

2K2

1 not Reset 1nF

VCC GND

VS S
GND * these values are given only as typical example

GND GND

9/27

4 Boot management

AN1775

4

Boot management
Three different boot modes are available and can be enabled by means of three input pins: BOOTEN, BOOT0 and BOOT1. The following table describes the different boot mode configurations.
BOOTEN 0 1 1 1 1 BOOT0 x 0 1 0 1 BOOT1 x USER: boot from internal FLASH memory 0 0 1 1 Reserved RAM: boot from internal RAM memory EXTMEM: boot from external memory mapped on the EMI interface at 0000 0000h address. BOOT Mode

The following figure gives an implementation example of boot management for STR71x devices. BOOT0 and BOOT1 are alternate function pins used for boot configuration during the RESET phase (floating-input configuration), so they can be used afterwards in the application as standard I/Os. For more details concerning boot configuration, refer to the device reference manual. Figure 7. Boot mode selection implementation example
3V3
10K*

STR71x 3V3 BOOTEN
10K*

3V3
10K*

GND GND

nSTDBY 3V3
10K*

BOOT0 BOOT1 TEST
GND

GND
* these values are given only as typical example

Note: 1 As the nSTDBY pin has a floating input configuration, an external pull-up has to be provided to avoid remaining in stand-by mode. 2 The TEST pin of the STR71x must always be forced to ground (ST reserved test pin)

10/27

AN1775

5 Debug management

5

Debug management
The Host/Target interface is the hardware equipment that connects the Host to the application board. This interface is made of three components: a hardware debug tool, such as Micro-ICE from ARM, a JTAG connector and a cable connecting the host to the debug tool. Figure 8 shows the connection of the host to the STR71x board. Figure 8. Host to board connection
ICE Debug tool ICE connector

HOST PC STR71x BOARD

Power Supply

5.1

ICE debug tool
ICE Debug tool is a host interface that connects a PC to an STR71x development board featuring a debug interface as shown in Figure 8. The Embedded ICE is an intelligent host interface that provides fast access to host services, access to on-chip emulation and debug facilities. When you are using the ST7R71x board as stand-alone system, the ICE Debug tool can be used to download programs. The STR71x development kit supports the ARM RealView ICE Micro Edition. The Micro-ICE is plugged in to the host via a USB cable.

5.2

JTAG / ICE connector
The ICE connector enables JTAG hardware debugging equipment, such as RealView-ICE, to be connected to the ST7R71x board. It is possible to both drive and sense the system-reset line, and to drive JTAG reset to the core from the ICE connector. The Figure 9 shows the ARM ICE connector pin-out. The STR71x has a user debug interface. This interface contains a five-pin serial interface conforming to JTAG, IEEE standard 1149.1-1993, "Standard Test Access Port-Scan Boundary Architecture". JTAG allows the ICE device to be plugged to the board and used to debug the software running on the STR71x. JTAG emulation allows the core to be started and stopped under control of the connected debugger software. The user can then display and modify registers and memory contents, and set break and watch points.

11/27

5 Debug management

AN1775
Ice connector implementation
3V3 3V3
JTAG Connector CN9 CONN_2*10 RA_IDC

Figure 9.

3V3

STR71x nJTRST JTDI JTMS JTCK JTDO nRSTIN DBGRQS
10K* GND GND 10K*

(1) VTref (3) nTRST (5) TDI (7) TMS (9) TCK (11) RTCK (13) TDO (15) nSRST (17) DBGRQ (19) DBGACK**
See
3V3

(2) (4) (6) (8) (10) (12) (14) (16) (18) (20)

J4 GND
10K*

Note 1 J4

22K T R1 B C8 4 6

GND
10K
50v 10nF

GND

47K

T R2 B C8 4 6

GND

GND

GND

* these values are given only as typical example ** The Debug acknowledge to JTAG equipment (DBGACK pin) is not used.

Note: 1 In order for JTAG and Chip Reset to be synchronized the J4 jumper must be fitted. 2 STR71x has a Debug Request (DBGRQS) pin, on 144-pin packages only. This active high signal can be used to force the core to enter Debug Mode, giving the Emulation system access to internal resources (code, registers, memory, etc). This pin must be kept LOW when emulation is not being used. The following table describes the JTAG connector pins:
Std Name nTRST STR71x JTRST Description Test Reset (from JTAG equipment) Test data in (from JTAG equipment) Test mode select (from JTAG equipment) Function This active LOW open-collector is used to reset the JTAG port and the associated debug circuitry. It is asserted at power-up by each module, and can be driven by the JTAG equipment. TDI goes down the stack of modules to the motherboard and then back up the stack, labelled TDO, connecting to each component in the scan chain. TMS controls transitions in the tap controller state machine. TMS connects to all JTAG components in the scan chain as the signal flows down the module stack.

TDI

JTDI

TMS

JTMS

TCK

JTCK

TCK synchronizes all JTAG transactions. TCK connects to all JTAG components in the scan chain. Series termination resistors are used to reduce reflections and maintain good Test clock (from signal integrity. TCK flows down the stack of modules and JTAG connects to each JTAG component. However, if there is a equipment) device in the scan chain that synchronizes TCK to some other clock, then all down-stream devices are connected to the RTCK signal on that component.

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5 Debug management

Std Name

STR71x

Description

Function Some devices sample TCK (for example a synthesizable core with only one clock), and this has the effect of delaying the time that a component actually captures data. Using a mechanism called adaptive clocking, the RTCK signal is returned by the core to the JTAG equipment, and the clock is not advanced until the core had captured the data. In adaptive clocking mode, the debugging equipment waits for an edge on RTCK before changing TCK.

RTCK

Return TCK (to GND JTAG (not used) equipment)

TDO

JTDO

Test data out (to JTAG TDO is the return path of the data input signal TDI. equipment) nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when a board has been reset by the user. When the signal is driven LOW by the reset controller on the core module, the motherboard resets the whole system by driving nSYSRST low. DBGRQ is a request for the processor core to enter debug state.

nSRST

nRSTIN

System reset (bidirectional)

DBGRQ

DBGRQS Debug request (not used (from JTAG w/ 64pin) equipment)

Debug GND acknowledge DBGACK (not used) (to JTAG equipment)

DBGACK indicates to the debugger that the processor core has entered debug mode.

For more details on the JTAG port refer to the IEEE standard 1149.1-1993, "Standard Test Access Port-Scan Boundary Architecture" specification.

13/27

6 Reference Design

AN1775

6
6.1

Reference Design
Main
This reference design is based on the STR710FZ2T6, a highly integrated microcontroller, running at 48 MHz that combines the popular ARM7TDMITM 32-bit RISC CPU with 256 Kbytes of embedded flash, 64 Kbytes of high speed SRAM, and numerous on-chip peripherals.

6.1.1

Clock

+3.3 V surface mounted 16 MHz oscillator provides the main clock source: S113, please refer to Section 2.1 on page 6 for more details. RTC real-time clock for wakeup from standby mode with 32 KHz crystal: Y101, please refer to Section 2.2 on page 6 for more details.

6.1.2

Reset
One push button S112 is used to generate a hardware reset, please refer to Section 3 on page 9 for more details.

6.1.3

Boot mode
Three switches S108, S109 and S110 are used to select the boot Mode, please refer to Section 4 on page 10 for more details.

6.1.4

Wake-Up
S111 push button is used to exit from STANDBY mode (power supply voltage removed except Real time Clock). For more details, please refer to the STR71x reference manual.

6.2

Power supplies
Power to the board is supplied using a power supply providing 5 V DC to the board. All other required voltages are provided by the on-board voltage regulator 3V3 LD1085V33 and Zener Diode LM4040 for ADC input voltage. For more details, refer to LD1085V33, LM4040 datasheets and Section 1 on page 4.

6.3

USB full speed interface
USB full speed interface device supported via type B connector. The USB clock uses a separate 48 MHz oscillator. A transistor circuit is used to indicate the cable status (Cable connected USB/IND pin = 0 logic, Cable deconnected = USB/IND pin = 1 logic).

14/27

AN1775

6 Reference Design

6.4

CAN interface
A general purpose, asynchronous serial I/O data port connected through a 9-pin D-type male connector with micro switches selectable between High or Low bus output S702, and between Standby or Slope control S700. For more details, refer to CAN transceiver SN65HVD230D datasheet.

6.5

RS232 serial interface
A general purpose, asynchronous serial I/O data ports is connected through 9-pin D-type male connectors. RS232 connects directly to UART0, transmit and receive only (null modem). RTS is shorted to CTS and DTR is shorted to DSR at the connector. For more details, refer to RS232 transceiver ST3232 datasheet.

6.6
6.6.1

Serial ROM
SPI Flash
1-Mbit SPI serial flash connected to the buffered serial peripheral interface (BSPI). Switch S603 is used to enable or disable write protect (pull down = Write protect, pull up = Write enabled). For more details, refer to SPI Flash M25P10-A datasheet.

6.6.2

I2C EEPROM:
8-kbit EEPROM connected to the I2C0 interface, Switch S600 is used to enable or disable write protect (pull down = Write protect, pull up = Write enabled). For more details, refer to I2C Eeprom M24C08 datasheet. The values R614 and R616 are dependent on the I2C communication speed. For more details on theses values, please refer to the STR71x reference manual.

6.7

JTAG interface
Refer to the section Section 5 on page 11.

6.8

SRAM
Two SRAM 2M byte are connected to External Interface Memoy EMI and mapped from 0x6200 0000 to 0x623F FFFF. For more details, refer to the SRAM memory TC55V8200FT-12 datasheet.

15/27

6 Reference Design

AN1775

6.9

Flash
One Flash 2M word is connect to External Interface Memoy EMI and mapped from 0x6000 0000 to 0x603F FFFF (boot bank). For more details, refer toFlash memory M28W320ECB datasheet.

6.10

LCD interface
LCd 2 * 16 is connected to external interface memory EMI. Address 2 A2 is used as the LCD register address signal. Region space available from 0x6400 0000 to 0x65FF FFFF

6.11

Conclusions and recommendations

System clock jitter values decrease when the system clock is delivered by STR71x internal PLL1 (comparing to the jitter values on the external oscillator inputs), because the noise injected in the CLK pin input was filtered by the internal PLL. It is possible to use one single external 4MHz oscillator to generate both core, peripheral's clocks and 48MHz USB clock to minimize and save board cost and space. With this single external oscillator generating both the system clock using PLL1 and the 48Mhz USB clock using PLL2, the STR710/STR711 has all the characteristics to pass the requirements for USB revision 2.0 full speed device test and get the USB certification.

Par ticular care must be taken to decrease external oscillator noise while routing its clock on board.

16/27

7

AN1775

1 +3V3 C102 +3V3 33nF C103 1.0uF 129 128 55 54 not RESET not RESET VCC VSS D 1 2 2K2 D105 STM1001T (3.08V) R130 10uF C101 +3V3 +3V3AN 47 51 6 22 40 83 104 113 138 66 58 59 +3V3 S111 SW-PB C100 R127 1K R128 STR710 S112 SW-PB JTAG.Sch 3 +3V3 C104 1nF V33_1 V33_2 V33_3 V33_4 V33_5 V33_6 V33_7 AVDD P0.15_WAKEUP not STDBY V18_1 VSS18_1 V18_2 VSS18_2 V18BKP VSSBKP 10nF R129 10K

2

3

4

5

6

+3V3

BOOT_EN R100

BOOT.0

10K R101

SW SPDT S108

D

BOOT.1

10K R102

SW SPDT S109

10K

SW SPDT S110

Schematics

R122 R103 R104 22 22 22

7 8 11 12 P2.0_not CS.0 P2.1_not CS.1 P2.2_not CS.2 P2.3_not CS.3 CK CKOUT DBGRQS DBGRQS 33 page 8 CAN.Sch CAN_RX CAN_TX page 7 88 89 USB.Sch RTCXTO 32KHz C106 15pF 50V CK R132 3 RTCXTO RTCXTI BOOT_EN P0.9_U0.TX_BOOT.0 P0.11_U1.TX_BOOT.1 P1.11_CANRX P1.12_CANTX 16 BOOT_EN 144 BOOT.0 3 BOOT.1 50 RTCXTO 49 RTCXTI 46 CK 45 CKOUT OUT EN
VCC +3V3

JTDI JTDO JTCK JTMS not JTRST not RSTIN S113 16MHz OSC

30 33 32 31 34 52 not RESET JTDI JTDO JTCK JTMS not JTRST not Reset 1

R131 10K

SRAM.Sch

FLASH.Sch

ADD (23:0)

ADD (23:0)

RTCXTI Y101 C C113 15pF 50V

DATA (15:0)

DATA (15:0)

C

not CS_SRAM not OE not WR0 not WR1 USBDP USBDN P1.10_USBCLK P2.11 P2.12 Serial_ROM.Sch page 9 USBDP USBDN USBCLK USBV_IND USB_PULL_UP not Reset 90 91 106 25 26

page 4

not CS_FLASH not OE not WR vpp not RESET

page 3

*Switch used for ADC calibration +2V5AN S115

LCD.Sch 9 10 RX TX ADCIN RX TX 71 page 6

ADD0 ADD1 ADD2 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 ADD22 ADD23 ADD24 A.0 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 A.14 A.15 A.16 A.17 A.18 A.19 P2.4_A.20 P2.5_A.21 P2.6_A.22 P2.7_A.23 P1.14_HRXD_I0.SDA P1.13_HCLK_I0.SCL P0.4_S1.MISO P0.5_S1.MOSI P0.6_S1.SCLK P0.7_S1.SSN P1.8 SDA SCL MISO MOSI SCLK SSN not S P0.13_U2.RX_T2.OCMPA P0.14_U2.TX_T2.ICAPA P1.0_T3.OCMPB_AIN.0 108 107 127 140 141 142 86 SW SPDT S114 ADCIN RS232.Sch RX TX page 5

98 99 100 101 102 114 115 116 117 118 119 120 121 122 130 131 132 133 134 135 13 14 15 17

DATA (7:0)

notE

R139 4K7

ADD2 1

RS P0.0_S0.MISO_U3.TX P0.1_S0.MOSI_U3.RX P0.2_S0.SCLK_I1.SCL P0.3_S0.SSN_I1.SDA P2.9 P2.10 23 24 Button_1 Button_2 123 124 125 126 LED_P0.0 LED_P0.1 LED_P0.2 LED_P0.3

U101A

Figure 10. Reference design top level schematics

B

R/W

2

B

74LCX14 VCC +3V3

page 2

DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 D.0 D.1 D.2 D.3 D.4 D.5 D.6 D.7 D.8 D.9 D.10 D.11 D.12 D.13 D.14 D.15 LED_P0.0 LED_P0.1 LED_P0.2 LED_P0.3 R135 560 R136 560 R141 560 R142 560

61 62 63 64 65 78 79 80 81 82 92 93 94 95 96 97

+3V3 D106 D107 D108 D109 LED R137 10K LED LED LED Button_1 S116 SW-PB

+3V3

R133 R134 R140 22 22 22

2 137 136 not RD not WE.0 not WE.1 P2.8 18

R138 10K Button_2 S117 SW-PB C114 0.1uF

DBGRQS VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7

38 36 35 44 TEST TEST NU DBGRQS

P1.2_T3.OCMPA_AIN.2 P1.1_T3.ICAPA_AIN.1 P1.3_T3.ICAPB_AIN.3 P1.4_T1.ICAPA P1.5_T1.ICAPB P1.6_T1.OCMPB P1.7_T1.OCMPA P1.9 P1.15_HTXD P0.8_U0.RX_U0.TX P0.10_U1.RX_U1.TX_SCDATA P0.12_SCCLK P2.13 P2.14 P2.15

73 72 74 75 76 77 85 105 111 143 1 4 27 28 29

C115 0.1uF

AVSS

A

A Title

42 84 103 112 139 5 21

67

STR710 MCU
Size B Date: File: Number

* For not used pins set to logic le el by software v
2 3 4 5

1
22-Jun-2005

Revision Sheet 1 of 10 Drawn By: 6

1.0

1

7 Schematics

17/27

18/27
2 3 4 5 6 D +5

7 Schematics

1

D

Figure 11. LCD interface

R200 4K7 R201 R202 15 16 C DATA (7:0) A K

C

DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VCC5V R/W E RS GND VO LCD LWM 1602 B-BG/SYN 3 1 2 DIR G 74LCX245 VCC +3V3 1 19

18 17 16 15 14 13 12 11

2 3 4 5 6 7 8 9

7 8 9 10 11 12 13 14

+5

5 6 4

C203 10uF 16V

C204 0.1uF

RnotW U200A notE 74LCX14 VCC +3V3 RS 1K C205 100pF R209 1 2

R203 10K

B

B

A Title Size B Date: File: 2 3 4 5 Number

A

LCD
2 22-Jun-2005 Sheet 2 of Drawn By: 6 Revision 10 1.0

AN1775

1

AN1775

1

2

3

4

5

6

Figure 12. EMI Flash
D

D

DATA (15:0)

ADD (23:0) R305

C

C

+3V3 +3V3 +3V3

R306 10K R308 10K

R307 10K

ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD1 4 ADD1 5 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 not CE not WE not OE VPP 13 not WP not RP FLASH M28W320ECB VCC +3V3 vpp 26 11 28 14 12

25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10

B not RESET

not CS_FLASH not WR not OE

B

A Title Size B Date: File: 2 3 4 5 22-Jun-2005 Sheet 3 of Drawn By: 6 10

A

FLASH
Number 3 Revision Text

1

7 Schematics

19/27

20/27
2 3 4 5 6

7 Schematics

1

Figure 13. EMI SRAM

D

D

DATA (15:0) ADD (23:0)

R401

R402

C

IO_1 IO_2 IO_3 IO_4 IO_5 IO_6 IO_7 IO_8

22 24 31 33 49 51 4 6 IO_1 IO_2 IO_3 IO_4 IO_5 IO_6 IO_7 IO_8

DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 22 24 31 33 49 51 4 6 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15

C

+3V3 +3V3

+ 3V 3

R403 10K R405 10K

R404 10K

ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A 14 A15 A16 A17 A18 A 19 A20 not WR1 15 13 16 42 15 13 16 42 not WE not CE N_CE2 not OE SRAM TC55V8200FT-12 VCC +3V3

11 10 9 8 7 48 47 46 45 44 38 37 36 35 34 21 20 19 18 17 39 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21

11 10 9 8 7 48 47 46 45 44 38 37 36 35 34 21 20 19 18 17 39

not WR0 not CS SRAM _ not OE

B

not WE not CE N_CE2 not OE SRAM TC55V8200FT-12 VCC +3V3

B

A Title Size B D a te : File: 2 3 4 5 22-Jun-2005 10 Sheet 4 of 10 Drawn By: 6 Number 4

A

SRAM
Re vis i on 1.0

AN1775

1

AN1775

1

2

3

4

5

6

D

D

Figure 14. RS232 interface

+3V3 C501 0.1uF 25V C502 0.1uF 25V 2 C C2+ C503 0.1uF 25V C1C25 J500 4 6 V-

1 C1+ C500 0.1uF 25V 3

TX RX T1OUT T2OUT R1IN R2IN DB9 male

11 10 12 9 T1IN T2IN R1OUT R2OUT R510 ST3232 VCC +3V3

V+

C

14 7 13 8

1 6 2 7 3 8 4 9 5

B

B

A Title Size B Date: File: 2 3 4 5 22-Jun-2005 Sheet 5 of Drawn By: 6 10

A

RS232
Number 5 Revision 1.0

1

7 Schematics

21/27

22/27
2 3 4 5 6 D +3V3 +3V3 +3V3 +3V3 +3V3 R616 4K7 1 2 3 E1 E2 E3 SCL not WC I2C_EEP OM M24C08 R VCC +3V3 C SDA SDA 5 6 7 R603 R614 4K7 +3V3 R600 R601 R602 10K 10K 10K R615 10K S600 P SW S DT * connect to pull-up by default SCL

7 Schematics

1

D

Figure 15. Serial ROM interface

C

+3V3 +3V3 R619 MOSI D C SCLK S603 not S not S not W not HOLD SPI_FLAS M25P10-A H VCC +3V3 SW S DT P * connect to pull-up by default 1 3 7 6 5 Q 2

R617 10K R618 10K

MISO

B

B

+3V3

R620 10K SSN

A Title

A

SERIAL MEMO Y R
Number 22-Jun-2005 3 4 5 Size B Date: File: 6 Revision 1.0

AN1775

1

2

Sheet 6 of 10 Drawn By: 6

AN1775

1

2

3

4

5

6

D

D

Figure 16. CAN interface

+3V3 +3V3

R701 10K SW S DT P +3V3 S700 R703 10K

C R700 CAN_TX CAN_RX SN65HVD230D VCC +3V3 R704 120 DB9 R702 10K 1 2 3 4 D GND VCC R RS CANH CANL Vref 8 7 6 5 1 6 2 7 3 8 4 9 5 J701

C

S702 S SW-SP T B

B

A Title CAN Number 7 Size B Date: File: 2 3 4 5 22-Jun-2005 Revision 1.0

A

1

Sheet 7 of 10 Drawn By: 6

7 Schematics

23/27

24/27
2 3 4 5 6 D +3V3 +3V3 R800 10K R801 10K R802 10K

7 Schematics

1

D

Figure 17. JTAG interface

JP801 not JTRst JTDI JTMS JTCK JTDO DBGRQS R804 10K HEADER 10X2 R803 10K R805 10K

C

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

C

not Reset +3V3 S801 SW SPST

*Switch closed by default

R817 22K B R818 R807 47K Q800 BC846 10K Q803 BC846 C800 0.01uF

B

A Title

A

JTAG
Size B Date: File: 13-Sep-2005 3 4 5 Sheet 8 of 10 Drawn By: 6 Number 8 Revision 1.0

AN1775

1

2

AN1775

1

2

3

4

5

6

D +3V3 R900 47K USBV_IND R905 56K R904 56K US _PULL_UP B R901 1K5 Q900 BC547E

Figure 18. USB interface
D C

C

USBDN USBDP R902 R903 C900 15pF C901 15pF

0 0

1 2 3 4

R906 USB_CON VBUS DN DP GND

+3V3 B J900 48MHz C OS USBCLK 3 OUT EN 1 VCC +3V3 R907 10K

B

A Title

A

USB
Numbe9 r Size B Date: File: 22-Jun-2005 3 4 5 1. Revision0

1

2

Sheet 9 of 10 Drawn By: 6

7 Schematics

25/27

GND

+3V3 +5V C1015 C1016 C1017 C1019 100uF 10V 100uF 10V 10nF 50V 10nF 50V C1021 100nF 25v C1022 C1023 100nF 25V 100nF 25v

2

26/27
2 3 4 5 6 +5V +3V3 R1001 1K C1045 10uF 16V C1046 C1047 0.1uF 25V 10nF 50v D1002 LM4040 L1001 FBEAD +3V3AN +2V5AN D C1000 47uF 16V C1001 C1002 C1003 C1004 100nF 25V 100nF 25V 100nF 25V 100nF 25V +3V3 3 C1018 10uF 10V C1020 10nF 50V

7 Schematics

1

D

R1000

J1000 2 +5V 1 JACK +5V

1

SV

CV

3

2

SG

CG1 CG2 CG3

4 5 6

BNX002

+5V 1 C1014 10nF 50V U1001 VOLT_REG_3V3 Vin Vout

Figure 19. Power schematics

C

C1011 10uF 10V

C

+3V3

C1012 10uF 10V

C1013 10uF 10V

R1002 1K

R1003 560

+3V3

D1000 LED C1028 C1030 C1032 C1034 C1036 C1038 C1040 C1042 C1044 100nF 25V 100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V 100nF 25V

D1001 LED B

B

C1024 C1026 100nF 25V 100nF 25V

+3V3

C1027 C1025 100nF 25V 100nF 25V

C1029 C1031 C1033 C1035 C1037 C1039 C1041 C1043 100nF 25V 100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V

A Title

A

POWER
Number 22-Jun-2005 3 4 5 Size B Date: File: 10 Revision 1.0

AN1775

1

2

Sheet 10 of 10 Drawn By: 6

AN1775

7 Schematics

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Document Number: 10332



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