AN1957 APPLICATION NOTE
Microprocessor Supervisor Functions
Designers of microprocessor systems have to achieve high reliability, in the face of a large number of threats to stability or even correct functioning (such as, voltage drops, glitches, long ramp-up times, programs stuck in endless loops, etc.). Supervisor circuits, from STMicroelectronics, provide highly effective solutions for minimizing the risks of system failure, and for ensuring the safe running of the system, at a low cost. The members of the ST Supervisor family offer various combinations of functions. This Application Note describes the main Supervisor functions and features, to help the user to understand their principles and the advantages of using them, through the description of waveforms, recommended values, and hardware hookup diagrams. Overview of ST Supervisors Microprocessor Supervisors STM705, STM706, STM706T/S/R, STM707, STM708, STM708T/S/R, STM813L, STM706P, STM6321L/M, STM6321T/S/R, STM6821L/M, STM6821T/S/R, STM6823L/M, STM6823T/S/R, STM6824L/M, STM6824T/S/R, STM6825L/M, STM6825T/S/R Microprocessor Supervisors with Switchover M40SZ100W, M40Z111, M40Z300W, STM690A, STM692A, STM690T/S/R, STM802L/M, STM802T/ S/R, STM703, STM704, STM704T/S/R, STM806T/S/R, STM805L, STM805T/S/R, STM804T/S/R, STM817L/M, STM818L/M, STM819L/M, STM795T/S/R TIMEKEEPERTM Supervisors M41ST95W, M41ST87W, M41ST87Y, M41ST85W, M41ST85Y, M41T315V, M48T201V, M48T201Y, M48T212V
This Application Note is dedicated to the Microprocessor Supervisor and Microprocessor Supervisor with Switchover families.
March 2005
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TABLE OF CONTENTS
Overview of ST Supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Supervisor Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 POWER-ON RESET AND LOW VOLTAGE DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram Showing the Supervisor Reset Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 1. Supervisor Reset Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reset Waveforms for the Microprocessor Supervisor Devices . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Power-On Reset and Low Voltage Detect Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Reset Timings for the STM703/704 Supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Reset Thresholds (VRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Hardware Hookup for the STM703/704 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Hardware Hookup for the STM703/704 Supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 POWER-FAIL COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram of a Power-Fail Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Block Diagram of a Power-Fail Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hardware Hookup for the STM692A Supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Example calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Recommended Resistances for some VTRIP Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Hardware Hookup for the STM692A Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Example of Power-Fail Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Power-Fail Values for all Microprocessor Supervisors (except for the devices mentioned in Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Power-Fail Values for 3V Microprocessor Supervisors with Battery Switchover (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . . . . . . . . . 10 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7. Logic Diagram of a Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Watchdog Timer Input and Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Watchdog Timer Time-out Value for the STM705 Supervisor . . . . . . . . . . . . . . . . . . . . . 11 Hardware Hookup for the STM705 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9. Hardware Hookup for the STM705 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BATTERY SWITCHOVER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10.Block Diagram of a Battery switchover Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switchover Waveforms for the STM806R Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 11.Battery Switchover Waveforms for the STM806R Supervisor. . . . . . . . . . . . . . . . . . . . . 14 Figure 12.Switchover Waveforms with Hysteresis Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. Switchover Values for the STM806R Supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Hardware Hookup for the STM806R Supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13.Hardware Hookup for the STM806R Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Hardware Hookup for the STM795 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14.Hardware Hookup for the STM795 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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CHIP ENABLE GATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 15.Chip Enable Gating Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical Waveforms for the STM818 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 16.Typical Waveforms for the STM818 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. Typical values for the STM818 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Hardware Hookup for the STM818 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17.Hardware Hookup for the STM818 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 BATTERY FRESHNESS SEAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 18.Typical Waveforms for the STM817/818/819 Supervisors . . . . . . . . . . . . . . . . . . . . . . . 20 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Table 1. Supervisor Options
3V or 5V Supervisor STM690T/S/R STM690A(3) STM692A(3) STM703(4) STM704(4) STM704T/S/R STM705(5) STM706(5) STM706T/S/R STM706P(6) STM707 STM708 STM708T/S/R STM795T/S/R STM802L/M STM802T/S/R STM804T/S/R(7) STM805T/S/T(7) STM805L STM806T/S/R STM813L STM817L/M STM818L/M STM819L/M
Note: 1. 2. 3. 4. 5. 6. 7.
Active Active Manual Battery Chip- Battery Power-fail Watchdog Watchdog Low High Reset Switch Enable Freshness Comparator Input output over Gating Seal RST(1) RST(1) Input ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !(2) ! ! !(2) !(2) ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
3V 5V 5V 5V 5V 3V 5V 5V 3V 3V 5V 5V 3V 3V 5V 3V 3V 3V 5V 3V 5V 5V 5V 5V
Push-Pull Output (unless otherwise specified). Open drain output. STM690A has a typical Reset Threshold of 4.65V and STM692A has a typical Reset Threshold of 4.40V. STM703 has a typical Reset Threshold of 4.65V and STM704 has a typical Reset Threshold of 4.40V. STM705 has a typical Reset Threshold of 4.63V and STM706 has a typical Reset Threshold of 4.38V. The STM706P is identical to the STM706R, except for its Reset output which is active High. STM804T/S/R and STM805T/S/R have different minimum and maximum Reset Thresholds with VCC falling and VCC rising (see datasheet).
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POWER-ON RESET AND LOW VOLTAGE DETECT
After system start-up, a certain period of time is required for the power supply voltage to stabilize. For this reason, ST Supervisor devices generate a Reset pulse after power-up (the minimum pulse width is trec = 140ms, see Table 2.). Over the trec period, during which reset is asserted, the clock is stabilized and the registers are set to their default values. This function is called Power-On Reset (POR). Some designers attempt to use RC circuits, instead of a Reset implementation, because it is cheaper. But it is also unsafe and unreliable. RC circuits are not suitable for use as professional devices in industrial environments (see REFERENCES section, AN1772). Another major function is Low Voltage Detect (LVD), which detects power supply brownouts and glitches. Whenever VCC falls below the Reset threshold (VRST), the Reset output is asserted and remains so trec after VCC increases above the Vrst threshold. In the case of an RC circuit, no minimum Reset pulse width is guaranteed. Also, if the triggering event is a narrow glitch, an RC circuit will only generate a poor Reset, which may lead to malfunctioning of the microprocessor (failing to load registers correctly, executing invalid instructions, processing incorrect data, etc.). Some Supervisor devices include a Manual Reset input (MR) that can be used by the user, or the external device, to generate a Reset. Typically, a low-cost push-button switch is connected to the Manual Reset input, which allows the user to restart the processor without turning off the power. No additional components are needed because Supervisor devices already include a debounce circuit that filters the noise of contact closure. This function can be used to debug, to perform the final test of a processor, or to restart a processor that is locked. The Reset button is also useful in systems where the processor is never turned off, even when the system is in Off mode. Some processors include an internal Reset that operates correctly under stable power supply conditions, but usually has difficulties in handling voltage drops and transients as well as looser tolerances for Vrst. The use of an external Reset is therefore recommended. Block Diagram Showing the Supervisor Reset Feature Figure 1. illustrates the Power-On Reset, Low Voltage Detect and Manual Reset features. The Reset is asserted if one of the following events occurs:
system start-up; Brownout, voltage drop, significant transient or glitch, negative voltage spike etc. on the power supply line; Manual Reset.
Figure 1. Supervisor Reset Features
VCC
MR
RESET Power-On Reset Low Voltage Detect
RST RST
ai10104
Note: VCC is the supply voltage, MR is the Manual Reset input. RST and RST are Reset outputs. Supervisor devices can have an active-Low output (RST), an active-High output (RST) or both.
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Reset Waveforms for the Microprocessor Supervisor Devices When the input voltage level reaches the Reset threshold (VRST) after system power-up, the Supervisor holds the Reset output signal (RST) Low for a minimum time of trec before driving it High again (see Figure 2.). Switching the Manual Reset signal (MR) to Low, causes the RST signal to go Low. RST remains Low as long as MR is kept Low, and returns High trec after MR has been released. All Microprocessor Supervisor devices have glitch immunity. That is, the minimum MR pulse width required to Reset the output is fixed. All shorter pulses are ignored. The Supervisor also reacts to voltage drops, brownouts and significant glitches. If the input voltage falls below VRST, the Reset output is asserted. Note that some Supervisor devices have a Reset output that is active High (RST). They therefore have a waveform that is the inversion of the one that is shown in Figure 2. Figure 2. Power-On Reset and Low Voltage Detect Waveforms
VCC VRST Manual Reset Power-up Voltage drop
MR
tMLMH RST trec tMLRL Manual Reset Glitch Immunity
AI10105
trec
trec
Note: VRST is the Reset threshold, see Table 3. for values.
Table 2. Reset Timings for the STM703/704 Supervisor
Symbol tMLMH tMLRL trec Al t tMR tMRD MR Pulse Width MR to RST Output Delay VRST to RST High and MR High to RST High Manual Reset Glitch Immunity Parameter Min. Max. Min. Typ. Value 150 250 140 100 U ni t ns ns ms ns
Table 3. Reset Thresholds (VRST)
Supervisor Min. STM706P/70xR STM70xS STM70xT STM692A/704/706/708, 8xxM STM690A/703/705/707, 8xxL 2.55 2.85 3.00 4.25 4.50 Reset threshold (VRST) Typ. 2.63 2.93 3.08 4.40 4.65 Max. 2.70 3.00 3.15 4.50 4.75 V V V V V Unit
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Hardware Hookup for the STM703/704 Supervisor In the example of Figure 3., the Reset output is asserted in three cases:
during system power-up, until VCC is stabilized (VCC is greater than VRST) for a duration of trec after a VCC drop (VCC falls below VRST) by pressing the Manual Reset push-button (the Reset button should be held for at least for tMLMH).
The Manual Reset input is not necessarily connected to a physical push button switch, it can also be connected to a peripheral, provided that a minimum MR pulse width of 150ns is ensured. If the Reset circuit is placed in a noisy environment, or if MR is driven from long cables, it is recommended to use an external 0.1F capacitor, as shown in Figure 3. The MR input includes an internal pull-up resistor. So in applications where the MR input is not used, the pin can be left unconnected. The MR input can be driven with a TTL output, a CMOS output, or an open drain output. It is always appropriate to connect a decoupling capacitor in parallel with the power supply. The recommended value is 1F. Figure 3. Hardware Hookup for the STM703/704 Supervisor
VCC 1 VCC GND C1 1F STM703/704 VOUT VBAT 8 RST 7 MR PF0 6 5 C2 0.1F Reset Button
Microprocessor
2 VCC 3 VSS 4 PFI
SO8/TSSOP8
RST
AI10106
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POWER-FAIL COMPARATOR
Inadvertent or unexpected power loss can cause a number of malfunctions in a system (data loss, uncontrolled program status, indeterminate processor state, etc.). For a reliable design, systems should receive early power failure warning, to leave enough time for the microprocessor to start a safeguard routine, for backing up crucial data, registers, etc. Power-fail comparators are used to monitor unregulated power supplies. Their reaction to power loss is very fast, and can provide enough time to execute all the necessary safeguard processes that precede an expected power failure (see REFERENCES section, AN1336). Block Diagram of a Power-Fail Comparator The power-fail comparator works like an ordinary comparator with hysteresis (see Figure 4.). The PowerFail Input (PFI) is compared to an internal reference voltage, the power-fail threshold, VPFI. If the voltage on PFI is less than VPFI, the Power-Fail Output (PFO) is asserted. Figure 4. Block Diagram of a Power-Fail Comparator
PFI PFO
VPFI
ai10107
Hardware Hookup for the STM692A Supervisor The Power-fail comparator can be used in many different ways. It is most commonly used as an Early Power-Fail Warning (see Figure 5.) to monitor an unregulated supply voltage. Two external resistors R1 and R2 form a voltage divider to set the voltage level (VTRIP) below which PFO is asserted (see the waveforms shown in Figure 6.). Usually, a value is selected for R2, then R1 is derived using the following formula: VT R I P V P F I R 1 = R 2 × ----------------------------- , Where VPFI = 1.25V. VP F I The sum of the resistances should be about 1M to minimize power consumption, and the tolerance of the resistor should not exceed 1%, to ensure that there are not large variations in the sensed voltage. Example calculation. We have: VTRIP = 11.5V and VPFI = 1.25V. Let us put: R2 = 100k VT R I P VPF I 3 11.5 1.25 R1 is calculated as follows: R 1 = R 2 × ----------------------------- = 100 10 × ------------------------- = 820 k VP F I 1.25
Thus R1 = 820k.
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Table 4. Recommended Resistances for some VTRIP Voltages
VTRIP (V) 8.5 10.0 11.5 12.5 15.0 R1 (k) 750 910 820 820 1100 R2 (k) 130 130 100 91 100
Figure 5. Hardware Hookup for the STM692A Supervisor
~220V ~120V Power Supply VUNREG Regulator VCC C STM692A R1 VPFI R2 1 VOUT 2 VCC 3 VSS VBAT 8 RST 7 WDI 6 5 1F
Microprocessor VCC
PF0 4 PFI SO8/TSSOP8
NMI GND
ai10108
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Example of Power-Fail Waveforms Figure 6. shows the case of a voltage drop. The unregulated power supply voltage (VUNREG) begins to decrease. As it falls below VTRIP, at t0 in Figure 6., PFO is asserted, invoking a non-maskable interrupt in the microprocessor, and causing the execution of the safeguard routine. The microprocessor continues operating until Reset is asserted. From t1, the power supply voltage (VCC) starts to fall. At t2 Reset is asserted and Write Protect occurs. This means that the safeguard routine cannot last more than t2 - t0. Figure 6. Voltage Drop
VUNREG, VCC VUNREG VTRIP VCC VRST
Voltage Drop +12V +11.5V +5V +4.4V t
VPFO
t0
t1 t2
t
ai10109
Note: At t0 the voltage drop is detected; at t1 VCC begins to fall; at t2 Reset is asserted and/or Write Protect occurs.
Table 5. Power-Fail Values for all Microprocessor Supervisors (except for the devices mentioned in Table 6.)
Symbol V PFI Parameter Power-fail threshold Typ. Value 1.25 Unit V
Table 6. Power-Fail Values for 3V Microprocessor Supervisors with Battery Switchover (STM690/704/802/804/805/806)
Symbol V PFI Parameter Power-fail threshold Typ. Value 1.237 Unit V
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WATCHDOG TIMER
The role of a Watchdog timer is to prevent system failures that are caused by certain types of hardware errors (non-responding peripherals, bus contention etc.) or software errors (bad code jump, code stuck in loop etc.). The watchdog timer has an input, WDI, and an output, WDO (see Figure 7.). The input is used to clear the timer periodically within the specified time-out period, tWD (see Table 7.). While the system is operating correctly, it periodically toggles the Watchdog Input, WDI (see Figure 8.). If the system fails, the watchdog timer is not reset, and a system alert is generated: the Watchdog output, WDO, or the Reset output, is asserted (see Figure 8.). Some microprocessors have an integrated watchdog timer, with a time-out period that is software-adjustable. The great disadvantage of this solution, though, is that the integrated watchdog timer uses the same power supply, and clock signal, as the microprocessor. So, a system malfunction may also lead to a failure of the watchdog timer. Figure 7. Logic Diagram of a Watchdog Timer
WDI
Watchdog timer
WDO
ai10110
Note: 1. WDI is the Watchdog Input, WDO is the Watchdog Output.
Figure 8. Watchdog Timer Input and Output Waveforms
Correct operation System of the system failure System Correct operation restar t of the system
WDI
t WDO
tWD
t
ai10111
Note: 1. WDI signal frequencies greater then 50MHz (20ns period) will be filtered. 2. tWD is the Watchdog time-out period. See Table 7. for value.
Table 7. Watchdog Timer Time-out Value for the STM705 Supervisor
Symbol tWD Description Watchdog time-out period Typ. Value 1.6 Unit s
Note: This tWD value is valid for all Microprocessor Supervisors.
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Hardware Hookup for the STM705 Supervisor WDI is usually connected to the output pin of the microprocessor as shown in Figure 5. and WDO is tied to the microprocessor Non-Maskable Interrupt (NMI) or Reset input. The code should take care of clearing the watchdog timer within the time-out period by toggling the microprocessor's I/O pin. Figure 9. Hardware Hookup for the STM705 Supervisor
Microprocessor 1 VCC C 1F STM705 MR WDO RST WDI PF0 SO8 I/O NMI
ai10112
8 7 6 5
2 VCC 3 VSS 4 PFI
In any case, if VCC drops below the Reset threshold (VRST), WDO goes Low even if the watchdog timer has not timed out. The timer remains cleared and does not count for as long as Reset is asserted. The counter automatically restarts after trec expires. In 5V supply devices, the watchdog function may be disabled by floating WDI or tri-stating the driver that is connected to WDI.
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BATTERY SWITCHOVER
A common task of battery switchover devices is to provide an uninterrupted power supply to external devices in the event of voltage drops and brownouts. Battery switchover devices can also be useful in portable devices. When the external power supply (such as the AC power supply adapter) is disconnected, the battery switchover device switches to the internal supply (such as a battery). The use of a battery switchover has the following advantages:
providing continuous and reliable service, even if the external supply fails extending the battery lifetime debouncing the power spikes occurring while connecting and disconnecting the AC adapter.
Battery switchover devices can be used as a main power supply backup for MCUs, memories and other peripherals, and to prevent system failures (see Figure 10.). Diode-OR connections are often used as an equivalent solution. However the diode voltage drop represents a large percentage of the battery voltage, and power supply spikes are not filtered. With an ST Supervisor, the device is supplied from the main power supply as long as the voltage is high enough, even if the battery voltage is greater than the power supply voltage, which saves the battery and extends its lifetime. Instead of a backup battery it is also possible to use a backup capacitor. Recommended capacitor values start from 0.1F. The battery switchover device monitors the power supply voltage, VCC, which is compared to the reference voltage, VSO, as shown in Figure 11. If VCC drops too low, the VOUT output is switched to the battery voltage, VBAT. The comparator includes hysteresis for noise immunity purposes. Figure 10. Block Diagram of a Battery switchover Device
VCC
VBAT
VOUT
VSO
ai10113
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Switchover Waveforms for the STM806R Supervisor The Battery Backup Switchover Voltage (VSO) depends on the Battery Voltage (VBAT) and on the Switchover Threshold, VSW (see Figure 11.). If VSW is lower than VBAT, VSO is equal to VSW. If VSW is greater than VBAT, VSO is equal to VBAT. Whenever VCC falls below VSO, the VOUT output is connected to the battery, VBAT (see Figure 11.). Figure 11. Battery Switchover Waveforms for the STM806R Supervisor
VCC, VBAT
VBAT > VSW, then VSO = VSW VBAT VSW VSO Voltage Drop
VBAT < VSW, then VSO = VBAT VCC VSO Voltage Drop
VOUT
VSW VCC
VOUT VBAT
ai10114
Note: The red line represents the switchover voltage (VSO). The blue line represents the battery switchover circuit output voltage (VOUT), which is switched to VCC, or to VBAT depending on the voltage magnitude.
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STM806R has a voltage hysteresis of 40mV, which gives it good noise immunity. The hysteresis depends on VBAT and VSW as illustrated in Figure 12.:
If VBAT > VSW and VCC falls, the battery switchover detects the switchover threshold VSW and switches VOUT to the backup battery supply. When VCC rises, the voltage level VSW + 40mV is detected and VOUT is switched back to the main power supply (VCC). If VBAT < VSW and VCC falls, the battery switchover detects the voltage level VBAT - 75mV and switches VOUT to the backup battery supply. When VCC rises, the voltage level VBAT - 35mV is detected and VOUT is switched back to the main power supply (VCC).
Figure 12. Switchover Waveforms with Hysteresis Details
VCC, VBAT VBAT > VSW, then VSO = VSW VBAT VCC VSW VSO Voltage Drop Voltage Drop VSO VBAT < VSW, then VSO = VBAT
VOUT
VSW VCC
VOUT VBAT
VCC VBAT VSW VCC
VOUT VSW + 40mV
VCC VSW VBAT VCC VBAT - 75mV
VOUT
VBAT - 35mV
ai10115
Table 8. Switchover Values for the STM806R Supervisor
Symbol V SW Vhys V SO Threshold Hysteresis VBAT < VSW Battery Backup Switchover Voltage VBAT > VSW VSO = VSW V Description Condition Typical Value 2.4 40 VSO = VBAT Unit V mV V
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Hardware Hookup for the STM806R Supervisor Figure 13. shows one particular hardware hookup, using the STM806R Supervisor to switch the power supply source, with good efficiency and without introducing any switching noise. In this case, the battery switchover backups the main power supply of MCU, memories and other peripherals. If sufficient power is available from the backup supply, the system can continue working normally. However it is also possible to run a safeguard routine, and to force the system to the low-power mode, so that the backup power supply can last longer, until the main power supply is restored. Figure 13. Hardware Hookup for the STM806R Supervisor
VCC SRAM VCC GND C 1F 1 STM806R VOUT VBAT 8 RST 7 MR PF0 6 5 3V Battery
2 VCC 3 VSS 4 PFI
SO8/TSSOP8
AI10263
Hardware Hookup for the STM795 Supervisor The VOUT output is able to switch 75mA (maximum). If the peripherals have greater current needs, it is possible to use the Vccsw output of the STM795 device, and to drive the gate of the external PMOS transistor (as shown in Figure 14.). When VOUT switches to the battery, the Vccsw goes High. When VOUT switches back to VCC, Vccsw goes Low again, and the transistor provides current directly from the power supply. Figure 14. Hardware Hookup for the STM795 Supervisor
VCC Microprocessor VCC GND C 1F SRAM VCC GND 1 STM795R VOUT VBAT 8 RST 7 3V Battery E5
2 VCC 4 VSS
3 VCCSW ECON 6 SO8/TSSOP8
AI10264
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CHIP ENABLE GATING
Internal gating of the chip enable signal prevents erroneous data from corrupting the external SRAM, in the event of an under-voltage condition. The chip enable signal, which normally goes directly from the microcontroller to the SRAM, is routed instead through the Supervisor device. The short propagation delay enables the chip enable gating to be used with most microcontrollers. During normal operation (when Reset is not asserted), the Chip Enable signal is transmitted through the Supervisor device unaltered. When Reset is asserted, the SRAM is placed in its low power mode and the memory is inaccessible. In this way, the SRAM contents are protected from data corruption. Chip enable gating uses a series transmission gate from E to ECON (see Figure 15.). During normal operation (with Reset not asserted), the E transmission gate is enabled, and passes all E transitions. At that time, the impedance of E appears as a resistor, typically about 40, in series with the load at ECON. When Reset is asserted, the transmission path becomes disabled. In the disabled mode, E becomes high impedance, the transmission gate is turned off, and an active pull-up connects ECON to VOUT. This pullup turns off again, when the transmission gate is enabled. Figure 15. Chip Enable Gating Block Diagram
VCC VRST Comparator ECON Output Control
trec Generator
RST VOUT
E
ECON
AI10265
Note: Connect E to VSS if unused.
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Typical Waveforms for the STM818 Supervisor After power-up, the ECON output stays High for a period of trec (see Figure 16.). After this it starts to pass the E input signal on. While Reset is asserted, the chip-enable transmission gate is disabled, E is high impedance, and an active pull-up connects ECON to VOUT (disabled mode). If the voltage at E is High during a Power-down sequence (when VCC passes the Reset threshold), the chip-enable transmission gate is disabled, and E immediately becomes high impedance. If E is Low when Reset is asserted, the chip-enable transmission gate will be disabled 15s after Reset is asserted. This permits the current write cycle to complete during power-down. Any time a Reset is generated, the chip-enable transmission gate remains disabled, and E remains high impedance (regardless of any activity on E) for the Reset time-out period. The propagation delay through the chip-enable transmission gate depends on VCC, the source impedance of the drive connected to E, and the loading on ECON. For the minimum propagation delay, minimize the capacitive load on ECON and use a low-output impedance driver. Figure 16. Typical Waveforms for the STM818 Supervisor
VCC
VRST
ECON VBAT trec VBAT 15s trec
RST
E
AI10266
Note: The chip enable gating function is also implemented on the STM795 device. Nevertheless there are two differences, in comparison to the STM818. Firstly the ECON signal is held High only for half of the tREC period, and secondly the chip-enable transmission gate is disabled only 10s after Reset is asserted if the E input is Low.
Table 9. Typical values for the STM818 Supervisor
Description E-to-ECON Resistance Reset-to-ECON High Delay (Power-down) E-to-ECON Propagation Delay ECON Short Circuit Current Typical Value 40 15 2 0.75 Unit s ns mA
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Hardware Hookup for the STM818 Supervisor Figure 17. illustrates the hookup of the STM818 Supervisor circuit connected to a microprocessor and an SRAM memory. All the functions of the STM818 are used (battery switchover, watchdog, chip enable gating, Power-On Reset, Low Voltage Detect). The Chip Enable signal is decoded by the Address Decoder and it goes to the E input of the Supervisor circuit. The ECON output is connected to the CS (Chip Select input) of the SRAM memory. Figure 17. Hardware Hookup for the STM818 Supervisor
Microprocessor VCC 1 VCC STM818 VOUT VBAT RST WDI ECON 8 7 6 5 3V Battery
2 VCC 3 VSS Address Decoder 4E C 1F
SO8/TSSOP8
A0-A15 I/O RST GND
SRAM VCC A0-Axx CS GND
AI10267
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BATTERY FRESHNESS SEAL
The battery Freshness Seal is a feature that is available on the STM817/818/819. It disconnects the backup battery from the internal circuitry and VOUT until it is needed. This allows an OEM (Original Equipment Manufacturer) to ensure that the backup battery connected to VBAT will still be fresh when the final product is put to use. To enable the Freshness Seal on the STM817 and STM819: 1. Connect a battery to VBAT 2. Ground PFO 3. Bring VCC above the Reset threshold voltage, and hold it there until Reset is deasserted, following the Reset timeout period 4. Bring VCC Low again (see Figure 18.). For the STM818, use the same procedure, but ground ECON instead of PFO. Once the battery Freshness Seal has enabled (disconnecting the backup battery from internal circuitry and anything that is connected to VOUT), it remains enabled until VCC is next brought above VRST. Figure 18. Typical Waveforms for the STM817/818/819 Supervisors
VCC
VRST
trec
RST
AI10268
Note: 1. For the STM818, ECON is held Low, externally. The ECON state is latched half way through the tREC period, and the Freshness Seal function is enabled. 2. For the STM817 and STM819, PFO is held Low, externally. The PFO state is latched half way through the tREC period, and the Freshness Seal function is enabled.
CONCLUSION
ST Microprocessor Supervisors have a large range of features adapted to the user's needs:
Centralised function for managing a system Reset. Early warning of power failure, in time to initiate any safeguard routines. Watchdog timer, monitoring for cessation of normal processor activity. Battery switchover, either to allow continued operation, or to maintain minimum functionality. Also useful for the regulation of noisy power supplies. Battery Freshness Seal, for maintaining the battery life on the production line, for the end user.
ST Microprocessor Supervisors are the ideal choice for adding protection to applications that are used in noisy environments and require power supply monitoring for proper operation.
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REFERENCES
AN1772: How to Control Power-up/Reset and Monitor the Voltage in Microprocessor Systems using ST Reset Circuits. AN1336: Power-Fail Comparator for NVRAM Supervisory Devices.
REVISION HISTORY
Table 10. Document Revision History
Date 15-Mar-2005 Version 1 First issue Revision Details
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If you have any questions or suggestions concerning the matters raised in this document, please refer to the MPG request support web page: http://www.st.com/askmemory
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