Application Notes | Industrial | Motor Control | 8-bit Microcontrollers | ST7 - 8-bit Microcontrollers

Implementation of a current regulator for BLDC motor control with ST7FMC

Application Note

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Last Updated: 20/06/2006

Pages: 19

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Low voltage motor control demonstration kit based on the ST7MC2S4 and STS8DNH3LL

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Source file for implementation of a current regulator for BLDC motor control with ST7FMC

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AN2267 Application note
Implementation of current regulator for BLDC motor control with ST7FMC
Introduction
A conventional method of controlling BLDC motors is to implement an inner current loop for torque / current control. Reference to this inner loop is provided either by an outer speed loop or by some other means based on application requirement. The linearity of inner current / torque loop is greatly affected by the faithfulness of current feedback. In the first section, an outline to various approaches for obtaining current feedback is presented and analyzed with the limitations of each. In the subsequent sections, a presentation is given of a simple, linear and cost effective approach of implementing the inner current loop by sampling the DC link current at the mid-point of PWM "on time" with ST7FMC. Experimental results are also discussed. An accompanying software file is available with this application note and can be downloaded from www.st.com/mcu

June 2006

Rev 1
www.st.com

1/19

Contents

AN2267

Contents
1 2 3 4 5 6 7 Outline to various approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Obtaining the average current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 BLDC motor control using ST7FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Implementation using ST7FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Appendix A Sampling inner current loop procedure . . . . . . . . . . . . . . . . . . . . . 14 Appendix B Event U interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Appendix C ST7MC 3-phase motor control schematics . . . . . . . . . . . . . . . . . . . 16

2/19

AN2267

Outline to various approaches

1

Outline to various approaches
A BLDC motor driven in a conventional 6-step method greatly resembles a brushed DC motor. Hence, one may choose to regulate the average DC link current. But this actually results in constant power operation for the motor because at constant DC link voltage, if the average link current is regulated at a certain value, it effectively regulates the power at that point for any variation in motor load, and the average load current / motor torque varies inversely with speed depending on the load. Any effort to compensate the average DC link current data with the duty cycle to obtain average phase current will be impaired by a filter time constant, rendering this option ineffective. Since the DC link current does not reveal winding currents during PWM "off time", one may choose to monitor all 3 winding currents and build a regulator. But this requires two current sensors to monitor any two phase currents, while the third phase current can be reconstructed from these two. However, the cost of these sensors makes this option expensive. A third option would then be to regulate the peak current per PWM period. Though it is inexpensive and easy to implement, it is not exactly linear. During PWM on time, at lower duty cycles, when both speed and BEMF are small, the phase current rises much faster than at higher duty cycles when the speed and BEMF are large. The same peak currents per PWM period represent different average currents at different duty cycles. An intuitive geometric approach will reveal this as shown in Figure 1. A typical variation in average current vs duty cycle at a given peak current reference is shown in Figure 2. Figure 1. Iphase I peak Peak current regulation at different duty cycles with BEMF load Iphase I peak

t Figure 2. Iave vs duty cycle at a given Ipeak Iave

t

Ipeak

dutycycle 0 0.5 1.0

3/19

Obtaining the average current

AN2267

2

Obtaining the average current
For linear torque control, it is important that we sample the average phase current as feedback to the current regulator. It is best to get this information from the DC link current using only a shunt resistor because of its low cost and simplicity. However, the DC link current is not continuous and is present only during PWM on time. As a simple model for current control, assume a simple buck converter feeding an RL load as shown in Figure 3. Figure 3. Buck converter feeding an RL load
PWM CONTROL

SW1 1

2

R1 BT1 D1 VL L1 Rsh

Ish

IL

The switching frequency, PWM on time and load inductance are such that the load current is continuous. Figure 4 shows the load voltage, load current and DC link current waveforms. A close look at the load current waveform reveals that its average value is equal to its instantaneous value during the middle of PWM on time or off time. Since the load current flows through the DC link during PWM on time, sampling the DC link current during the middle of PWM on time gives the average load current. Figure 4. Buck Converter - Waveforms V

IL IL(ave IS

To

Toff

4/19

AN2267

BLDC motor control using ST7FMC

3

BLDC motor control using ST7FMC
The main feature of ST7FMC is its powerful motor control macro cell, capable of generating control signals to drive a sensorless or sensored 3 phase BLDC or AC motor. STMicroelectronics application notes AN1946 [1] and AN2030 [2] explain, in detail, the procedure to control a 3 phase BLDC motor using ST7FMC. Figure 5 shows the simplified block diagram of the hardware motor control macro cell. The macrocell has multiple timers performing various functions in parallel to generate control pulses for the motor. An auto scalable 8-bit timer (MTIM) monitors the time difference between successive phase back EMF zero crossings (Z events) of the motor. When a Z event occurs, the timer value is captured into MZREG and the timer restarts counting from zero, and, the previous content of MZREG is transferred to MZPRV. This timer is a part of what is called DELAY MANAGER that, based on this time difference and a delay coefficient (MWGHT), identifies the timing for next phase commutation instant (C events). All in parallel, a 12-bit free running counter generates the PWM carrier for inverter switching. Figure 5. Simplified block diagram of Motor control Macro cell for BLDC motors
DELAY or SPEED MEASURE UNIT (not
WEIGH CAPTURE MTI TIM E BEMF ZERO-CROSSING BEMF= [Z In DELAY = WEIGHT x Ex MCI MCI MCI MCVRE

=
COMMUTE

TACH Encoder

Vre

INPUT DETECTION

MEASUREMENT WINDOW GENERATOR (I

CURRENT VOLTAGE (V

P H A S

MCO MCO MCO MCO MCO MCO U, V, Phase CFAV OAON + NMCE MCAO MCAO MCAOZ/ MCCFI Vdd AD

MOD

PWM

Phase

MCCRE

(V (I R

CHANNEL
12-bit Phase Phase V Phase W [Z] : Back EMF Zero-crossing Z n : Time elapsed between two consecutive Z [C] : Commutation C n : Time delayed after Z event to generate C (I): Current (V): Voltage

C

(V

PCN

12-bit THREE-PHASE PWM GENERATOR
MCPWM MCPWM MCPWM

3

5/19

BLDC motor control using ST7FMC Figure 6. Motor Control Macro cell - BLDC motor control configuration

AN2267

Board + Mot r o Mi croc ntroll er o E F [2 : 0] F i lte r / D ZH
o r or o r

P Z V D b i t C Bn bit P Z b i t

R O bt E i

D ,H S C ,H S 2

IS nbit

MC A I MC B I

E F [2 :0 ] F il t e r / C S R bit
or

Q 1

D CP 2

+ CS,HVR F E D ,H S VR2 0 MPWME R g e

MC C I MC R F VE

DH X T1 b t 6i Fc u p R+ H D M n bit C Bn bit P

S PLG 1

1/ 4

V

I

MC W U PM 1 /2 1 /20 C mpa e U o r 12- bi t P W M ge nera tor MC W V PM MC W W PM SR bit
n

+ 1

MTM I
= F h? F 4

bits

MREF Rg e

ST3- 0 bits

OS

1/ 2

R tio a

1

1/ 128

1

MZR G E <5 h 5? Rc k

H V

SA3- 0 & OT1-0 bits cr l

3 Ch 0

SWA bit Z MC 0 O De d a Time MC 2 O MC 4 O B 1 0 Ch 1 I V CH

MTI M [ 8 bit U Coun er] p t 8 ZH MZR G R g [Zn E e ] ZS,H MZP R R g [ Zn ] Ve 1 Com are p SZn bt i EF [2:0] Filt e / C r

x6
Hig Fr que c y Chop er he n p

x6

Ch 2 Ch 3

D H MD EG R g [D ] R e
n

MP H T Reg S

SQ R

De d a Time

n

A MCO1 MCO3 MCO5 C

Ch4
n

C mpar o e

DC bit B MW HT Reg [a G 8 ]

n- n 1

SDM bit Ch 5 EF[2:0] F ilter / C DS,H D 6
S

n1 +

8

8 DTG regs ter i 2 M POL R g e PCN bit =0 6 A O bit 6 1 MOE bit

A x B/ 256 ZS SWA bit 8

MPA R R g e

De d a Time

N CS ME MCPWMU/V/ W MCAOP MCAON MCAOZ

CL MI MR R g e MISR Reg Co p r e ma CSH ,
R/+

C F[ 2 0] bit F :

MCOMP R g [Cn 1 e +]

+ -

E ZS,H D
S,H

VD D

C L

+ C A V bit F

M C FI C MC R F CE

A
() V
Cext

(I) Re t 1x

Filt e / PWM r C ,H S

Re t 2x

A PWM output is generated as a result of comparison between this carrier and a compare register (MCPUH:MCPUL) that carries pulse width (duty cycle) information. This PWM signal is directed to one of the six inverter switches by a CHANNEL MANAGER that acts as a traffic diverter on the PWM output. The channel manager also selects a complementary switch, as programmed by the user, which together with the switch receiving PWM will force current into the motor windings. Based on the motor terminal voltages or Hall sensor outputs, an analog block identifies the motor phase BEMF Z events and captures the contents of MTIM timer into MZREG and the previous value of MZREG into MZPRV and this cycle repeats all over again.

6/19

AN2267

Implementation using ST7FMC

4

Implementation using ST7FMC
A typical schematic block diagram of ST7FMC based sensorless control of BLDC motor [2] is shown in Figure 7. Refer to Appendix C on page 16 for a complete schematic of the experimental hardware. This schematic resembles the motor control starter kit schematic from Softec Microsystems, with matching I/O assignments wherever possible. Figure 7. Schematic block diagram of ST7FMC based sensorless control of BLDC motor Vdclink
MCO0 MCO1 MCO2 MCO3 MCO4 MCO5 Shut Down

VCC

Speed Ref
AINy

BLDC

ST7FMC VC C

AINx PE0 PE1 PE2

Max Current Limit

MCIA MCIB MCIC

Figure 8a shows the PWM carrier configured in center aligned mode, where the counter counts up to a maximum value (as defined by MCP0) and starts counting down to zero and repeats this cycle again. (See Appendix A for information on setting the PWM frequency). The PWM generator is set to generate a duty cycle update interrupt (U event) upon completion of every N carrier cycles as specified by MREP register. (See Appendix A for information on setting the periodicity of this interrupt). The timing of the U event or interrupt is positioned as shown in Figure 8a. The carrier is compared with MCPU and PWM pulses are generated as shown in Figure 8b. Due to the application of PWM voltage on motor windings, a current flows in its windings as shown in Figure 8c.

7/19

Implementation using ST7FMC Figure 8. PWM on time midpoint identification and control U event MCP0 Fig 8a Carr ier Ref

AN2267

U event

t Fig 8b PWM t Fig 8c Current t Fig 8d U ISR t T From Figure 8a and Figure 8b, it is clear that the U event takes place at the center of PWM on time. Based on the previous discussions, this is the right instant to read the instantaneous DC link current in order to get the average phase current value. Hence the interrupt associated with U event should be set to the highest priority and the very first instruction in this Interrupt Service Routine (ISR) should read the DC link current value. In any case, there is an interrupt latency time of approximately 3-4s, which is also the typical conversion time of on-chip Analog to Digital Converter (ADC). If the current feedback analog input channel was previously selected and set for sampling continuously, then, when the first instruction in U event interrupt subroutine reads the ADC data register, it will aptly hold the DC link current value fairly close to that during the middle of PWM on time.

8/19

AN2267 Figure 9.

Implementation using ST7FMC Update (U) event interrupt subroutine flow chart Star t U

Read current feedback Set U ISR priority lower if required Read other Analog inputs Current loop PI regulator Dutycycle update Set ADC Channel back to Sample current feedback Restore ISR priority to the highest

End U The flowchart in Figure 9 shows the actions within the U event interrupt service routine. To coordinate the reading of any other analog inputs to the ADC, it is recommended that they are all read within this U event subroutine after the DC link current read. However, before returning from the interrupt, it is important to restore the ADC to sample the DC link current channel again so that on re-entry in the next U event, the DC link current value can be read from ADC right away. If required, interrupt priority of this routine can be lowered after reading the current value upon entry, but should be restored to the highest value before returning for obvious reasons. Refer to the accompanying file for a complete listing of the code and experimental workspace.

9/19

Results

AN2267

5

Results
Experimental implementation of this scheme yielded satisfactory results. A closed loop regulator for BLDC motor control with inner current and outer speed loops as shown in Figure 10 was implemented. Current loop sampling time of 500s and speed loop sampling time of 2ms was chosen. The amount of computing time required within a 2ms time window to execute through a full cycle of control loop and all motor control ISRs at an electrical frequency of 200Hz is less than 1ms. The important waveforms obtained are shown in figures 11 and 12. Figure 11 shows the convergence of reference and actual phase current values at the instant of occurrence of U event which is the feedback sampling instant. Notice that the U event occurs during the middle of PWM ON time. Figure 12 shows the tight control of motor average phase current for a given current reference. Figure 10. Closed loop current and speed control - block diagram
ST7FMC controller PI reg PI reg I*
Vdclink
d ut y

+ -

+ -

BLDC

Speed estimator

10/19

AN2267

Results Figure 11. DC link current sampling at U event and closed loop convergence

Figure 12. Tight control of average phase current vs reference

11/19

Conclusion

AN2267

6

Conclusion
The experiments performed based on the described method gave fairly linear current control. One limitation of this sampling method is when the motor current becomes discontinuous, in which case the actual average current is less than the instantaneous value at the mid point of PWM on time, and correcting this error is quite cumbersome.

12/19

AN2267

References

7

References
[1]. STMicroelectronics AN1946 - Sensorless BLDC motor control and BEMF sampling methods with ST7MC [2]. STMicroelectronics AN2030 - Back EMF detection during PWM on time by ST7MC

13/19

Sampling inner current loop procedure

AN2267

Appendix A

Sampling inner current loop procedure

Procedure to set carrier frequency (Fpwm) and periodicity of U event (TU) for sampling inner current loop: Chosen Fpwm = 16KHz where, Fpwm = Fmtc / (Prescaler . 2 . MCP0)

U MCP0

U MREP

Repeat Counter

U

Fmtc

Prescaler

Up/ Down counter

MPCR
CMS = 1

MPCR
PCP[2:0]

Fpwm

Given Fmtc = 16MHz, and choosing Prescaler = 1, then, MCP0 = 500

Choosing TU = 500S where, TU = Tpwm . (MREP + 1) / 2 Substituting for TU and Tpwm, MREP = 15

14/19

AN2267

Event U interrupt service routine

Appendix B

Event U interrupt service routine

/* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** Motor control - Event U interrupt service routine * * ** * ** * ** * ** * ** * ** * ** * ** * ** * **/ @interrupt @nosvf void mtcU_CL_SO_ISR(void) { if (bitTest_TRUE(MISR, PUI) ) // check for U event presence { /* === Current loop PI Controller begins here === */ currentFb = (ADCDRMSB << 2) + ADCDRLSB; // get new value of currentFb piconCur(); // call current loop PI regulator to get new dutycycle MCPUL = PIconCur.byte.b2; // update MCPUH :MCPUL with new dutycycle MCPUH = PIconCur.byte.b3; /* === Current Loop PI controller ends here === */ // Read potentiometer to get latest speed reference getADC_10bit (speedRef , SPEED_REF_CHNL); if (speedRef > SPEED_REF_MAX) speedRef = SPEED_REF_MAX; // Current Feedback measurement setup for next cycle ADCCSR = ADON + CURRENT_FDBK_CHNL; ADCDRMSB; // to clear EOC of prev conv MISR = 0xff - PUI; //reset IT flag } return; }

15/19

SIG21 SIG20

D

1

2
Idc

R73 10K

1 61 50 49 38 Vpp/ PD5/AIN15 / ICCDATA PD4 / EXTCLK_A / AIN14 / ICCCLK RESET
C32 22pF R51 51K SW DIP-2

2

2

0.1uF 10K

C36

1

1

2

5K

5K 5K

5K

RV1

RV2 RV2

RV3

1

4

2

3

1

1

1

1

4

1

3

Vss_0 Vss_1 Vss_2 Vss_A
C34 680pF R58 1K5

2

2

2

2

2

PWM3 / PA0 PWM2 / (HS) PA1 PWM1 / PA2

PF2 / MCO / AIN10 PF3 (HS) / BEEP PF4 (HS) PF5 (HS)

PD0 / OCMP2_A / AIN11 PD1(HS) / OCMP1_A PD2 / ICAP2_A / AIN12 PD3 / ICAP1_A / AIN13

PE4 / EXTCLK_B PE3 / ICAP1_B PE2 / ICAP2_B PE1 / OCMP1_B PE0(HS) / OCMP2_B

9 10 11

41 42 43 44

45 46 47 48

SW1 SW2 SW3 SW4 SIG1 SIG2 SIG3 SIG4

2

2

1

2

SW8 1

SW10 SW10 1

SW9 1

+5V

+5V P7

10K R79

OVER_cur OVER_volt

P9

1
0.1uF C46

2

A

RV2 SIG18 OVER_temp RV1

0.01uF

0.01uF

0.01uF

0.01uF

SIG12 SIG13 PE2 PE1 PE0

PB3

C45

C49

C48

2

C50

59 58 57 56 55

16/19
4 3 2 1

Appendix C

5

ICC Interface R54 10K R64 10K

D

J3 CON10A

2
U2 J1

R72 10K

1 1 2

R50 10K

+5V

1 3 5 7 9

2 4 6 8 10

+5V R52 Y1 16.00MHz Ceramic resonator

1 PF1 / MCZEM / AIN9 PF0 / MCDEM / AIN8 MCVREF / PB0
5K +5V

5 6 OSC1 OSC2 40 39 17
SW6

OAP / PC2 OAN / PC3 AIN6 / MCCFI1 / OAZ MCCREF / PC4 MCPWMV / PC6

27 28 29 30 32

2 R68 470K 1
RV4 C28 0.1uF TP1

PB2

+5V Vdclink 10K C38 0.1uF R80 P8

SW1 SW2 SW3 SW4

25 15 13 60 (HS) PC0 ARTIC2 / PA6 ARTCLK / (HS)PA4 PE5 / 1 2
0.1uF +5V U4 D33 30V NEC2501 D32 U3 1K5 D28 R57 P5 C47

AIN5 / MCCFI0 / PC1 MCIC / PB3 MCIB / PB2 MCIA / PB1

26 20 19 18

Vref Idc1 Vc Vb Va

Figure 13. Schematic 1 of 3

C

R75 100E Temprtr SIG17

C

ST7MC 3-phase motor control schematics

RV1 RV2 RV3

0.1uF

+5V

12 14 16 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5 AIN2 / PA7 MCES PC7 / MCPWMW / AIN7 MCPWMU / PC5 52 51
+5V R59 2K2 200E R69

(HS)MCO5 (HS)MCO4 (HS)MCO3 (HS)MCO2 (HS)MCO1 (HS)MCO0 4
SHUTDOWN RV3 SIG19

3 2 1 64 63 62
CL CH BL BH AL AH

C41 GREEN D27 SIG5 SIG6 SIG7

0.1uF

0.1uF

0.1uF

C42

C43

C44

R60 470E

21 22 23 24 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 / SS/(HS)PB7 33 31 VAREF Vdd_2 Vdd_1 Vdd_0 PD7(HS) / TDO PD6(HS) / RDI
+5V

R61 680E D26 RED

+5V

34 54 8 37

R74 20K NEC2501 st72mc_qfp64 R62 8K2

R82 20K

R81 20K

R83 20K

B

36 7 53 35
R63 8K2

D29

1 6 2 7 3 8 4 9 5
DB9

B

+5V

SIG21 PE1 SIG13

A

CD3 0.1uF

CD1 0.1uF

CD2 0.1uF

CD4 0.1uF

Title ST7MC control of 3 phase motor Size B Date: Document Number Tuesday, January 03, 2006
3 2

SIG18 SIG7 SIG5 SIG2 SIG17 HEADER34
4

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
SIG20 PE0 PE2 SIG12 SIG4 SIG19 SIG6 SIG1 SIG3

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

Rev 3.0 Sheet
1

3

of

3

ST7MC 3-phase motor control schematics

5

AN2267

AN2267

5

4

3

2

1

AC POWER IN
STTA106U +15V Vdc D22 1N4148WS D7 IR8GBU06 F1 FUSE +4

MAIN RECTIFIER
D23

15v REGULATED SUPPLY

P2

L1

2 4 8 7 6 5

SW NEU C20

1 3
W1 C29
0.23V SET RES

D

680uF/200V C1 2 0.1uF/400V 22uF/25V 100uF/25V 100uF/25V R1 100K/2W
VDD DRAIN

IC4 VIPER12AS D25 18V +15V

D

Figure 14.

HEADER 2 0.1uF/400V 15V

C26 D24 22uF/25V

1-

3
FB SOURCE

0.1uF/400V

3 1 POWER_JUMPER
C9

C2 R19 100K/2W C30 22nF L1 1mH C31 +5V R20

+

N

GND

LINE FILTER
680uF/200V D20 STTA106U

1 2

C13 D21 U1 L7805 5V 1 Vi Vo

3
C27 10uF/25V

Idc

0.015E/2W 1%

+15V IC1 AL R25 1K L6386 Tantalum C10 D1 0.47uF/50V 1N4148WS T1 R7 47E C3 0.01uF 1N4148WS T2 R9 47E C4 0.01uF

D8 STTA106U

Vdc

Schematic 2 of 3

C

1 LIN SD HIN VCC DIAG CIN GND GND 8
R10 22E

VBOOT HVG OUT NC NC LVG 9 10 11 12
R8 22E D2

14 13

2

C

R45 27K +15V

AH

R26 1K

3 4 5 6

OVER_volt Vprot R30 1K C15 0.1uF

STGP7NB60HD

R27 1K

D11 1N4148WS

STGP7NB60HD

+5V

2

OVER_cur

7

+15V 1uF/25V 1uF/25V 1uF/25V CP1 CP2 Vdc CP3

P3

1 2
T3

Idc1 +15V IC2 +5V BL 1K R28 L6386 Tantalum C11 D3 0.47uF/50V D9 STTA106U

1N4148WS R11 47E

1 LIN SD HIN VCC DIAG CIN GND GND LVG 9 8
R14 22E

VBOOT HVG OUT NC NC 10 11 12 13

14

C33 0.1uF

68
R46 51K R39 10K R37 8K2 D12 1N4148WS +15V

1
Q1 2N4403 BH

2 4 5 6 1
C17 0.1uF R38 1K PB1 +5V

R29 1K

3

5+ 1 7

7

C5 R12 0.01uF 22E D4 1N4148WS R13 47E C6 0.01uF

T4

IC5B TS272

2-

STGP7NB60HD

B

C25 0.01uF J2

+5V

2

B

VA_OUT VB_OUT VC_OUT P1

R40 1K5

3+ 4 2
IC5A TS272 R48 2K R49 1K C14 1nF CL +5V CH R32 1K +15V D13 1N4148WS 1nF 1nF R31 1K C16 C18 +15V IC3 L6386

STGP7NB60HD

1 2
D10 STTA106U Vdc Tantalum C12 D5 0.47uF/50V 1N4148WS T5

3

SHUTDOWN

1 2 3 4 5 6 7

LIN SD HIN VCC DIAG CIN GND

VBOOT HVG OUT NC NC LVG GND

14 13 12 11 10 9 8
R18 22E

OVER_temp R47 27K R33 1K C19 1K R34 0.1uF +5V R2 NTC 10K

A

Temprtr

STGP7NB60HD R15 47E

C7 R16 0.01uF 22E D6 1N4148WS R17 47E C8 0.01uF

T6

A

STGP7NB60HD

Title ST7MC control of 3 phase motor Size B Date: Document Number Tuesday, January 03, 2006
3 2

Rev 3.0 Sheet
1

2

of

3

5

4

ST7MC 3-phase motor control schematics

17/19

Figure 15. Schematic 3 of 3

ST7MC 3-phase motor control schematics

C

0.01uF

A

D30

1N4148WS

D31 1N4148WS

18/19
4 3 2 1

5

VA_OUT VB_OUT VC_OUT R23 1K +5V R3 180K/2W R22 100K/2W R53 4K7 P4 +5V R41 1K D18 1N4148WS C35 D19 1N4148WS HEADER 5
C D

D

R24 1K R4 180K/2W R55 4K7 R56 4K7 R5 180K/2W

R6 1K

R42 1K D16 1N4148WS D17 1N4148WS SW3 SW DIP-3 SW4 SW DIP-3 +5V

R43 1K

R44 1K

D15 1N4148WS

D14 1N4148WS

5 4 3 2 1

SW2 SW DIP-4

SW1 Vc Vb Va Vref SW DIP-4

SW5 SW DIP-4

B

C24 0.1uF R65 47K R70 47K R71 47K

C23 0.1uF

C22 0.1uF

C21 0.1uF

B

+5V +5V R66 10K R78 10K RV5 5K Vdc Q2 2N2222 C40 0.1uF R76 100E C39 2.2nF R77 0(NC) +5V PE2 PE1 SW7 SW DIP-2

PE0

P6

R67 10K

2

1

R21 330K/2W

R36 39K

R35 470E

** SW3 and SW5 are fully CLOSED
Title ST7MC control of 3 phase motor Vdclink Vprot Size B Date:
3 2

A

C37 0.1uF

Document Number Tuesday, January 03, 2006 Sheet
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