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STR75x hardware development getting started

Application Note

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Last Updated: 10/07/2007

Pages: 22

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ARM7TDMI-S™ 32-Bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN

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AN2419 Application note
STR75x hardware development getting started
Introduction
This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the STR75x product family and describes the minimum hardware resources required to develop an STR75x application. Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes.

July 2007

Rev 2

1/22
www.st.com

Contents

AN2419

Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 1.2.2 1.2.3 1.2.4 Power scheme 1: single external 3.3V power source . . . . . . . . . . . . . . . 4 Power scheme 2: dual external 3.3V and 1.8V power sources . . . . . . . . 5 Power scheme 3: single external 5V power source . . . . . . . . . . . . . . . . . 6 Power scheme 4: dual external 5.0V and 1.8V power sources . . . . . . . . 7

1.3

Reset and power startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 1.3.2 Power startup specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Main 4MHz or 8MHz oscillator (OSC4M) . . . . . . . . . . . . . . . . . . . . . . . . . 10 Low power 32.768 kHz oscillator (OSC32K) . . . . . . . . . . . . . . . . . . . . . . 11 USB clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PLL, FREEOSC, and AHB/APB prescalers . . . . . . . . . . . . . . . . . . . . . . . 12 Clock-out capability: MCO (Main Clock Output) . . . . . . . . . . . . . . . . . . . . 13 Clock detector (CKD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3

Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 3.2 Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 External memory (SMI) boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4

Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 4.2 ICE debug tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 JTAG / ICE connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5

Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 5.1.2 5.1.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/22

AN2419

Contents

5.2

JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 7

Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3/22

Power supplies

AN2419

1
1.1

Power supplies
Introduction
The device has five power pins:

VDD_IO: power supply for I/Os (3.3V 0.3V or 5V 0.5V). Must be kept on, even in STANDBY mode. V18 (pins V18REG and V18 which are internally shorted): Power Supply for Digital, SRAM and Flash: 1.8V 0.15V. V18_BKP: Backup Power Supply for STANDBY or STOP Mode

Two embedded regulators are available to supply the internal 1.8V digital power: V18 and V18_BKP are normally generated internally by these regulators. The Main Voltage Regulator (MVREG) supplies V18 and V18_BKP. It delivers a power supply of 1.8V 0.15V. The Low Power Voltage Regulator (LPVREG) can supply V18_BKP or V18 in STOP or STANDBY mode. It delivers a power supply of around 1.4V. Two sensitive analog blocks have dedicated power pins:

VDDA_PLL: Analog Power supply for PLL (must have the same voltage level as VDD_IO) VDDA_ADC: Analog Power supply for ADC (must have the same voltage level as VDD_IO)

1.2

Power supply schemes
The device can be connected in any of the following configurations depending on your application requirements:

Power Scheme 1: Single external 3.3V power source Power Scheme 2: Dual external 3.3V and 1.8V power sources Power Scheme 3: Single external 5.0V power source Power Scheme 4: Dual external 5.0V and 1.8V power sources

1.2.1

Power scheme 1: single external 3.3V power source
In this configuration, the internal voltage regulators are switched on by forcing the VREG_DIS pin to low level.

The V18REG pin must be connected to external stabilization capacitors (min. 10 uF Tantalum, low series resistance). The V18 pin must be connected to external stabilization capacitors (33nF ceramic). The V18_BKP pin must be connected to an external stabilization capacitor of 1F. A decoupling capacitor of 1F must be added on the VDD_IO pin which is closest to the V18REG pin.

4/22

AN2419 Figure 1.

Power supplies
Power supply scheme 1 (single 3.3V supply, VREGDIS=0) in NORMAL mode

STR750
V18_BKP 1F VSS_BKP VREG_DIS V18 33nF VSS18 V18REG 10F VSS18 VSS_IO VSS_ADC +3.3V VDD_IO 1F VSS_PLL VDD_ADC +3.3V VDD_PLL +3.3V

1.2.2

Power scheme 2: dual external 3.3V and 1.8V power sources
In this configuration, the internal voltage regulators are switched off by forcing the VREG_DIS pin to high level. This scheme has the advantage of saving power consumption when the 1.8V power supply is already available in the application. V18 and V18_BKP are provided externally through the V18REG, V18 and V18_BKP power pins.

The external 3.3V power supply must always be kept on. VREG_DIS pin is tied to high level which disables the Main Voltage Regulator and the Low Power Voltage Regulator. All digital power pins (V18REG, V18 and V18_BKP) must be externally shorted to the same 1.8V power supply source. In this scheme, STANDBY Mode is not available.

Caution:

When powered by 5.0V, the USB peripheral cannot operate.

5/22

Power supplies Figure 2.
Power supply scheme 2 (3.3V and 1.8V supplies, VREGDIS=1)

AN2419

STR750
+1.8V V18_BKP VSS_BKP +3.3V VREG_DIS +1.8V V18 VSS18 +1.8V V18REG VSS18 VDD_IO VSS_IO VSS_ADC +3.3V VDD_PLL VSS_PLL VDD_ADC +3.3V +3.3V

NOTE : THE EXTERNAL 3.3V POWER SUPPLY MUST ALWAYS BE KEPT ON

1.2.3

Power scheme 3: single external 5V power source
In this configuration, the internal voltage regulators are switched on by forcing the VREG_DIS pin to low level.

The V18REG pin must be connected to external stabilization capacitors (min. 10 uF Tantalum, low series resistance). The V18 pin must be connected to external stabilization capacitors (33nF ceramic). The V18_BKP pin must be connected to an external stabilization capacitor of 1F. A decoupling capacitor of 1F must be added on the VDD_IO pin which is closest to the V18REG pin.

Caution:

When powered by 5.0V, the USB peripheral cannot operate. Figure 3. Power supply scheme 3(single 5V supply, VREGDIS=0) in NORMAL mode

STR750
V18_BKP 1F VSS_BKP VREG_DIS V18 33nF VSS18 V18REG 10F VSS18 VSS_IO VSS_ADC +5V VDD_IO 1F VSS_PLL VDD_ADC +5V VDD_PLL +5V

6/22

AN2419

Power supplies

1.2.4

Power scheme 4: dual external 5.0V and 1.8V power sources
In this configuration, the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high level. This scheme has the advantage of saving power consumption when the 1.8V power supply is already available in the application and providing 5V I/O capability. V18 and V18_BKP are provided externally through the V18REG, V18 and V18_BKP power pins.

VREG_DIS pin is tied to high level which disables the Main Voltage Regulator and the Low Power Voltage Regulator. All digital power pins (V18REG, V18 and V18_BKP) must be externally shorted to the same 1.8V power supply source. STANDBY Mode is not available USB functionality is not available Power supply scheme 4 (5.0V and 1.8V supplies, VREGDIS=1) STR750
+1.8V V18_BKP VSS_BKP +5.0V VREG_DIS +1.8V V18 VSS18 +1.8V V18REG VSS18 VDD_IO VSS_IO VSS_ADC +5.0V VDD_PLL VSS_PLL VDD_ADC +5.0V +5.0V

In this scheme:

Figure 4.

NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON

1.3
1.3.1

Reset and power startup
Power startup specifications
To ensure the MCU starts-up cleanly, the rise time of the VDD_IO power supply must be comprised between 20s/V and 20ms/V. In addition, you must provide an external RESET for at least 20s after the VDD_IO power supply has reached its minimum working value (3.0V). It is recommended to use an external Power-On-Reset circuit monitoring VDD_IO to assert the RESET at power-up . During VDD_IO power-up (from 0V to 3.3V or 5.0V), all I/Os are guaranteed to be in HiZ state, assuming external RESET is asserted. If you are using an external 1.8V power supply, the rise time of power supply V18 must be comprised between 20s/V and 20ms/V.

7/22

Power supplies

AN2419

1.3.2

External reset
The NRSTIN pin acts as an asynchronous RESET active low. The NRSTIN pad input is a Schmitt Trigger input pin. A filter is added to ignore all incoming pulses with short duration:

All negative spikes with a duration less than 150ns are filtered. All trains of negative spikes with a ratio of 1/2 are filtered. This means that all spikes with a maximum duration of 150ns with minimum interval between spikes of 75ns are filtered. An internal pull up is connected on each of the pins NRSTIN and NRSTOUT.

An external reset circuit can be connected (STM1818) to manage the reset signal: both for power-on reset during startup and management of the reset button (debounce functionality and pulse duration control). Figure 5. Reset circuit STR750
V DD_IO

VDD

EXTERNAL RESET

RPU
RST NRSTIN

VCC VSS
STM1818 STM1813* * use STM1818TWX7F if VDD=3.3V use STM1813LWX7F if VDD=5.0V

VDD_IO

R PU

NRSTOUT

The NRSTOUT pin is an exact image of the system Reset signal (active low) provided to the device which is used to generate the reset of the AHB System and the reset of each APB peripherals. Internal circuitry guarantees a minimum reset pulse duration of 20s. Some peripheral registers, like the RTC or the BACKUP registers are not reset by a System Reset but only by an RSM Reset: this means that these registers are only reset at VDD power up. For more details see the Reference manual UM0191.

8/22

AN2419

Clocks

2
2.1

Clocks
Clock overview
Figure 6. Clock overview
PLL FREEOSC
4MHz 1-10 MHz UP TO 64 MHz

PLL

48 MHz CKD FLAG

XT1 XT2
OSC4M
CK_SYS

AHB & APB DIVIDERS

HCLK UP TO 64MHz PCLK UP TO 32MHz CK_TIM UP TO 64MHz

CLOCK DETECTOR /128
XRTC1 XRTC2
32kHz

CKD FLAG

CK_USB 48 MHz

OSC32K

RTC

ALARM WAKEUP

LPOSC

300kHz

USB_CK
For further details see the Reference manual UM0191.

Several on-chip oscillators can feed the MCU system clock (CK_SYS) from which the HCLK and PCLK derive:

FREEOSC: Internal Free Running Oscillator providing a clock between 1 and 10MHz, also used as emergency clock. It consists of the internal VCO of the PLL configured in free running mode OSC4M: 4MHz or 8MHz Main Oscillator (Crystal or Ceramic oscillator or external clock) a 4 MHz Crystal/Ceramic oscillator connected to XT1/XT2 or an 8 MHz Crystal/Ceramic oscillator to XT1/XT2 followed by a divider by 2 or external clock connected to XT1

OSC32K: 32.768kHz Oscillator (Crystal or Ceramic oscillator) which can drive either the system clock and/or the RTC. LPOSC: Internal Low Power RC Oscillator providing a clock around 300kHz which can drive either the system clock and/or the RTC.

Several configurable dividers provide a high degree of flexibility to the application in the choice of the APB or AHB frequency, while keeping a fixed frequency value for the USB clock (48 MHz).

9/22

Clocks

AN2419 The Clock Detector (CKD) protects the Microcontroller against OSC4M or external clock failures. The RTC provides calender, alarm and wake-up functions and can be clocked by any of the oscillators other than FREEOSC.

Caution:

The FREEOSC and PLL are reset during the whole assertion of System RESET. After reset release, the PLL is disabled and FREEOSC supplies the system clock (1-10 MHz).

2.2

Main 4MHz or 8MHz oscillator (OSC4M)
XT1 and XT2 pins are used to connect the Main Oscillator source, which can be a resonator (crystal or ceramic) or an external source. Both sources can be used as the input clock to PLL frequency multiplier (PLL). Crystal or ceramic resonator This 4 MHz oscillator (OSC4M) has the advantage of producing a very accurate rate on the main clock. This oscillator can be directly connected to

a 4 MHz Oscillator or an 8 MHz Oscillator followed by an internal divider by 2.

If an 8 MHz Crystal or Ceramic is connected, You must select the divider by 2 The associated hardware configuration are shown in Figure 7. Refer to the electrical characteristics section of the datasheet for more details. Figure 7. Clock sources
Hardware Configuration

STR7
External Clock

X T1

XT2 (HiZ)

EXTERNAL SOURCE

Crystal/Ceramic Resonators

STR7 XT 1 X T2

C L1

LOAD CAPACITORS

C L2

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

10/22

AN2419 External Source (Bypass Mode)

Clocks

In this mode, an external clock source must be provided. The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the XT1 pin while the XT2 pin should be left hi-Z.

2.3

Low power 32.768 kHz oscillator (OSC32K)
XRTC1 and XRTC2 pins are used to connect the 32k Oscillator source, which can be a resonator (crystal or ceramic).The OSC32k clock can be used as a low power system clock Figure 8. Clock sources
Hardware Configuration Crystal/Ceramic Resonators

STR7 XRT C 1 X RT C2

C L1

LOAD CAPACITORS

C L2

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

2.4

USB clock
STR75x series microcontrollers contain a USB 2.0 Full Speed device module interface that operates at a precise frequency of 48 MHz. This clock is usually generated by the internal PLL using one single external oscillator for both the system and USB module to save board space and cost. However, if the chosen system clock is not compatible with the 48 MHz clock generation (frequency below 48 MHz), the USB clock can also provided by an external oscillator connected to the USB clock pin USBCLK. The following diagram shows the basic implementation of the USB external clock. Figure 9. USB clock oscillator
3V3
OSCILLATOR

48MHz

STR75x

OSC_OUT

USB_CK VSS

11/22

Clocks

AN2419

2.5

PLL, FREEOSC, and AHB/APB prescalers
Figure 10. PLL, FREEOSC & AHB/APB prescaler scheme
OSC4M CKOSCSEL CK_RTC 1 CK_OSC4M 0 PLLEN NCKDF CKSEL FREEOSC 1-10MHz 1 4MHz CK_PLL1 UP TO 64MHz 0 4MHz CK_OSC4M UP TO 64MHz PLL 48MHz CK_PLL2 48MHz LOCK PLLEN MX[1:0] RANGE APB PRESC /1,2,4 or 8 /2 1 0 PCLK UP TO 32MHz CK_TIM UP TO 64MHz USB_CK 48MHz PPRESC[1:0] PPRESC[2] 0 1 CK_SYS HPRESC[1:0] AHB PRESC /1,2,4 or 8 HCLK UP TO 64MHz

The CPU can execute:

the SRAM up to 64 MHz at zero wait state. the Flash up to 60 MHz speed in burst mode (zero wait state for consecutive accesses, 1 wait state for any non-consecutive access) the Flash up to 32 MHz at zero wait state

The PLL provides a Frequency Multiplier starting from a single input clock (OSC4M source) and providing the 2 following independent output clocks:

CK_PLL1 output with 4 programmable multiplication factors (up to 64 MHz) used for generating CK_SYS CK_PLL2 output with fixed 48 MHz frequency when input clock is 4 MHz used for generating CK_USB

FREEOSC provides a Free Running Oscillator for the system clock: this clock is selected when:

The PLL is disabled: FREEOSC acts as an oscillator source The clock failure flag is active: FREEOSC acts as an emergency clock source. Software cannot switch CK_SYS to CK_PLL1 (multiplied clock output) until the PLL is locked. CK_USB is gated until the software enables the PLL2EN bit in the MRCC_CLKCTL register.

For security, hardware prevents the software from making certain unrecoverable errors:

12/22

AN2419

Clocks The AHB and APB prescalers allow you to choose the AHB and APB frequencies from a wide range of possibilities:

HCLK (AHB Clock) can be generated from CK_SYS divided by 1, 2, 4 or 8 PCLK (APB Clock) can be generated from HCLK divided by 1, 2, 4, 8 or 16

The clock provided to the Timers (CK_TIM) can have twice or the same frequency as PCLK. This allows the timers to count at high frequency (up to 64MHz) Table 1 gives some typical clock configurations: Table 1.
fOSC4M (MHz)

Typical prescaler uses
fCK_SYS HPRESC [1:0] Factor (MHz) PLL x16 x15 64 60 56 48 64 00 00 00 00 01 fHCLK (MHz) 64 01 60 56 48 32 00 00 00 00 32 60 1 x14 x12 x16 56 48 32 28 24 16 16 30 48 PPRESC [1:0] 00 fCK_TIM (MHz) 64 PPRESC2 fPCLK fCK_USB (MHz) 32 (MHz)

4

The software must respect the configuration constraints of the PLL.

2.6

Clock-out capability: MCO (Main Clock Output)
The Main Clock Output (MCO) capability allows you to output a clock on the external MCO pin. The configuration registers of corresponding GPIO port must programmed in alternate function mode. You can select one of 4 clock signals as MCO clock.

CK_PLL2 HCLK PCLK CK_OSC4M

The selection is controlled by the MCOS[1:0] bits of CLKCTL register. A dedicated prescaler (divide by 1 or 2, selected by MCOP bit) can be applied to this clock before outputting it to the MCO pin. Care must be taken when switching MCO clock selection, the alternate function should be disabled to avoid any glitches on the MCO pin.

2.7

Clock detector (CKD)
A CKD (Clock Detector) is implemented to:

detect if no clock is present on OSC4M (broken or disconnected resonator) and prevent the software from selecting it. automatically feeds the MCU with the FREEOSC used as emergency clock if no clock is detected. generate an interrupt if enabled, allowing the MCU to perform some rescue operations

For more detail see the Reference Manual (UM0191).

13/22

Boot configuration

AN2419

3

Boot configuration
In the STR750, 4 different boot modes can be selected by means of the BOOT[1:0] pins as shown in Table 2. Table 2. Boot modes
Boot Mode Aliasing Embedded FLASH sector B0F0 mapped at 0h Note

BOOT Mode Selection Pins BOOT1 BOOT0 0 1 0 1 0 0 1 1

Embedded Flash Embedded SRAM SystemMemory External SMI Serial Flash memory

All FLASH sectors accessible except Embedded SRAM mapped SystemMemory sector at 0h SystemMemor y mapped at 0h -

SMI Bank 0 mapped at 0h -

Figure 11. Boot mode selection implementation example
STR75x 3V3
10K*

3V3
10K*

BOOT0 BOOT1 TEST
GND

* these values are given only as typical example

This aliases the physical memory associated with each boot mode to Block 000 (boot memory).The value of the BOOT pin is latched on the 4th rising edge of CK_SYS after Reset. It is up to the user to manage the BOOT1 and BOOT0 pins at reset release to select the required boot mode. Note that the user should also manage these pins when exiting Standby mode as the BOOT pins are resampled. Even when aliased in the boot memory space, the related memory (FLASH, SRAM or SMI) is still accessible at its original memory space. After this start-up delay has elapsed, the ARM CPU will start code execution from the boot memory space, located at the bottom of the memory space starting from 0x0000_0000h. The application can read the status of the boot pins that was latched at start-up and change the memory aliasing on-the-fly by modifying the SW_BOOT bits in the CFG_GLCONF register. Caution: The TEST pin of the STR75x must always be forced to ground (ST reserved test pin)

14/22

AN2419

Boot configuration

3.1

Embedded boot loader mode
Embedded Boot Loader Mode is used to re-program the FLASH using one of the serial interfaces (typically a UART). This program, called, ICP boot loader, is located in the SystemMemory and is programmed by ST during production. Refer to the STR7 Family Flash Programming Reference Manual for details.

3.2

External memory (SMI) boot mode
When SMI boot mode is selected the Serial Memory Interface is automatically configured as follows:

Chip Select Polarity = low SMI bank 0 is selected and the associated I/O alternate functions are enabled. Boot Space (0000_0000h to 00FF_FFFFh -16MB) is aliased to SMI bank 0. The SMI is configured as NORMAL READ MODE (reset value) The SMI_PRESCALER is set to "2" (reset value)

Programming considerations when booting from SMI After RESET, the PLL is disabled and both CK_SYS and HCLK are clocked by the internal FREEOSC oscillator (1-10MHz). Consequently, the SMI clock output is also between 0.5 and 5MHz (SMI_PRESCALER reset state is 2). To use a higher frequency, software has to configure the clock and PLLs. Care is needed if the program performing the PLL and clock configuration is executed directly from serial memory. The software must ensure that a proper clock frequency is provided to the serial memory when changing the SMI_PRESCALER and switching the system clock. That is why the SMI_PRESCALER must be changed first before switching the system clock to the PLL output clock. For example, to use the SMI in NORMAL READ MODE with a 60 MHz HCLK frequency, set the SMI_PRESCALER to 4 before switching HCLK to 60 MHz. The SMI clock frequency is then 60 MHz / 4 = 15 MHz. It is possible to obtain the highest SMI frequency using the FAST READ MODE, if the serial memory supports this mode. For instance, fHCLK can be set to 48 MHz and the SMI_PRESCALER can be be loaded to "1" to address a high speed Serial Memory at 48 MHz (for read only). Note: Make sure that the SMI clock frequency (resulting from of your AHB clock and SMI_PRESCALER settings) does not exceed the maximum allowed value. The maximum frequency of the SMI is limited by the I/O speed. Take care to load the SMI_PRESCALER and the FAST_READ mode with the same write transaction. This can be done by a program which is executed from the serial Flash. In this case, the SMI will change the clock and the READ MODE only at the end of this access. For more details refer to the Reference Manual.

15/22

Debug management

AN2419

4

Debug management
The Host/Target interface is the hardware equipment that connects the Host to the application board. This interface is made of three components: a hardware debug tool, such as Micro-ICE from ARM, a JTAG connector and a cable connecting the host to the debug tool. Figure 12 shows the connection of the host to the STR75x board. Figure 12. Host to board connection
ICE Debug tool ICE connector

HOST PC STR75x EVAL

Power Supply

4.1

ICE debug tool
ICE Debug tool is a host interface that connects a PC to an STR75x development board featuring a debug interface as shown in Figure 12. The Embedded ICE is an intelligent host interface that provides fast access to host services, access to on-chip emulation and debug facilities. When the STR75x board is configured as a stand-alone system, the ICE Debug tool can be used to download programs. The STR75x development kit supports the ARM RealView ICE Micro Edition. The Micro-ICE is plugged in to the host via a USB cable.

4.2

JTAG / ICE connector
The ICE connector enables JTAG hardware debugging equipment, such as RealView-ICE, to be connected to the STR75x board. It is possible to both drive and sense the systemreset line, and to then send a JTAG reset to the core through the ICE connector. Figure 13 shows the ARM ICE connector pin-out. The STR75x has a user debug interface. This interface contains a five-pin serial interface conforming to JTAG, IEEE standard 1149.1-1993, "Standard Test Access Port-Scan Boundary Architecture". JTAG allows the ICE device to be plugged to the board and used to debug the software running on the STR75x. JTAG emulation allows the core to be started and stopped under the control of the connected debugger software. The user can then display and modify registers and memory contents, and set break and watch points.

16/22

AN2419 Figure 13. Ice connector implementation
3V3 STR75x
10K* 10K* 10K* 10K*

Debug management

3V3

3V3

3V3

3V3

JTAG Connector CN9 CONN_2*10

3V3

nJTRST JTDI JTMS JTCK RTCK JTDO NRSTIN
10K* 10K* 10K*

(1) VTref (3) nTRST (5) TDI (7) TMS (9) TCK (11) RTCK (13) TDO (15) nSRST (17) DBGRQ (19) DBGACK

(2) (4) (6) (8) (10) (12) (14) (16) (18) (20)

3V3
J4 See
Note 1 10K*

GND

10K*

* these values are given only as typical examples

Note:

1

The JTAG reset pin (nJTRST) is a dedicated pin: When JTAG communication is used on the application board, nJTRST must be connected to a pull-up. However, it is mandatory to apply one negative pulse on nJTRST pin after powerup otherwise the MCU may enter unexpected test modes. For instance, nJTSRT can be connected to the system reset which is pulled-up. When JTAG communication is not used on the application board, nJTRST can be connected to the system reset or it can be also indefinitely grounded.

Caution:

When the internal Flash is readout protected, the Flash will not execute if nJRST is not continuously reset because it is considered as an intrusion. Consequently, in this case, it is mandatory that the nJRST pin sees a continuous low level after reset when the user application is running.

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Debug management Table 3.
Std Name

AN2419 JTAG connector pins
STR75x Description Test Reset (from JTAG equipment) Test data in (from JTAG equipment) Test mode select (from JTAG equipment) Function This active LOW open-collector is used to reset the JTAG port and the associated debug circuitry. It is asserted at power-up by each module, and can be driven by the JTAG equipment. TDI goes down the stack of modules to the motherboard and then back up the stack, labelled TDO, connecting to each component in the scan chain. TMS controls transitions in the tap controller state machine. TMS connects to all JTAG components in the scan chain as the signal flows down the module stack.

nTRST

JTRST

TDI

JTDI

TMS

JTMS

TCK

JTCK

TCK synchronizes all JTAG transactions. TCK connects to all JTAG components in the scan chain. Series termination resistors are used to reduce reflections and maintain good Test clock (from signal integrity. TCK flows down the stack of modules and JTAG connects to each JTAG component. However, if there is a equipment) device in the scan chain that synchronizes TCK to some other clock, then all down-stream devices are connected to the RTCK signal on that component. Using a mechanism called adaptive clocking, the RTCK Return TCK (to signal is returned by the core to the JTAG equipment, and the clock is not advanced until the core had captured the JTAG equipment) data. In adaptive clocking mode, the debugging equipment waits for an edge on RTCK before changing TCK. Test data out (to JTAG equipment) TDO is the return path of the data input signal TDI. nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when a board has been reset by the user. When the signal is driven LOW by the reset controller on the core module, the motherboard resets the whole system by driving nSYSRST low.

RTCK

RTCK

TDO

JTDO

nSRST

NRSTIN

System reset (bidirectional)

For more details on the JTAG port refer to the IEEE standard 1149.1-1993, "Standard Test Access Port-Scan Boundary Architecture" specification.

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AN2419

Reference design

5
5.1

Reference design
Main
This reference design is based on the STR750, a highly integrated microcontroller, running at 64MHz that combines the popular ARM7TDMI-STM 32-bit RISC CPU with 256 Kbytes of embedded Flash, 16Kbytes of high speed SRAM.

5.1.1

Clock
Two clock sources are used for the microcontroller.

X1-32 kHz crystal for embedded RTC X2-4 MHz crystal for STR750Fx microcontroller

5.1.2

Reset
The reset signal on this STR750-REF schematic is active low. The reset sources include:

Power On Reset from STM1818 (U2) Reset button (PB1) Debugging tools via the connector CN1

5.1.3

Boot mode
The STR750 is able to boot from:

Embedded User Flash Embedded SRAM for debugging System memory with boot loader for ISP External SPI Interface Flash

The boot option is configured by setting switches SW1 (Boot 0) and SW2 (Boot 1).

5.2

JTAG interface
Refer to the section Section 4: Debug management on page 16.

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6

20/22
2 +3V3 R1 2 1 +3V3 10K U1 3 SW1 3 4 P000 P001 P002 P003 P004 P005 P006 P007 SW2 R7 2 1 +3V3 10K 3 A

Schematics

1

CN1

+3V3

TRST

TDI

R2

10K

A

TMS

R3

10K

TCK

R4

10K

Schematics

RTCK

R5

10K

TDO

R6

10K

RESET

R8

10K

DBGRQ +3V3 R11 10K

R9

10K

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 TDI TDO TCK TMS TIM0_OC2/P1.00 TIM0_TI2/P1.01 TIM2_OC2/P1.02 TIM2_TI2/P1.03 P WM3N/P1.04 P WM3/P1.05 P WM2N/P1.06 P WM2/P1.07 P WM1N/P1.08 P WM1/P1.09 P WM_EMERG/P1.10 UART0_RTS/P1.11 P1.12 P1.13 P1.14 WAKUP/P1.15 JTDI/P1.16 JTDO/P1.17 JTCK/P1.18 JTMS/P1.19

DBGACK R 1 0

10K

95 94 68 67 91 90 89 88 87 81 80 34 1 93 92 60 21 20 19 18

JTAG connector

B JP1 TRST JP3 JP2 RESET

B

BOOT0/TIM0_OC1/P0.00 MCO/TIM0_TI1/P0.01 TIM2_OC1/P0.02 TIM2_TI1/P0.03 SMI_CS0/SSP0_NSS/P0.04 SSP0_SCLK/P0.05 SMI_DIN/SSP0_MISO/P0.06 SMI_DOUT/SSP0_MOSI/P0.07 I2C_SCL/P0.08 I2C_SDA/P0.09 SMI_CS3/UART0_RX/P0.10 BOOT1/SMI_CS2/UART0_TX/P0.11 SMI_CS1/UART0_CTS/P0.12 RTCK/UART0_RTS/P0.13 CAN_RX/P0.14 CAN_TX/P0.15 SSP1_SCLK/P0.16 SSP1_MISO/P0.17 SSP1_MOSI/P0.18 SSP1_NSS/USB_CLK/P0.19 UART1_RX/P0.20 UART1_TX/P0.21 UART1_CTS/P0.22 UART1_RTS/P0.23 UART2_RX/P0.24 UART2_TX/P0.25 UART2_CTS/P0.26 UART2_RTS/P0.27 TIM1_OC1/P0.28 TIM1_TI1/P0.29 TIM1_OC2/P0.30 TIM1_TI2/P0.31 P009 P010 P011 P012 RTCK P014 P015 P016 P017 P018 P019 P020 P021 P022 P023 P024 P025 P026 P027 P028 P029 P030 P031 3V3 V33 V33 V33 V18 V18REG V18BKP 96 52 55 3V3 Vdda_PLL 45 3V3 Vdda_ADC VREG_DIS 70 75 VREG_DIS GND C4 1uF C2 10uF C3 33nF 69 99 44 C1 1uF

4 3 2 100 79 78 77 76 30 29 28 27 26 25 64 63 42 41 40 39 17 16 15 11 38 37 36 35 8 7 6 5

R12 10K

P200 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P2.00 P2.01 P2.02 UART1_RTS/P2.03 TIM2_OC1/P2.04 P WM3N/P2.05 P WM3/P2.06 P WM2N/P2.07 P WM2/P2.08 P WM1N/P2.09 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 P2.16 UART2_RTS/P2.17 P2.18 P2.19

24 23 14 13 12 86 85 84 83 82 72 71 62 61 51 50 43 33 32 31

Figure 14. STR750F microcontroller connections

U2 1 4 GND X1 4 R13 TRST 9 TEST STR750 4MHz C7 22pF C8 22pF C6 22pF 1M X2 USB_D+ USB_DRESET 3 RESET RSTOUT 59 58 NRSTIN NRSTOUT P B1 2

RST +3V3

C

VSS

C

VCC

STM1818TWX7F

1

C5 2 3 22pF MC306_32KHz

57 56 66 65 46 47 22 XRTC1 XRTC2 USB_DP USB_DN XT2 XT1 NJTSRST

Vss33 Vss33 Vss33 Vss33 Vss18 Vss18 Vssa_ADC Vssa_PLL VssBKP

74 48 98 10 53 97 73 49 54

D

STMicroelectronics
Title:

D

STR750-REF
Number:001 Rev: B.1(PCB.SCH) 3 Date: 23/08/06 4 Sheet

1of

1

1

2

AN2419

AN2419

Revision history

7

Revision history
Table 4.
Date 20-Nov-2006 09-Jul-2007

Document revision history
Revision 1 2 Initial release. References to VREF_ADC pin removed from document Table 1: Typical prescaler uses on page 13 enhanced Changes

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AN2419

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Document Number: 12643



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