AN2451 Application note
ST7540 FSK powerline transceiver design guide for AMR
Introduction
The ST7540 reference design has been developed as a useful tool to demonstrate how a small, high-performance powerline node can be built using the ST7540 FSK transceiver. With this reference design, it is possible to evaluate the ST7540 features, in particular, its transmitting and receiving performances through actual communication on the power line. The ST7540 reference design may be considered to be composed of three main sections:
Power supply section, specifically tailored to match powerline coupling requirements and to operate within a wide range of the input mains voltage Modem and crystal oscillator section Line coupling interface section
The coupling interface is designed to allow the ST7540 FSK transceiver to transmit and receive on the mains using 72 kHz carrier frequencies, within the European CENELEC standard A-band specified for automatic meter reading. Figure 1. ST7540 reference design board with outline dimensions
52 mm
76 mm
As it can be seen from the picture above, a special effort has been made to obtain a very compact reference design board, while keeping the focus on transmission and receiving performances. Note: The information provided in this application note refers to EVALST7540-1 reference design board.
January 2008
Rev 2
1/55
www.st.com
Contents
AN2451
Contents
1 2 3 4 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Safety precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ST7540 FSK powerline transceiver description . . . . . . . . . . . . . . . . . . 10 Evaluation tools description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Coupling interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 5.1.2 5.1.3 5.1.4 Tx active filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Tx passive filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Rx passive filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2
Conducted disturbances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.1 5.2.2 Conducted emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 5.4 5.5 5.6 5.7
Thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Oscillator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Surge and burst protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 50-pin connector for the EVALCOMMBOARD . . . . . . . . . . . . . . . . . . . . . 35 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 7
Performance and ping tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 7.2 7.3 7.4 7.5 7.6 Three-phase architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Zero crossing detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Received Signal Strength Indicator (RSSI) . . . . . . . . . . . . . . . . . . . . . . . 44 Nonisolated coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC powerline applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 110 and 132.5 kHz coupling circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8
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Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
AN2451
Contents
Appendix A Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 10 List of normative references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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List of figures
AN2451
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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ST7540 reference design board with outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical curve for output current limit vs. RCL value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ST7540 Transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Complete evaluation system including a PC, an EVALCOMMBOARD and the EVALST7540-1 board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ST7540 powerline modem demonstration kit with control register window . . . . . . . . . . . . 12 Positioning of the various sections of the board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Modem and coupling interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power supply schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Schematic of Rx and Tx filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Measured frequency response of the Tx active filter (typical curve). . . . . . . . . . . . . . . . . . 20 Simulated frequency response of the Tx active filter with components tolerance effect. . . 20 Measured frequency response of the Tx active + passive filters connected to the CISPR network (typical curve) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Simulated frequency response of the Tx active + passive filters connected to the CISPR network with the components tolerance effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Measured frequency response of the Rx passive filter (typical curve) . . . . . . . . . . . . . . . . 23 Simulated frequency response of the Rx passive filter with components tolerance effect . 24 Measured input impedance magnitude of coupling interface in Tx mode (typical curve) . . 25 Measured input impedance magnitude of coupling interface in Rx mode (typical curve) . . 25 Conducted emissions test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output spectrum (typical) at 72 kHz, 2400 baud, deviation 1, fixed transmitted tone = "1", mains 220 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Narrow-band conducted interference test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Measured BER vs. SNR curve (typical), white noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SNR vs. frequency curve (typical) at BER = 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PCB copper dissipating area for ST7540 reference design board . . . . . . . . . . . . . . . . . . . 29 Packet-fragmented transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Equivalent model of the thermal impedance qJA of the HTSSOP28 package with exposed pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Output current vs. supply current typical curve for ST7540 in Tx mode . . . . . . . . . . . . . . . 31 Dissipated power vs. load impedance modulus typical curve for ST7540 reference design board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 A recommended oscillator section layout for noise shielding . . . . . . . . . . . . . . . . . . . . . . . 32 Common mode disturbances protection - positive disturbance . . . . . . . . . . . . . . . . . . . . . 33 Common mode disturbances protection - negative disturbance. . . . . . . . . . . . . . . . . . . . . 34 Differential mode disturbances protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Scheme of the connector for the EVALCOMMBOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical waveforms at 230 Vac: open load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical waveforms at 230 Vac: full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical waveforms at 265 Vac: short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical waveforms at 265 Vac: startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SMPS efficiency curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ST7540 powerline modem demonstration kit window for the master board . . . . . . . . . . . . 41 Scheme of principle for three-phase architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Schematic of a zero crossing detection circuit for nonisolated coupling. . . . . . . . . . . . . . . 43 Schematic of a zero crossing detection circuit for isolated coupling. . . . . . . . . . . . . . . . . . 44 ZC_OUT vs. AC mains waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AN2451 Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51.
List of figures Peak detector electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Measured DC_OUT Vs. AC_IN peak detector response . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Example schematic for nonisolated solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Line coupling interface for 110 kHz channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Line coupling interface for 132.5 kHz channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PCB layout - component placing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PCB layout - top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PCB layout - bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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List of tables
AN2451
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Electrical characteristics of the ST7540 reference design . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Output voltage level setting through Vsense partitioning - typical values. . . . . . . . . . . . . . . . 8 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ST parts on the ST7540 reference design board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Line coupling transformer specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Noise immunity test settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 50-pin connector digital signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 50-pin connector analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 50-pin connector power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SMPS specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SMPS transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Electrical characteristics
1
Table 1.
Electrical characteristics
Electrical characteristics of the ST7540 reference design
Value Min Typ Operating conditions Max Notes
Parameter
Ambient operating temperature Transceiver section Transmitting specifications (Tx mode) Selected channel frequency Transmitting output voltage level at mains output Transmitting output current limit 2nd Harmonic distortion at mains output 3rd Harmonic Distortion at mains output 50 Hz attenuation 100dB Receiving specifications (Rx mode) Minimum detectable Rx signal 49 dBuV RMS Auxiliary supply 5 V Regulated voltage 5 V Current capability 3.3 V Regulated voltage 3.3 V Current capability -5% 3.3 V -5% 5.05 V 72 kHz
85 C
If ST7540 junction temperature exceeds 180 C, device shuts down
FSK carrier R7=6.2 k, R8=1.5 k. See Table 2 R6=1.3 k. See Figure 2 -55dBC Loaded with CISPR 16-1 network Loaded with CISPR 16-1 network
2VRMS
2.25VRMS
500mARMS
-61dBC
BER<10-3, negligible noise
+5% 50 mA +5% 50 mA
ST7540 Internally generated
ST7540 Internally generated
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Electrical characteristics Table 1. Electrical characteristics of the ST7540 reference design (continued)
Value Min Typ Power supply section AC mains voltage range Mains frequency Output voltage Output voltage ripple Peak output current Output power Efficiency at Pout=3.5 W Nominal transformer Isolation(1) Number of holdup cycles Input power Switching frequency 100 mW -10% 65 kHz +10% 70% Primary to secondary/ secondary to auxiliary -10% 85 V 50-60 Hz 12.3 V +10% 1% 500 mA 5.6 W 265 V Max
AN2451
Parameter
Notes
Green LED ON IOUT = 500 mA, Vin=85 Vac
4 kV
0
Transceiver section in Tx mode
1. ST does not guarantee transformer isolation. ST assumes no responsibility for the consequences that may arise from that risk.
Table 2.
Output voltage level setting through Vsense partitioning - typical values
V(PA_OUT) [dBuVRMS] 114 118 120 121 122 124 126 127 128 130 R7 [k] 0.620 1.8 2.7 3.3 3.9 5.1 6.2 8.2 9.1 11 R8 [k] 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
V(PA_OUT) [VRMS] 0.500 0.800 1.000 1.125 1.250 1.500 2.000 2.250 2.500 3.160
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AN2451 Figure 2. Typical curve for output current limit vs. RCL value
Safety precautions
2
Safety precautions
The board must be used only by expert technicians. Due to the high voltage (220 V ac) present on the parts which are not isolated, special care should be taken with regard to people's safety. There is no protection against high voltage accidental human contact. After disconnection of the board from the mains, none of the live parts should be touched immediately because of the energized capacitors. It is mandatory to use a mains insulation transformer to perform any tests on the high voltage sections (see circuit sections highlighted in Figure 7 and Figure 8) in which test instruments like Spectrum Analyzers or Oscilloscopes are used. Do not connect any oscilloscope probes to high voltage sections in order to avoid damaging instruments and demonstration tools.
Warning:
ST assumes no responsibility for any consequences which may result from the improper use of this tool.
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ST7540 FSK powerline transceiver description
AN2451
3
ST7540 FSK powerline transceiver description
ST7540 transceiver uses Frequency Shift Keying (FSK) modulation to perform a half-duplex communication on a powerline network. It operates from a 7.5 to 13.5 V single supply voltage (Vcc) and integrates a power amplifier (PA), which is able to drive low line impedance, and two linear regulators providing 5 V and 3.3 V. Figure 3. ST7540 Transceiver block diagram
The ST7540 can communicate using eight different communication channels (60, 66, 72, 76, 82.05, 86, 110, 132.5 kHz), four baud rates (600, 1200, 2400, 4800) and two deviations (1 and 0.5). Additional functions are included, such as watchdog, automatic control on PA output voltage and current, carrier/preamble detection and band-in-use signaling, transmission time-out, and thermal shutdown. The transceiver, which is dedicated only to physical communication, operates with a microcontroller whose aim is to manage the communication protocol stack. A reset output (RSTO) and a programmable clock (MCLK) can be provided to the microcontroller by the ST7540 in order to simplify the external logic and circuitry. The host controller can exchange data with the transceiver through a serial interface, programmable to operate either in UART (CLR/T data clock not used) or in SPI mode. Communication on the power line can be either synchronous or asynchronous to the data clock that is provided by the transceiver at the programmed baud rate. When in transmission mode (i.e. RxTx line at low level), the ST7540 samples the digital signal on the TxD line at the programmed baud rate and modulates it in a FSK sinusoidal output on the Tx_OUT line. This signal is then externally fed into the power amplifier to add current capability. The power amplifier can also introduce gain and active filtering to the signal, just using few external passive components. The resulting signal on the PA_OUT line is coupled to the power line. When in receiving mode (i.e. RxTx line at high level), an incoming FSK signal on the Rx_IN line is demodulated and the digital output is available for the microcontroller on the RxD pin.
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AN2451
Evaluation tools description The device also recovers the synchronism of the received signal using an internal PLL. The recovered clock is present on CLR/T output. The ST7540 operating parameters can be set by means of an internal control register, accessible only through the SPI host interface.
4
Evaluation tools description
The complete evaluation system for the ST7540 powerline communication consists of:
a PC using the "ST7540 Power Line Modem Demo Kit" software tool one EVALCOMMBOARD hosting the ST7 microcontroller one ST7540 reference design board (EVALST7540-1).
The correct procedure for connecting the EVALST7540-1 and the EVALCOMMBOARD is as follows: 1. 2. 3. 4. Connect the EVALST7540-1 and the EVALCOMMBOARD Connect the ac mains cable to the EVALST7540-1 and the USB cable to the EVALCOMMBOARD Connect the EVALST7540-1 to the ac mains supply Connect the EVALCOMMBOARD to the PC via the USB cable.
Warning:
Follow the connection procedure to avoid damaging the boards.
Figure 4.
Complete evaluation system including a PC, an EVALCOMMBOARD and the EVALST7540-1 board
USB / RS232
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Evaluation tools description Figure 5.
AN2451
ST7540 powerline modem demonstration kit with control register window
The complete chain, controlled by the ST7540 powerline modem demonstration kit, can set up real communication at bit level, simply by sending or receiving a user-defined bit stream. It is possible to establish a half-duplex communication with two of these communication nodes (two chains) connected to each other. In order to better evaluate communication between two nodes, the ST7540 powerline modem demonstration kit has some particular features, including:
Frame synchronization: a byte synchronization header can be added to the to the exchanged data to set up a simple protocol, intended to test the capability of the system to correctly receive the exact transmitted bit sequence. This can be done in two ways: via the ST7540 control register settings (the internal configuration register of the modem has a frame header field, in which an 8- or 16-bit header can be set) or via the Rx panel of the ST7540 powerline modem demonstration kit (setting a synchronization at SW level). A bit synchronization can be introduced as a simpler feature by enabling the preamble detection method in the control register panel and then inserting at least one "0101" or one "1010" sequence at the beginning of the transmitted bit stream. Ping session: a master-slave communication with automatic statistics calculation can be very useful to test a point-to-point or a point-to-multipoint powerline communication network, thus providing a method to evaluate reachability of each node in the network. For further details about the ST7540 powerline modem demonstration kit, please refer to the user manual UM0239 "ST7540 power line modem demo kit graphical user interface".
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Board description
5
Board description
The ST7540 reference design is composed of the following sections:
Power supply section, based on ST's VIPer12A-E IC ST7540 modem and crystal oscillator section Line coupling interface section, with three subsections: Transmission active filter Transmission passive filter Receiving passive filter.
The board also has two connectors, which allow the user to plug the mains supply on one side of it and the I.B.U. communication board on the other side. Figure 6. Positioning of the various sections of the board
Connection to Mains Supply
Power Supply (with ST VIPer12A -E)
Connection to C Board C Board
Line Coupling Interface
ST7540 Modem Section
The schematics of the whole reference design appear in Figure 7 and 8. Figure 7 shows the modem and the coupling Interface circuits, while Figure 8 represents the power supply circuit. In both the schematics, high voltage regions are highlighted. Table 3 lists the components used to develop the reference design board. All parts have been selected to give optimal performances. The layout of the printed circuit is given in Appendix A - Figure 49, Figure 50 and Figure 51.
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2
BU/THERM Vcc WD CL 3 1 ALTERNATIVA 1 10 RSTO VDC Vdd PA_INPA_OUT Rx_IN Tx_OUT C19 100nF R18 18k C32 390 pF R10 13k C33 150 pF Rx_IN C27 10 nF R17 750 4 5 PA_IN+ 1 R19 3k9 R9 4k7 C22 10uF A T2 8 B R12 1k R16 NM R20 25k C20 NM D8 BAV99 P VDC C31 22 pF 2
1 2 3 4 5 VDC 2 L6 220 uH Rx_IN Vcc VDC ANALOG_DIG_OUT D10 BAV99 3
Vdd JP4 1 CLOSE U3 2
VDC
1
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C21 150pF R13 0 Ohm 3 R14 1k8
Board description
Figure 7.
TEST PADS
Tx Rx RxTx Vcc A 5 6 T2X B CLRT C30 15 pF JP3 CLOSE 1-2 1
REG_DATA
REG_DATA
TxD
MCLK
MCLK
RxD
UART/SPI
UART
Rx/Tx
BU/THERM
CLR/T
HIGH VOLTAGE SECTION
Vsense
Vsense
WD
CD/PD
CD/PD
CL
Tx_OUT
Tx_OUT
RSTO
PA_OUT
PA_OUT
VDC
PA_IN-
PA_IN-
Vdd
L5 47 uH
C23 100nF X2 N
PA_IN+
PA_IN+
Rx_IN
PA
D9 SMBJ12CA
J1 C26 22 nF
P
SVss
PEAK METER CONNECTOR
CL VDC C12 33pF Rx_IN CL Vsense R6 1k1
VDC Vcc Vdd VDDF Vdd RxD Rx/Tx TxD BU/THERM CLR/T
CN2
Vcc
CD/PD REG_DATA
Modem and coupling interface schematic
VDDF_FORCE
ST7540
X1 16Mhz OSCIN Tx_OUT PA_IN+ PA_OUT Tx_OUT R7 6k2 Vsense Vcc C11 33pF
ANALOG_DIG_OUT ANALOG_DIG_OUT B_ID_PLM1 GND B_ID_PLM0 GND RSTO RSTO Vcc UART/SPI WD BU/THERM C24 10 uF C25 100 nF C15 10 uF VDC
MCLK RSTO UART/SPI WD PA_IN-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 CD/PD REG_DATA GND RxD Rx/Tx TxD BU/THERM CLR/T Vdd MCLK RSTO UART/SPI WD PA_INTEST2 TEST1 VDC Rx_IN CL Vsense X2 X1_OSCIN SVss Tx_OUT PA_IN+ Vcc Vss PA_OUT
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CD/PD REG_DATA RxD Rx/Tx UART/SPI WD BU/THERM
CD/PD REG_DATA RxD Rx/Tx
VDC
Vdd
C14 10nF
CLR/T
CLR/T
R8 1k5
TxD
TxD
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
CON50A
C16 100 nF
C17 10 uF
C18 100 nF
AN2451
Digital Ground
Analog Signal Ground
Analog Power Ground
AN2451 Figure 8.
4
Vcc
TEST PADS
Vcc
Vss L3 470uH 4 D1 BRIDGE R2 220k T1 1 D4 2 3 L2 D2 8 2 Q1 3 D3 1 3 2 3 5 560 R4 + C9 47uF 16V C29 47uF 16V D6 L ED C8 470uF 16V R5 1k5 1 Vcc L4 33 uH 2 1 10 1 + C3 10uF 400V + C2 10uF 400V 470pF 630V + C4
F1 T - 2A
R1 10R 1W
CN1
5
6
P
Power supply schematic
3
1 2
C1 33nF X2
N
L1 1 mH
AC INPUT
85 V ac to 256 V ac
1
C5 220 pF R3 10 K
4
U1 C6 10 uF DRAIN 4 Vdd 3 FB 2 1S 5 6 7 8
C10 2.2 nF 3 4 1
DC OUTPUT 12 V dc
2 U2 3 D5 10V 1 2
HIGH VOLTAGE SECTION
C7 47 nF
Board description
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Board description
AN2451
Table 3.
Item
Bill of materials
Qty Part WD, Vsense, Vdd, Vcc, VDC, RxD, UART/SPI, Tx_OUT, TxD, RxTx, Value Description
1
21
RSTO, REG_DATA, PA_OUT, PA_IN-, PA_IN+, MCLK, GND, CLR/T, CL, CD/PD, BU/THERM
Testpoint
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 1 1 2 1 1 4 1 1 2 1 2 1 2 4 1 1 1 1 1 1 1 1 1 1
CN1 CN2 C1 C2,C3 C4 C5 C6,C15,C17,C24 C7 C8 C9,C29 C10 C11,C12 C13 C14,C27 C16,C18,C19,C25 C20 C21 C22 C23 C26 C30 C31 C32 C33 D1
Header 2 CON50A 33 nF X2 10 F / 400 V 470 pF / 1 kV 220 pF / 50 V 10 F / 16 V 47 nF / 25 V 470 F / 16 V 47 F / 16 V 2.2 nF Y1 33 pF NM 10 nF 100 nF NM 150 pF 10 F 100 nF X2 22 nF 15 pF 22 pF 390 pF 150 pF DF06S
Mains supply connector 50 pins SMT right angle female p=1.27 mm Murata GA355XR7-GB333K Yageo SE-K / Nichicon VK 20% TDK C4520X7R-3A471K TDK C0603C0G-1E220J TDK C3216X7R-1C106MT Murata GRM188R7-1E473K Rubycon 3M0319 / Yageo SE-K 20% Murata GRM32ER6-1C476K TDK CD12-E2GA222MYNS / Murata DE1E3-KX222M TDK C1005C0G-1H330J
Murata GRM188R7-1H103K TDK C1608X7R-1H104K
Murata GRM1555C-1H151J Murata GRM21BR6-1A106K / TDK C2012X5R-0J106K EPCOS B32922-A2683K p=15 mm 10% Murata GRM21B5C-1H223J / TDK C3216C0G1H223J Murata GRM1555C-1H150J Murata GRM1555C-1H220J Murata GRM1885C-1H391J Murata GRM1885C-1H151J 600 V - 1.5 A bridge rectifier
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AN2451 Table 3.
Item 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
Board description Bill of materials (continued)
Qty 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 2 1 1 1 Part D2 D3 D4 D5 D6 D8,D10 D9 F1 JP3 J1 L1 L2 L3 L4 L5 L6 Q1 R1 R2 R3 R4 R5,R8 R6 R7 R9 R10 R12 R13 R14 R15,R16 R17 R18 R19 Value STTH1L06A BAS16 2L STPS1H100 BZX84C10 LED BAV99 SMBJ12CA-TR 2AT Close 1-2 Peak meter 1 mH 2x10 mH 470 H 33 H 47 H 220 H BC857BL 10R 1 W 220 k 10 k 560 1K5 1K1 6K2 4K7 13 k 1 k 0 (jumper) 1K8 NM 750 18 k 3K9 Metal oxide - radial Epcos B82442-H1105K Radiohm 42V15 0.3A Epcos B82442-A1474K Epcos B82462-A4333K Epcos B82464-A4473K / Würth 744-775-147K Epcos B82462-A4224K / Wür th 744-774-222K Description DO214AC BAS21 also suitable DO214AC 10V Zener Green LED Dual SMD diode 12V bidirectional transil diode Time-lag
17/55
Board description Table 3.
Item 60 61 62 63 64 65 66
AN2451
Bill of materials (continued)
Qty 1 1 1 1 1 1 1 Part R20 T1 T2 U1 U2 U3 X1 Value 25 k SMPS transformer Line transformer VIPer12AS-E SFH610-A ST7540 16 MHz TDK SRW12.6EF-E07H013 / Wür th S06-100-057 Vac T60403-K5024-X044 / Radiohm 69H14-2101 Voltage regulator Optoswitch Powerline transceiver Jauch Q 16.0-SS2-16-30/50-FU Description
Table 4.
ST parts on the ST7540 reference design board
Value ST7540 VIPer12AS-E STTH1L06A STPS1H100 SMBJ12CA-TR Description Powerline transceiver SMPS controller / switch Ultrafast diode Schottky diode 12 V bidirectional transil diode
5.1
Coupling interface
The mains coupling interface is composed of three different filters: the Tx active filter, the Tx passive filter and the Rx passive filter. All three filters are described in the sections Section 5.1.1, 5.1.2, and 5.1.3. In each section, calculations and measured frequency responses are given. The filters are quite sensitive to the components' value tolerance. Actual components used in the ST7540 reference design have the following tolerances:
+/- 10% for coils and for the X2 capacitor +/- 1% for SMD resistors +/- 5% for SMD ceramic capacitors.
To evaluate sensitivity of the filters to the tolerances listed above, the following sections include simulated responses of the filters with Montecarlo statistical analysis. Statistical simulation helps understanding the relationship between components' value tolerance and variations on the responses of the filters. In simulation curves, the ideal response is drawn in blue, while red curves indicate statistical variations generated through simulation.
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AN2451 Figure 9. Schematic of Rx and Tx filters
C21 150pF
Board description
Tx ACTIVE FILTER
C31 22 pF VDC R12 1k R20 25k Tx_OUT R19 3k9 C19 100nF R18 18k C32 390 pF R10 13k R9 4k7 PA_IN-
C30 15 pF
Vcc 2
R14 1k8
3
D8 BAV99
PA_OUT
C22 10uF A 1 R17 750 4 5 T2 8 B
1
L5 47 uH
C23 100nF X2 N
PA
PA_IN+
C33 150 pF
Rx_IN
C27 10 nF
D9 SMBJ12CA
P VDC 2 L6 220 uH C26 22 nF
Tx PASSIVE FILTER
D10 BAV99
3
Rx PASSIVE FILTER
5.1.1
Tx active filter
The Tx active filter is based on the ST7540 internal Power Amplifier (PA), whose input and output pins are available externally to allow a filtering network to be tailored around the amplifier. For the ST7540 reference design board, a 3-pole low-pass filter has been developed by cascading a simple R-C low-pass stage and a Sallen-Key 2-pole cell with 9dB gain. The R19-C32 low-pass stage is aimed at introducing attenuation starting from approximately an octave above the transmission channel frequency. The transfer function of the 2nd order Sallen-Key cell is: Equation 1
A0 A ( s ) = -----------------------------------------2 s --s---- + ---------------- + 1 -2 ·Q C
C
R 14 R9 · R 0 · C 3 · C 1 1 where A 0 = 1 + --------- , C = ---------------------------------------------------------- and Q = -------------------------------------1---------------3--------------2----------------- R 12 R 9 C 33 + R 10 C 21 + R 9 C 21 ( 1 A 0 ) R 9 · R 10 · C 33 · C 21
The corner frequency may be calculated as: Equation 2
1 f c = ----------------------------------------------------------------------- = 135.7 k H z 2 · R 9 · R 10 · C 33 · C 21
Figure 10 represents the measured transfer function of the Tx active filter. It shows good rejection on both the 2nd and 3rd harmonic frequencies for the 72 kHz signal.
1
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Board description
AN2451
Figure 10. Measured frequency response of the Tx active filter (typical curve)
Frequency Response - Tx Active Filter
15 10 5 0
f = 72 kHz G = 9 . 7 dB f = 144 kHz G = 1 . 1 dB f = 216 kHz G = -8.0 dB
Gain [dB]
-5 -10 -15 -20 -25 -30 -35 1. 00E+ 04
1.00E+ 05
1. 00E+06
Freq [Hz]
Simulation of the Tx active filter response against components' tolerance, depicted in Figure 11, shows +/- 1 dB variation in gain module at 72 kHz. Figure 11. Simulated frequency response of the Tx active filter with components tolerance effect
15
10
+1 dB -1 dB
5
0
-5
-1 0 1E4 1E5 3 E5
freq, Hz
5.1.2
Tx passive filter
Coupling to the power line requires some passive components in addition to the active filtering stage. In particular, Tx passive filter section is made of the decoupling capacitor C22, line transformer T2, inductor L5 and X2 safety capacitor C23. L5 has been accurately chosen to have a high saturation current (>1 A) and a very low equivalent series resistance (<0.2 ), to limit distortion and insertion losses even with heavy line load. Center frequency for the series resonance is calculated as: Equation 3
1 f c = -------------------------------2 L 5 · C 23
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AN2451
Board description provided that the dc-decoupling capacitor C22 is much greater than C23 (in this case, 100 times greater) and that parasitic components of the transformer have negligible effects on the filtering action. Par ticular attention has been paid in choosing the line transformer. The required characteristics are listed in Table 5. In order to have a good power transfer and to minimize the insertion losses, it is recommended to choose a transformer with a primary (shunt) inductance greater than 1mH and a series resistance lower than 0.5 . Another important parameter is the leakage inductance. If it has a relevant value (10 to 50 uH), this can be used to design the coupling filter without inserting series inductance (L5, L6). The drawback, however, is the poor accuracy of this parameter, which can lead to a shift of the filter response and to bad coupling. Consequently, a low leakage inductance value (<1 H) has been chosen, fixing the series inductance through a discrete component with greater accuracy. The last specified parameter, the 4 kV insulation voltage requirement, is described and coded in the EN50065-4-2 CENELEC document. Table 5. Line coupling transformer specifications
Parameter Turn ratio Magnetizing inductance Leakage inductance DC resistance DC saturation current Interwinding capacitance Withstanding voltage Value 1:1 >1 mH <1 H <0.5 >2 mA < 50 pF 4 kV
Figure 12 shows the measured response of the Tx active and passive filters, loaded with the CISPR network. The figure highlights a further filtering effect added by the passive L-C series resonant combined with the CISPR reactive load.
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Board description Figure 12. Measured frequency response of the Tx active + passive filters connected to the CISPR network (typical curve)
Frequency Response - Tx_OUT to CISPR network
20
AN2451
10
f = 72 kHz G = 9.8 dB
0
Gain [dB]
f = 144 kHz G = -4.4 dB f = 216 kHz G = -15.2 dB
- 10
- 20
- 30
- 40 1.00E+04
1.00E+05
1.00E+06
Freq [Hz]
Figure 13. Simulated frequency response of the Tx active + passive filters connected to the CISPR network with the components tolerance effect
15
10
+1 dB -1 dB
5
0
-5
-1 0
-1 5
-2 0 1 E4 1E5 3 E5
freq, Hz
5.1.3
Rx passive filter
The Rx filter is made up of a resistor in series with a parallel L-C resonant. The transfer function of the filter can be written as: Equation 4
s · L + RL -------------6-------------R 17 L C 2 R ( s ) = ------------------------------------------------6--------6---------------------------------- -R 17 + R L 2 R 17 R L C 26 + L 6 --------------------------------------- · s + ------------------------s+ R 17 L 6 C 26 R 17 L 6 C 26
where RL is the DC series resistance of the inductor (in our case, about 2.7 ). The center frequency and the quality factor of the filter can be expressed as:
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AN2451 Equation 5
Board description
R 17 L 6 C 26 1 1 R 17 + R L 1 f c = ------ · C = ------ ------------------------- -------------------------- , Q = --------------------------------------- · C 2 2 R 17 L 6 C 26 2 L C R 17 R L C 26 + L 6 6 26
The simplification made on fc formula is possible because R17>RL. Consequently, the quality factor and filter selectivity depend not only on R17, but also on RL. A higher RL produces a lower steepness of the resonance, while a higher R17 gives a higher selectivity. Actual values of the components give a Q nearly equal to 6. The RL value impacts in a clearer way on insertion losses. To evaluate the relationship between RL and the losses on the received signal, the following simplified expression of R ( s ) at f=fc may be used: Equation 6
C · L 6 R ( j · 2 f c ) Q · ------------------ = -----------------------1-----------------------R 17 C 26 1 + R L · R 17 · -------L6
With actual values of the components, we get a loss of about 2 dB. The same calculation gives unitary transfer if RL is set to zero. Looking at the first way to express the module of the transfer function, it is possible to notice that a higher value of Q can help keeping the losses small. Nevertheless, a high value of Q would bring a higher sensitivity of the filter to the components tolerance. Figure 14 shows the measured frequency response of the Rx passive filter. The filter has an actual -3 dB bandwidth equal to 12 kHz and an attenuation of about 2 dB at center frequency, just as expected. Figure 14. Measured frequency response of the Rx passive filter (typical curve)
f = 72 kHz G = -2.3 dB
Figure 15 represents a simulation of the response of the Rx passive filter with the components tolerance effect. A worst case loss of nearly 2 dB can be observed at 72 kHz due to a shift on center frequency.
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Board description
AN2451
Figure 15. Simulated frequency response of the Rx passive filter with components tolerance effect
0
-2 dB
-5
-1 0
-1 5
-2 0
-2 5
-3 0 3 E4 4E4 5 E4 6E4 7E4 8 E4 9E4 1 E5 2E5
freq, Hz
5.1.4
Input impedance
The input impedance of a powerline communication node is another critical point. Figure 16 and Figure 17 show the input impedance magnitude vs. frequency curves in both Tx and Rx mode. In both figures channel impedance point and the minimum impedance point are indicated. The impedance magnitude values prove that the ST7540 reference design board is compliant with the EN50065-7 document, which sets the following minimum impedance constraints for this kind of equipment:
Tx mode: free in the range 3 to 95 kHz 3 from 95 to 148.5 kHz 10 from 3 to 9 kHz 50 between 9 and 95 kHz only inside signal bandwidth (free for frequencies outside signal bandwidth) 5 from 95 to 148.5 kHz
Rx mode:
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AN2451
Board description Figure 16. Measured input impedance magnitude of coupling interface in Tx mode (typical curve)
Output Impedance - Txmode nput Impedance Tx mode
160 150 140 130 120
Impedance [Ohm]
110 100 90 80 70 60 50 40 30 20 10 0 10000.0
f = 72 kHz |Z| = 6
f
I
10 0 0.0
= 82.5 kHz |Z| = 2
10 0 00.0
Freq [Hz]
Figure 17. Measured input impedance magnitude of coupling interface in Rx mode (typical curve)
Input Impedance OutputImpedance Rx mode
500 480 460 440 420 400 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10000. 0
Impedance [Ohm]
f = 72 kHz |Z| = 280 f
= 28 kHz |Z| = 22.5
10 0 0.0
10 0 00. 0
Freq [Hz]
5.2
5.2.1
Conducted disturbances
Conducted emissions
The EN50065-1 standard describes the test setup and procedures for testing conducted emissions. The conducted emissions measurements have been taken with 220 Vac mains voltage. The test pattern consists of a continuous transmission of a fixed tone at a frequency of 70.8 kHz (72 kHz center frequency minus half the FSK frequency deviation, in this case 2400 Hz)
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Board description
AN2451
which corresponds to a symbol "1". The output signal measured at the CISPR Artificial Network has a value of 120 dBuVRMS which means a signal of 2 VRMS on the mains output. The spectrum analyzer performs a peak measurement instead of a quasi-peak measurement, as specified by EN50065-1. For continuous sinusoidal signals the two types of measurement give the same result. Figure 18. Conducted emissions test setup
Figure 19 shows the results for the output spectrum measurement. The EN50065-1 disturbance limits mask (traced in red) may be compared to the typical output spectrum of the ST7540 reference design board. Figure 19. Output spectrum (typical) at 72 kHz, 2400 baud, deviation 1, fixed transmitted tone = "1", mains 220 Vac
125.0 120.0 115.0 110.0 105.0 100.0 95.0
f1=70.8 kHz |S|=120 dBuV 72kHz spectrum EN50065-1
Output Level [dBuV]
90.0 85.0 80.0 75.0 70.0 65.0 60.0 55.0 50.0 45.0 40.0 35.0 30.0 25.0 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08
2f1=141.6 kHz |S|=56 dBuV 3f1=212.4 kHz |S|=58 dBuV
Freq [Hz]
5.2.2
Noise immunity
The tests on immunity against white noise and narrow-band conducted interferences are based on two ST7540 reference design boards performing a simplex (unidirectional) communication. The first board transmits a given bit sequence, while the receiving board
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AN2451
Board description passes the received bit stream to a BER tester software on a PC, which evaluates the percentage of correctly received bits. The noise (white noise or sinusoidal interferer) is produced by a waveform generator and injected into the artificial network through an AC coupling circuit. Figure 20 shows the test environment used to perform noise immunity tests. Figure 20. Narrow-band conducted interference test setup
PC with Demo SW ST7540
ST7540 Board STIMULUS
ST7540 Board Under Test
PC with BER Tester SW
Spectrum Analyzer AGILENT 4395A
Coupling Circuit
Table 6 reports the parameters for the test conditions settings. The received signal and noise levels are measured at the mains connector of the board under test. The 3 kHz resolution bandwidth chosen for the Spectrum Analyzer allows measurement of the actual signal and noise levels as seen by the receiving ST7540 internal circuitry, programmed for 2400 baud. Table 6. Noise immunity test settings
Parameter Received signal Frequency Baud rate Deviation Detection method Detection time Sensitivity Input filter Transmitted sequence S.A. resolution BW Value 86 dBuVrms 72 kHz 2400 1 Carrier with conditioning 3 ms High Off AACC h 3 kHz
Figure 21 represents the BER vs. SNR curve in the presence of white noise. It may be noted that a BER of 10-3 corresponds to a SNR around 12 dB, as expected from a nonideal FSK demodulator.
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Board description Figure 21. Measured BER vs. SNR curve (typical), white noise
BER vs. Signal to Noise Ratio
1.00E-01 S/N @ CISPR S/N @ Rx_IN 1.00E-02
AN2451
1.00E-03
B ER
1.00E-04 1.00E-05 1.00E-06 6. 0 7. 0 8. 0 9.0 10. 0 11. 0 12. 0 13.0 14.0 15.0 16.0 17.0 18.0
S/N
For narrow-band interference tests, two types of interfering noise have been used: a pure sinusoidal tone and an amplitude-modulated signal (modulating signal 1 kHz, modulation depth 80%). In both cases, the amplitude of the noise signal (of the carrier, for modulated signal) has been decreased until the measured BER was lower than 10-3 (one error every 1000 transmitted bits). Figure 22 shows SNR vs. frequency curves for both a pure sinusoidal and an AM modulated interferer. Figure 22. SNR vs. frequency curve (typical) at BER = 10-3
15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 30 40 50 60 70 80 90 100 110 120
No modulation AM 1kHz 80%
SNR [dB]
frequency [kHz]
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AN2451
Board description
5.3
Thermal design
All heat dissipation is based on the heat exchange between the ST7540 IC, the PCB and the surrounding environment. A large PCB copper area under the device is recommended to make an easier heat transfer from the ST7540 to the environment. The metallic slug under the device (exposed pad of HTSSOP28 package) must be properly soldered to the copper area on the PCB top side, as recommended in the datasheet. The large ground layer on the bottom side of the board must be connected to the top side layer through multiple via holes. In the case of ST7540 reference design, an area of about 0.2 cm2 is put on the PCB top side for exposed pad soldering, while ground layer dissipating area on the bottom side is nearly 1.5 cm2. Figure 23. PCB copper dissipating area for ST7540 reference design board
Top layer Bottom layer
Copper area
Soldering area
Multiple Via Holes
Large GND layer
Even if the ST7540 features a built-in thermal shutdown circuitry which turns off the power amplifier (PA) when the die temperature (TJ) exceeds 170 C. It is however recommended not to exceed 125 C during normal operating conditions to ensure the functionality of the IC. The relationship between junction temperature TJ and power dissipation during transmission PD is described by the following formula: Equation 7
T J ( t T X, d ) = T A P D · J A ( t T X, d )
where TA is the ambient temperature (from -45 to +85 C) and JA is the junction to ambient thermal impedance of the ST7540 IC, which is related to the length of the transmission (tTX) and to the duty cycle d = tPKT / (tPKT + tIDLE), assuming a packet-fragmented transmission as illustrated by Figure 24.
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Board description Figure 24. Packet-fragmented transmission
Transmission in progress Idle state
AN2451
tPKT
t IDLE tTX
When soldered to a proper copper area on the PCB as explained above, the IC is characterized by a steady-state thermal impedance of about 35 C/W. The transient of the thermal impedance JA can be estimated by simulating a 6-cell equivalent model, as shown in Figure 25. The simulated curve vs. the transmission duration and the duty cycle is also given. It can be noticed that the transient of JA takes several hundreds of seconds, after which the static value of 35 C/W is reached. Figure 25. Equivalent model of the thermal impedance JA of the HTSSOP28 package with exposed pad
40
R C
C/W W*s/C
JA(tTX, d) ( [C/W] j)
R1 0.4
R2 1
R3 8
30
C1 5e-4
C2 6e-3 R5 9.5
C3 17e-3 R6 6
20
PD
R4 11
10
TA
C4 0.09 C5 0.8 C6 15
0 1E-2 1E-1 1 1E1
d = 100% d = 75% d = 50% d = 25%
1E2 1E3
tTX [s]
This means that during the transient phase (i.e. if the transmission time tTX is some seconds or even less) the IC is able to dissipate power that is well above the one sustainable at steady state. For this reason, a complete thermal analysis requires taking into account the characteristics of the transmission, i.e. duty cycle and duration, determining the value reached by the thermal impedance and then the allowed power dissipation. Actual dissipated power PD can be calculated as: Equation 8
PD = PI N PO U T
where PIN=VCC*ICC and POUT=VOUT rms * IOUT rms. Note that power consumption by receiving circuitry and linear regulators is considered negligible for thermal analysis purposes. The relationship between current absorption from the power supply (ICC) and PA output current to the load (IOUT) is shown in Figure 26. The value of Vin can be deduced from the load regulation curve of the SMPS, given in Figure 37.
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AN2451
Board description Figure 26. Output current vs. supply current typical curve for ST7540 in Tx mode
The transmission output level VOUT rms of 2 V and the current limit IOUT rms(LIMIT) of 500 mA, fixed for the ST7540 reference design, correspond to a maximum output power POUT of 1 W over a 4 load. In these conditions, the required dissipation results equal: Equation 9
P D ( L I M I T ) = P I N ( L I M I T ) P O U T ( L I M I T ) ( 11.7 V · 0.25 A ) ( 2 V · 0.5 A ) 2 W
Figure 27 shows the curve of PD vs. the load impedance modulus according to the VOUT rms and IOUT rms(LIMIT) set for the ST7540 reference design. Figure 27. Dissipated power vs. load impedance modulus typical curve for ST7540 reference design board
Referring to the relationship between dissipated power and temperature, it can be proven that in a continuous transmission, i.e. with JA at its its steady-state value of 35 C/W, a 2 W dissipation can be sustained in safe conditions if the ambient temperature remains below 55 C. Instead, supposing a transmission time tTX of 1 s and a duty cycle d of 50%, according to the graph of Figure 25 the JA would be 15 C/W only. In this case a power dissipation of 2.7 W (corresponding to a 1 load) is allowed over the entire ambient temperature range of the ST7540.
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Board description
AN2451
5.4
Oscillator section
The ST7540 crystal oscillator circuitry is based on a MOS amplifier working in inverter configuration. This circuitry requires a crystal with a maximum load capacitance of 16 pF and a maximum ESR of 40 . It is very important to keep the crystal oscillator and the load capacitors as close as possible to the device. The resonant circuit should be far away from noise sources such as:
Power supply circuitry Burst and surge protections Mains coupling circuits Any PCB track or via carrying a signal.
To properly shield and separate the oscillator section from the rest of the board, it is recommended to use a ground plane on both sides of the PCB, filling all the area below the crystal oscillator and its load capacitors. No tracks or vias should cross the ground plane except for the crystal connections. It is also recommended to use a large clearance on the oscillator related tracks, to minimize humidity problems (see Figure 28). Connecting the case to ground is also a good practice to reduce the effect of radiated signals on the oscillator. Figure 28. A recommended oscillator section layout for noise shielding
5.5
Surge and burst protection
The specific structure of the coupling interface circuit of the application is a weak point against high voltage disturbances that can come from the external environment. In fact an efficient coupling circuit with low insertion losses consequently allows a very low impedance path from the mains to the powerline interface of the device. For this reason it is recommended to add some specific protection devices on the mains coupling path, to prevent high energy disturbances coming from the mains from damaging the internal circuitry of the ST7540.
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AN2451
Board description The possible environments for this kind of application can be both indoor and outdoor: residential, commercial and light-industrial locations. To verify the immunity of the system to environmental electrical phenomena, a series of immunity specification standards and tests must be applied to the powerline application. The requirements for ac-connected ports, fixed by the EN50065-2-3 document (part 7immunity specifications), include EN610000-4-4 (electric fast transients), EN610000-4-5 (surges), EN610000-4-6 (RF out-of-band disturbances), EN610000-4-11 (voltage dips). In particular, surge tests are specified as both common and differential modes at level +/- 4 kV, with pulse shape 1.2 x 50 s. Fast transient burst tests are specified at level +/- 2 kV, with pulse shape 5 x 50 ns and pulse frequency 5 kHz. Figure 29, Figure 30 and Figure 31 illustrate the protection criteria implemented in the ST7540 reference design. Figure 29 and Figure 30 show the protection against common mode disturbances. The BAV99 diodes are intended to prevent the voltage on PA_OUT and Rx_IN lines from going above the supply rail (Vcc for PA_OUT and VDC for Rx_IN) or below ground, with a tolerance of nearly 0.7 V. Figure 31 describes the protection intervention in case of differential mode disturbances. A differential voltage higher than 12 V is shorted by the bidirectional power transil, which is the most robust protection and also the one capable to absorb most of the energy of incoming disturbances. Figure 29. Common mode disturbances protection - positive disturbance
Vcc 2 3 D8 BAV99 C22 10uF A 1 T2 R17 750 4 5 P VDC 2 L6 220 uH C26 22 nF 8 D9 SMBJ12CA B 1
PA_OUT
L5 47 uH
C23 100nF X2 N
Rx_IN
C27 10 nF
D10 BAV99
3
1
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Board description Figure 30. Common mode disturbances protection - negative disturbance
Vcc
2
AN2451
3
D8 BAV99
PA_OUT
C22 10uF A 1 T2 R17 750 4 5 8 B
1
L5 47 uH
C23 100nF X2 N
Rx_IN
C27 10 nF
D9 SMBJ12CA
P VDC
2
L6 220 uH
C26 22 nF
D10 BAV99
3
Figure 31. Differential mode disturbances protection
Vcc 2 3 D8 BAV99 C22 10uF A 1 T2 R17 750 4 5 P VDC 2 L6 220 uH C26 22 nF 8 D9 SMBJ12CA B 1
1
PA_OUT
L5 47 uH
C23 100nF X2 N
Rx_IN
C27 10 nF
D10 BAV99
3
Figure 29 shows the protection against common mode positive disturbances. D8 protection diodes are able to quickly absorb fast transient positive disturbances higher than their 14 V
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1
AN2451
Board description clamping voltage. D10 discharges to the Vcc supply any disturbance higher than the supply voltage plus a diode forward voltage. Figure 30 indicates how the same D8 double-diode protection is able to clamp a common mode negative disturbance to ground, given that its level is lower than the forward voltage of the two diodes. Figure 31 describes the protection intervention in case of differential mode disturbances. A differential voltage higher than 6.8 V is shorted by the D9 bidirectional transil. D9 is the most robust protection and also the one that is able to absorb most of the energy of any incoming disturbance.
5.6
50-pin connector for the EVALCOMMBOARD
Figure 32. Scheme of the connector for the EVALCOMMBOARD
VD C VD D F _F OR C E 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 CN2 Vc c 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Vc c VD D F Vdd
AN ALOG_I N B_I D _PLM1 GN D B_I D _PLM0 GN D R STO U AR T/ SPI WD BU / TH ER M VD C
C D / PD R EG_D ATA RxD R x / Tx C LR / T Tx D
C ON 50A
The ST7540 transceiver requires external digital control to communicate. This is done through an ST7 microcontroller which is accommodated on the EVALCOMMBOARD (see Chapter 4 on page 11). Communication with the ST7 microcontroller involves several signals, which can be gathered into 3 groups: Digital signals, Analog signals and Power connections. The signals for each group are listed in Table 8, Table 9 and Table 10. Besides the ST7540 input and output signals, the link to the EVALCOMMBOARD includes:
A 2-bit (B_ID_PLM_1 and B_ID_PLM_0) Board Identification Code, which identifies the hosted powerline transceiver. The microcontroller is able to recognize the ST7540 reference design board through a "10" binary configuration of this code. An Analog Input (ANALOG_IN), which is a line intended to implement a Received Signal Strength Indicator (a peak meter used to give an Rx signal level estimation). A VDDF_FORCE signal, which forces the microcontroller to refer digital interface levels to the VDDF (VDD) supply voltage provided by the ST7540 reference design board. This way both the modem and the microcontroller "talk" on the same digital levels.
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Board description
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Table 7.
50-pin connector digital signals
Signal name B_ID_PLM_1 B_ID_PLM_0 CD/PD REG_DATA RxD RSTO RxTx UART/SPI CLR/T WD BU/THERM TxD Description Board ID for PLM applications (MSB) Board ID for PLM applications (LSB) Carrier or preamble detected signal Data communication or register access Serial data output Reset output Receiving or transmission selection Host Interface selection Serial data clock Watchdog timer reset - Rx mode: band-in-use detection signal - Tx mode: thermal event signal Serial data input Generated by PLC Board (VDC) PLC Board (GND) Modem C Modem Modem C C Modem C Modem C
Pin number 20 28 35 37 39 40 41 44 45 46 48 49
Table 8.
50-pin connector analog signals
Signal name ANALOG_IN Description Analog input (for C processing) Generated by -
Pin number 8
Table 9.
50-pin connector power connections
Signal name PLM_10 V VDD VDDF_Force VDDF GND Description 12 V power supply 3.3 V / 5 V power supply Force microcontroller digital level to VDDF Digital power supply Ground Generated by PLC Board Modem PLC Board (VDC) Modem (VDD) -
Pin number 2 4 5 6 22,34
5.7
Power supply
The ST7540 reference design includes a specifically designed Switching Mode Power Supply (SMPS) circuit, based on the ST VIPer12AS-E device. The VIPer12AS-E is a smart power device with a current mode PWM controller, a startup circuit and protections integrated in a monolithic chip using VIPower M0 technology. It includes a 27 Mosfet with 730 V breakdown voltage and a 400 mA peak drain current limitation. The switching frequency is internally fixed at 60 kHz, in order to provide a good compromise between EMI performances and magnetic parts dimensioning.
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AN2451 The internal control circuit offers the following benefits:
Board description
large input voltage range on VDD pin accommodates changes in supply voltage automatic burst mode in low-load condition overload and short-circuit protection in hiccup mode
The power supply is designed in isolated flyback configuration. Secondary regulation, implemented through an optocoupler and a Zener diode, takes the requested output tolerance for the specified application into account. The main specifications are listed in Table 10. Table 10. SMPS specifications
Parameter Input voltage range, Vin Output voltage, VOUT Peak output current, IOUT(MAX) Value 85-265 Vac 12 V10% 500 mA
In the input stage, an EMI filter is implemented (C1-L2 plus C3-L3-C2) for both differential and common mode noise, in order to fit the requested standard. The blocking diode D2 and the clamping network (R2-C4) clamp the peak of the leakage inductance voltage spike, assuring reliable operation of the VIPer12AS-E. D2 must be very fast recovery and very fast turn-on to avoid additional drain overvoltage. The clamp capacitor C4 must be low-loss (with polypropylene or polystyrene film dielectric) to reduce power dissipation and prevent overheating, since it is charged with high peak currents by the energy stored in the leakage inductance. A Leading Edge Blanking (LEB) circuit for leakage inductance spikes filtering has also been implemented (Q1 - C5 - R3). It blanks the spike appearing at the leading edges of the voltage generated by the self-supply winding, greatly improving short circuit behavior. The output rectifiers have been selected to take the maximum reverse voltage and the RMS secondary current into account. A STPS1H100 Power Schottky rectifier has been chosen for this purpose. A LC filter has been added on the output (consisting of L4, C9 and C29) in order to filter the high frequency ripple without increasing the output capacitors size or quality. The transformer used for this application has three windings, since one of them is needed to supply the VIPer12AS-E. The primary inductance has been chosen as 2.7 mH and the reflected voltage has been set to 80 V. A layer type has been chosen with EF12.6 or E13/7/4 core. The characteristics are listed in Table 11. Table 11. SMPS transformer specifications
Parameter Core geometry Primary inductance Leakage inductance Value SRW12.6ES or E13/7/4 2.7 mH10% 180 H max
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Board description Table 11. SMPS transformer specifications (continued)
Parameter NP NAUX NSEC Withstanding voltage Value 224 turns 0.1 mm 39 turns 0.1 mm 31 turns 0.2 mm (TEX-E wire) 4 kVRMS
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Some significant waveforms are represented in the following figures. Figure 33 and Figure 34 show typical waveforms in both open-load and full-load conditions. In any SMPS, protection against an output short-circuit is very important. All tests have been done by shorting the SMPS output at maximum input voltage. The results are given in Figure 35. The main parameters are the drain-source voltage (VDS), the output current (IOUT) and the supply voltage (VDD). The output current is an important parameter to be checked during shorts. Although the output current peaks are quite high, the mean value is very low, thus preventing component melting for excessive dissipation. In this way, the output rectifier, transformer windings and PCB traces don't get overstressed. This assures system reliability against long-term shorts. In case of device overheating, the integrated thermal protection stops the device operation until the device temperature falls. The startup phase could be critical for the SMPS. Output overshoot occurs if the circuit is not properly designed. Care must be taken in designing a proper clamp network in order to prevent voltage spikes, due to leakage inductance, from exceeding the breakdown voltage of the device (730 V minimum value). The startup transient is shown in Figure 36. It may be noted that the maximum drain-source voltage doesn't exceed the minimum breakdown voltage BVDSS, with a reasonable safety margin. Finally, load regulation is presented in Figure 37, for different input voltages. With 230Vac, the output voltage ranges from 12.3V to 11.1 V, within the requested tolerance.
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Board description
Figure 33. Typical waveforms at 230 Vac: open Figure 34. Typical waveforms at 230 Vac: full load load
VDD
VDD
IOUT
VDS
VDS
IOUT
Ch1 freq - 9.62 kHz (black) Ch2 mean - 9.90 V (green)
Ch1 freq - 57.71 kHz (black) Ch2 mean - 13.79 V (green) Ch4 max - 503 mA (light blue)
Figure 35. Typical waveforms at 265 Vac: short-circuit
Figure 36. Typical waveforms at 265 Vac: startup
VDS
VDD
IOUT
Ch1 freq - 23.50 Hz (geen) Ch4 max - 2.08 A (light blue) Ch4 meann - 383 mA (light blue)
Ch1 max - 702 V (black) Ch2 mean - 19.72 V (green) Ch4 max - 500 mA (light blue)
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Board description Figure 37. Load regulation
12.5 12.4 12.3 12.2 12.1 12 11.9 11.8 11.7 11.6 11.5 11.4 11.3 11.2 11.1 11 0 100 200 300
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185 V ac 230 V ac 265 V ac
Vout [V]
400
500
Iout [mA]
Figure 38 shows the efficiency vs. output current curve. Minimum efficiency occurs at lowload condition, as expected from any SMPS. This is not an issue for our application, since low efficiency corresponds also to low power consumption and thus to low dissipation. On the other hand, at output current values over 500 mA (full-load condition), both the transformer and the VIPer are forced to operate close to their current limitations and thus the efficiency is reduced. In general, efficiency is affected by the losses which are due to R1 (series input resistor limiting in-rush current) and to the filtering on both the primary and secondary side. Filtering is more important than efficiency because a powerline communication appliance has very restrictive EM disturbance limits and it is also highly sensitive to noise coming from the power supply. Figure 38. SMPS efficiency curve
0. 73 0. 71 0. 69 0. 67 0. 65 0. 63 0. 61 0. 59 0. 57 50 100 150 200 250 300 350 400 450 500
Iout [mA]
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Performance and ping tests
6
Performance and ping tests
Our evaluation system includes a ping test embedded into the ST7540 powerline modem demonstration kit and the FW of the EVALCOMMBOARD. This feature allows the user to perform in-field communication tests and to evaluate reachability of PLC network nodes. A ping session is based on a master board sending a sequence of messages to one or more slave boards. if the messages are correctly received by the slave boards, they are resent one by one to the master. The PC connected to the master keeps statistics of the messages sent and correctly received by the slave boards, thus making it possible to get a numerical evaluation of the reachability of each node corresponding to a slave. Figure 39 represents the ping window of the ST7540 powerline modem demonstration kit for the master node. The main characteristics of this tool are indicated in red. Figure 39. ST7540 powerline modem demonstration kit window for the master board
Number of Slaves (up to 255) Number of Messages
Repetition Control Graphical Statistics
Medium Access Control
Last Message Status
Numerical Statistics
Special controls are included in the ping test:
Repetition control: may be used to improve communication reliability. When repetition control is enabled, a message not responded by a slave is resent up to three times before sending a new message Medium access control: defines what type of medium access has to be used. Choices are "none", "BU" or "PD". In the last two cases, messages are sent to the slave only if the BU or CD/PD lines of the ST7540 modem are not active. If the PD setting is selected, the content of the ST7540 internal control register is changed to select "Preamble" as the detection method.
For further details about ST7540 powerline modem demonstration kit, please refer to the user manual UM0239 "ST7540 power line modem demo kit graphical user interface".
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Application ideas
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7
7.1
Application ideas
Three-phase architecture
Figure 40. Scheme of principle for three-phase architecture
Controller
Enable Ph1 Enable Ph2 Enable Ph3
Ph1 Ph2 Ph3
ST7540
Neutral Rx and TX Filters
Rx_IN PA_OUT
The ST7540 modem can be used to communicate on a three-phase network. A microcontroller should switch communication between the three phases, since the modem can transmit/receive only on one phase at a time. In Figure 40, the microcontroller uses three output lines as Enable signals for three switches (typically opto-switches), one for each phase line. For the ST7540, there is no difference with respect to single-phase communication.
7.2
Zero crossing detector
Often, in AMR (Automatic Meter Reading) applications, it is necessary to know which phase each meter is placed on. This information is mainly useful at system level in order to check for unexpected losses on the distribution line due to failures or energy theft. Since the three phases on the mains are sinusoidal waveforms with a phase shift of 120 from each other (equal to 6.67 ms at 50 Hz / 5.5 ms at 60 Hz), the simplest way to associate the meter to its correct phase is to synchronize the transmission to the phase itself. To do that, the meter should always start its transmission synchronously with zero voltage transitions on its phase and the concentrator should measure the delay between the beginning of the incoming frame and the transition on its reference phase. The act of detecting the zero voltage transitions on the mains phase is called zero crossing detection. Figure 41 and Figure 42 show two possible zero crossing detector circuit implementations. N and P mean neutral and phase lines respectively at the meter/concentrator side, while ZC_OUT is a digital output to the application microcontroller.
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Application ideas Par ticular attention should be paid to current rating (see solution in Figure 42) The maximum allowable current for 1W dissipation, sustainable by two ½ W resistors in a series, is 4.5 mA rms = 6.4 mA peak. Such a current flowing into the LED of the optocoupler can minimize the delay between the actual zero crossing of the mains voltage and the edge of the ZC_OUT signal, if the optocoupler has been chosen to have an activation current IF about 10 times smaller than the peak current. Figure 43 shows the behavior of the ZC_OUT digital signal versus the AC Mains Input for both circuits.
Warning:
The circuit in Figure 41 is only applicable to a nonisolated board topology. It is not possible to implement it directly on the ST7540 reference design.
Figure 41. Schematic of a zero crossing detection circuit for nonisolated coupling
VD C
R1 N
Q1 BS170F / SOT Z C _OU T
470k R2 220k D1
3
R3 450 1
BZ X79C 12A
P
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Application ideas
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Figure 42. Schematic of a zero crossing detection circuit for isolated coupling
VD C
R 1A N
R 1B
If<1m A
2 5 I SO1 1 4 D1 1N 4148 OPTOC OU PLER
25k 1/2W
25k 1/2W
P Z C _OU T
R2 100k
Figure 43. ZC_OUT vs. AC mains waveforms
AC Mains
5V
ZC_ouUT ZC O t
7.3
Received Signal Strength Indicator (RSSI)
In many application fields, measuring the strength of the incoming signal is useful to:
Evaluate the SNR (Signal to Noise Ratio) at the node Choose the best routing through the network (if repeaters are allowed)
One possible implementation for the Received Signal Strength Indicator (RSSI) is the one depicted in Figure 44, where a Peak Detector is used to measure the amplitude of the incoming signal.
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AN2451 Figure 44. Peak detector electrical schematic
5V
Application ideas
8 Rx_IN 3 2 + 4 R1 100k R2 18k
R4 4.7k U1A 1 LM393 R3 1N4148 C1 100n D1 DC_OUT
82k
The schematic above is based on a simple diode-capacitor (D1-C1) circuit improved with an LM393 comparator so that:
The comparator eliminates the diode reverse voltage. The feedback network (R3/R2) introduces a gain of 4 to improve performance against low amplitude signals.
In the end this circuit gives, on DC_OUT line, a DC voltage proportional to the AC peak-topeak level at the input. Figure 45 shows the measured behavior of this circuit with a given pure sinusoidal waveform at the input. The DC_OUT signal should be converted through an integrated A/D converter by the application microcontroller. Figure 45. Measured DC_OUT Vs. AC_IN peak detector response
3000
2500
2000 DC_OUT [mV]
1500
1000
500
0 0 200 400 600 AC_I N [mVpp] 800 1000 1200
7.4
Nonisolated coupling
A possible alternative solution for line coupling is a nonisolated circuit. An example is shown in Figure 46, in which the transformer T2 has been substituted with the shunt inductor L7. The value of the inductor has been chosen to give about 100 dB rejection to the mains voltage through a C23-L7 high pass filter. Advantages arising from nonisolated topologies
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Application ideas
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mainly include cost optimization, eliminating the need for isolation components, and circuit simplicity. Figure 46. Example schematic for nonisolated solution
Vcc 2 3 D8 BAV99 C22 10uF 1
PA_OUT
L5 47 uH
C23 100nF N
Rx_IN
C27 10 nF
R17 750
L7 1 mH
D9 SMBJ12CA
P VDC 2 L6 220 uH C26 22 nF
D10 BAV99
3
7.5
DC powerline applications
The ST7540 reference design can be adapted to communicate over a DC power line. In this case, the schematic of Figure 46 has to be referred to as line coupling, with two modifications: L7 can be removed and the C23 capacitor can be substituted with a lower voltage ceramic component. A DC-DC converter will substitute the ac-dc SMPS. For example, the L5970 DC-DC stepdown switching regulator can be used in case of 24 V bus to obtain the 12 V supply for the ST7540 device.
7.6
110 and 132.5 kHz coupling circuit
In this paragraph application circuits for CENELEC band B and C are provided. The 110 and 132.5 kHz channels of the ST7540 transceiver are suitable for home automation applications and in general for applications not subject to the European AMR regulations. Figure 47 and Figure 48 show the schematics for the line coupling interface tuned respectively to the 110 and 132.5 kHz channels.
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1
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C 21 120pF
C 31 22 pF Vc c 2 VD C R 12 1k 3 D8 BAV99 R 20 25k R 19 2k PA_I N PA_OU T R9 4k 7 C 22 10uF A 1 T2 R 17 750 4 5 8 1 R 14 1k 8
C 30 15 pF
Tx _OU T
L5 47 uH B
C 23 47nF X2 N
PA
C 19 100nF PA_I N + R 18 18k R 10 12k C 33 120 pF R x _I N C 32 390 pF C 27 10 nF
D9 SMBJ 12C A
P VD C 2 L6 220 uH C 26 10 nF
Figure 47. Line coupling interface for 110 kHz channel
D 10 BAV99
3
1
Application ideas
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VD C R 12 1k 3 D8 BAV99 R 14 1k 8
Tx _OU T
R 19 2k 5 PA_I N PA_OU T
R9 4k 7
C 22 10uF A 1 T2 R 17 750 4 5 8 B
1
R 20 25k
2
2
1
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C 21 100pF C 31 22 pF Vc c C 30 15 pF L5 33 uH C 23 47nF X2 N
Application ideas
PA
PA_I N + C 32 270 pF R 10 13k C 33 100 pF R x _I N C 27 10 nF
C 19 100nF
R 18 18k
D9 SMBJ 12C A
P VD C L6 220 uH C 26 6. 8 nF
Figure 48. Line coupling interface for 132.5 kHz channel
D 10 BAV99
3
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Troubleshooting
8
Troubleshooting
In this section the most frequently asked questions are described. 1. Problem: the ST7540 reference design board does not work at all. a) b) c) 2. Check that the AC mains supply cable is well connected to CN1. Check if the green LED D6 is on. Check the voltage on the Vcc test pad. The value must be about 12 V. What to check:
Problem: the ST7540 reference design board is not responding. a) b) c) d) Check the VDC voltage. The value must be about 5 V. In a noisy environment, spurious voltage spikes could compromise the internal linear regulator startup. If Vdd is not externally connected to the VDC line, verify the Vdd voltage. The value must be about 3.3 V. Check if the MCLK selected frequency is present. Check the connection between the reference design board and the EVALCOMMBOARD and the connection between the EVALCOMMBOARD and the PC.
What to check:
3.
Problem: the ST7540 reference design board does not transmit. a) Check the voltage on the PA_OUT test pad with the oscilloscope ground probe connected to the SVss signal ground. The programmed carrier frequency must be present on the PA_OUT line. Check there is no short-circuit impedance on the mains at the transmitting frequency. Check the CL voltage. It fixes the current limiting threshold. It has to be lower than 1.9 V, otherwise the IC is put in current-limit mode.
What to check:
b) c)
If the current-limit mode is forced on the transceiver, modify the value of the R6 feedback resistor to exit from limitation according to the actual load forced by the mains network. 4. Problem: the ST7540 reference design board transmits only for a short time. a) b) Check the transmission timeout setting. It has to be disabled for continuous transmission. Check if continuous or single sequence transmission is selected in the Tx panel of the ST7540 powerline modem demonstration kit window. Select continuous mode to be able to force a lasting transmission. Check there is no short-circuit impedance on the mains at the selected transmitting channel. What to check:
c) 5.
Problem: the ST7540 reference design board does not receive.
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Troubleshooting What to check: a) b) Check if the carrier frequency is present on the RAI pin voltage with the oscilloscope ground probe connected to the DVss signal ground pin.
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Check that the transmitting frequency matches the carrier frequency selected through the control register panel of the ST7540 powerline modem demonstration kit window. Check the preamble detection setting on the control register panel of the ST7540 powerline modem demonstration kit window. Check if data are present on the RxD pin.
c) d) 6. Note:
Problem: during a ping test or a transmission test, the ST7540 reference design board shows high bit error rate.
This point refers to a half-duplex communication involving two ST7540 reference design boards communicating with each other. What to check: a) b) c) d) Check that both reference design boards are programmed to transmit/receive on the same carrier frequency. Check preamble detection setting on the control register panel of the ST7540 powerline modem demonstration kit window. Check if the carrier frequency is present on the RAI pin voltage with the oscilloscope ground probe connected to the DVss signal ground pin. Check if data are present on the RxD pin.
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Board layout
Appendix A
Board layout
Figure 49. PCB layout - component placing
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Board layout Figure 50. PCB layout - top view
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Board layout
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List of normative references
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9
List of normative references
EN50065: Signaling on low voltage electrical installations in the frequency range 3 kHz to 148.5 kHz.
Par t 1: General requirements, frequency bands and electromagnetic disturbances Par t 2-1: Immunity requirements Par t 4-2: Low voltage decoupling filters - safety requirements Par t 7: Equipment impedance
10
Revision history
Table 12.
Date 10-Jan-2007
Document revision history
Revision 1 First issue Figure 2, 7, 8, 9, 23, 46, 49, 50 and 51 modified Figure 47 inserted Table 3, 4 and 5 modified Section 7.5 and 7.6 inserted Equation 2 modified Changes
28-Jan-2008
2
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