AN2466 Application note
STMPE801 - Hardware Interface guide
Introduction
STMPE801 is an eight-bit port expander that can be interfaced to the main digital ASIC or processor via the two-line bidirectional I2C bus. The digital engines in mobile multimedia platforms usually come with a limited number of I/Os. The port expander ICs can be used to increase the number of I/Os or control signals in such applications. STMPE801 can be used in advanced digital platforms such as:
Por table media players Game consoles Mobile phones Smar t phones etc.
This application note explains the setup and hardware interfacing of the device to the main processor.
March 2007
Rev 1
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Contents
AN2466
Contents
1 2 STMPE801 Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description of STMPE801 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 2.5 Power Supply - VCC and VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1 I2C General call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset pin (RESET_N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interrupt pin (INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5.1 2.5.2 2.5.3 Configuring GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 GPIO Level shifting feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 GPIO-Hot Key feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 2.7 2.8
Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power saving mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STMPE801 Device features
1
STMPE801 Device features
Figure 1. Concept of GPIO Port Expander
VCC
CLOCK DATA
VIO
GPIO 0 GPIO 1 GPIO 2 GPIO 3 Hotkey Chip Enable Temperature Sensor Control Signal/Ext.Interrupt
Processor
ADDRESS
STMPE801
INT
GPIO 4 GPIO 5 GPIO 6
RST_N
GPIO 7
LED BANK
GND
Low CPU utilization (Interrupts available and so no Polling!) Configurable Hotkey Detection on each GPIO Flexibility in configuration of each of the eight GPIOs Simpler communication with CPU (just two I2C lines) Low power consumption with ultra low standby current (< 1 A) IO and core voltages from 1.65 V up to 3.6 V Interrupt output (open drain) pin No external clock input required Small package QFN16 - 16 pins 1.8 mm x 2.6 mm, making it optimal for use in portable application like mobile phones with critical space constraints.
The STMPE801 offers great flexibility as each I/O can be independently configured as input or output. The eight GPIOs can be connected externally to different modules like LEDs, temperature sensors, chip selects for other devices, or as interrupt inputs from other devices. This device has been designed with very low quiescent current in standby mode and includes a Hot Key detection for each I/O to optimize the power consumption of the IC.
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Pin description of STMPE801 Figure 2. Block diagram of STMPE801
AN2466
GPIO Controller
GPIO 0-7
GPIO 0-7
VIO ADDRESS CLOCK DATA INT
IC Interface
P P
2
POR
RESET_N
VCC
GND
2
Pin description of STMPE801
The table below gives a list of all the pins on STMPE801. Table 1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14
STMPE801 Pin description
Name INT Reset_N CLOCK ADDRESS DATA VCC VIO GND GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 Type O I A I A IO IO IO IO IO IO Description Interrupt output (open drain) External reset input, active LOW I2C Serial clock line Digital Input for I2C slave address (either High or Low) I2C Serial data line Supply voltage for I2C block Supply voltage for GPIO controller (Note: VIO must always be VCC) GND GPIO GPIO GPIO GPIO GPIO GPIO
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Pin 15 16
Pin description of STMPE801 STMPE801 Pin description (continued)
Name GPIO_6 GPIO_7 Type IO IO GPIO GPIO Description
2.1
Power Supply - VCC and VIO
The STMPE801 device operates on two different power supplies, VCC and VIO. Both VCC and VIO can function in the range of 1.65 V to 3.6 V. This enables a variety of devices to interface directly to the device without a level translator block. Proper decoupling capacitors should be used to filter out the Power supply noise. There are some critical points to be noted to ensure proper functioning of the device as listed below: VCC pin supplies the I2C lines and ADDRESS pin. All other pins are connected to the VIO supply. At any time, to conserve power, the VCC can be turned off if there is no I2C activity but at no point, should the VIO be turned off while the VCC is ON. The VIO should always be VCC
2.2
I2C Interface
The port expander STMPE801 can be controlled with just the two I2C lines. All internal registers can be accessed through this I2C interface. The I2C interface features are as given below: I2C Slave device Operates on the VCC supply (1.65 V to 3.6 V) Compliant to Philip I2C specification version 2.1 Suppor ts standard (up to 100kbps) and fast (up to 400kbps) modes. 7-bit addressing mode supported. General call Up to two STMPE801 devices can be connected on the same I2C bus
The slave address is selected by the state of the ADDRESS pin. The address is read every time the I2C transaction occurs. This implies the slave address of the device can be changed on the fly without any need for latching the address into the device at reset.
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Pin description of STMPE801 Figure 3. STMPE801 Slave address selection
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GND VCC SCLK SDAT SCLK SDAT
STMPE801
ADDR0
The I2C Read/ W r i t e is done byte by byte. The R/ W bit is added as the LSB to the 7-bit slave address to make up one byte to be sent through the I2C interface from the master. Table 2. Valid I2C Slave address
ADDRESS pin 0 1 7-bit Slave Address 41h (10 0 01b) 44h (1000100b) 8-bit format to be used (including R/ W bit in LSB) 82h 88h
Figure 4.
I2C Read/write transaction
Once the slave address is configured and responding correctly, the internal registers can be accessed through I2C Interface. The SCLK and SDATA are open drain pins and should be provided with a pull-up resistor to VCC. The VCC can be selected based on the operating voltage of the I2C host, for example as either 1.8 V or 3.3 V without any need for an intermediate level translator stage.
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AN2466 Figure 5. I2C pin structure
Pin description of STMPE801
INPUT BUFFER
INTERNAL BLOCKS
Open Drain Buffer
PAD
ESD DIODE
Figure 6.
I2C line with external pull-up resistors
2.2.1
I2C General call
STMPE801 supports I2C general call based on the following table. When a general call address of 0x00 with R/ W = 0 is sent, the device responds with an acknowledgement and performs the instruction given by the second byte. The device does not give ACK for any second byte other than the valid second bytes listed in Table 3. Table 3. I2C General call
Definition Slave device should reset and latch in the slave address Slave device should latch in the slave address but without reset. Not allowed as second byte.
Second byte 0x06 0x04 0x0
2.3
Reset pin (RESET_N)
The Reset pin is an active low input. It should be tied HIGH to VIO supply in order to start normal operation of the device. Apart from the RESET_N pin, the device can also be reset through the "Soft_Reset" bit in the SYSCON register. Writing a '1' to Bit 7 resets the device and after reset, the bit is cleared to '0' by the Hardware.
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Pin description of STMPE801
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2.4
Interrupt pin (INT)
The interrupt pin is an open drain output pin with a structure similar to the SCL,SDA pins. The INT output should be provided with a suitable pull-up resistor to VIO supply. The interrupt output polarity can be configured as active low or active high by setting Bit 0 of the SYSCON register. The interrupt output should be enabled by writing a '1' to Bit 2 in the SYSCON. Even if individual GPIO interrupts are enabled, no interrupt will be generated if the global INT_Enable bit is not set in the SYSCON. The Interrupt is cleared by reading the ISGPIOR register (0x09). At reset, the interrupt output is disabled and the polarity is active LOW. Table 4.
Bit 7 6 5 4 3 2 1 0
SYSCON register
Reset value 0 0 0 0 0 0 0 0 INTPolarity `1' for active HI, `0' for active LOW INT_Enable `1' to enable, `0' to disable INT output Name SoftReset I2C_SHDN Description Writing `1' to this bit causes a soft reset of the device Writing `1' to this bit shuts down the I2C block on the next valid I2C clock.
2.5
GPIO Pins
All 8 GPIO lines are configured as inputs at power-on/reset and are independent of each other and can be individually programmed as input or output. Unused GPIOs should be configured as outputs to minimize power consumption. Figure 7. GPIO pin structure
VIO
P-BUFFER
INTERNAL BLOCKS
N-BUFFER
PAD
ESD DIODE
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Pin description of STMPE801
2.5.1
Configuring GPIO registers
The GPIO pin direction can be selected as input or output by writing into the GPDR register (0x12). Table 5. GPIO Direction register
GPDR Bit 7 IO_7 Reset value Bits 7:0 0 Name GPIO[x] 6 IO_6 0 5 IO_5 0 4 IO_4 0 3 IO_3 0 Description `0': The corresponding GPIO pin is set to Input. `1': The corresponding GPIO pin is set to Output. 2 IO_2 0 1 IO_1 0 0 IO_0 0
The GPIO output state can be set high or low by writing into the corresponding bit in the GPSR register (0x11). Table 6. GPIO State register
GPSR Bit 7 IO_7 Reset value Bits 7:0 0 Name GPIO[x] 6 IO_6 0 5 IO_5 0 4 IO_4 0 3 IO_3 0 Description `0': The corresponding GPIO output is set LOW `1': The corresponding GPIO output is set HIGH 2 IO_2 0 1 IO_1 0 0 IO_0 0
If the GPIO is configured as an input, the pin state is monitored by reading the corresponding bit in the GPMR register (0x10). Table 7. GPIO Monitor register
GPMR Bit 7 IO_7 Reset value Bits 7:0 0 Name GPIO[x] 6 IO_6 0 5 IO_5 0 4 IO_4 0 3 IO_3 0 Description Reading `0': The corresponding GPIO input state is LOW Reading `1': The corresponding GPIO input state is HIGH 2 IO_2 0 1 IO_1 0 0 IO_0 0
Each GPIO can be individually programmed to generate an interrupt on change of state.
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Pin description of STMPE801
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2.5.2
GPIO Level shifting feature
In STMPE801, all GPIO pins are connected to the VIO supply. At reset, all GPIO pins are LOW and if configured as output, the GPIO pins reach HIGH state only if a '1' is written to the corresponding bit in the GPSR register. The HIGH state corresponds to the VIO supply level. This provides a useful level shifting feature without using an explicit level translator device. For example, low-voltage processors (Example: 1.8V base-band processors) can directly control interfacing modules of much higher operating voltages (example 3.6 V drivers) simply by setting the VIO supply of STMPE801 to the required voltage and setting the GPIO High/Low by writing into the GPIO registers through the I2C interface. Figure 8. GPIO Level shifting feature
VCC = 1.8V
VIO = 3.6V
SCLK
1.8V Host
SDATA
STMPE801
GPIO
3.6V Driver
2.5.3
GPIO-Hot Key feature
A GPIO is known as 'Hot Key' when it is configured to trigger an interruption to the host whenever the GPIO input changes state from LOW to HIGH or vice versa. This can also be used to Wake-up the host processor from Sleep mode. The GPIO is normally pulled high or pulled low externally with resistors. Any subsequent change in this logic state triggers an interrupt. 1. 2. 3. 4. 5. 6. Programming sequence for Hot Key: The required GPIO pin should be configured as input through the GPDR register. The Global Interrupt (Bit 2) should be enabled by writing '1' and the interrupt polarity should be set (Bit 0) to active low or active high in the SYSCON register. The ISGPIOR register should be read before enabling the GPIO interrupts in order to clear any existing interrupt. The individual GPIO interrupts can be enabled by writing '1' into the corresponding bit in the IEGPIOR register. Now, the port expander is ready to detect the change in logic state on any of the GPIOs and generate an interrupt to the host processor. Each GPIO state change is reported by the corresponding bit in the ISGPIOR register and the source of interrupt can be identified by reading the ISGPIOR register. This permits eight different interrupt sources to be connected to the host through the port expander. It should be noted that the change of GPIO state is recorded in the ISGPIOR even if the GPIO interrupt is not enabled in the IEGPIOR.
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AN2466 Figure 9.
Pin description of STMPE801 Hotkey detection using external pull-up/pull-down resistors on GPIO
2.6
Minimum pulse width
Typically a minimum pulse width of 2 microseconds is required on the GPIO for Hotkey detection. Any pulse width less than the stated value may not be registered in the ISGPIOR.
2.7
Power saving mode of operation
STMPE801 operates entirely on the I2C clock. When there is no activity on the I2C bus, the current consumption of the device is extremely low. However, when there is activity on the I2C bus, current consumption increases, even if the I2C traffic is not directed to the assigned address. The host system may choose to shut-down the I2C block in the STMPE801, if no access to the registers is required. This feature allows the current consumption to drop to the minimum. The host can turn OFF the I2C block by writing '1' into the I2C_SHDN bit in the SYSCON register. The I2C block shuts down on the next valid clock edge of the I2C clock signal. In this state, the device cannot be accessed by I2C, as the I2C block has shut down completely.
Note:
The ACK from STMPE801 for a I2C SHDN command is kept low only for around 250 s after the SCL goes high. After this duration the device I2C block shuts down and the SDA line is released. The I2C host should sample the ACK within this interval. To turn ON the I2C block, the system host must reset the STMPE801. This can be accomplished by an active low signal on the RESET_N pin. Table 8. Typical current rating (VCC = VIO = 3 V)
Operating modes Normal operation mode with all outputs switching and continuous activity on I2C bus I2C Shutdown mode Typical VIO current consumption at Ta = 25 C ~ 10 A <10 nA
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Conclusion
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2.8
Power-Up sequence
1. 2. 3. 4. The GND pin of the device should be grounded first. First ground the GND pin. The Reset_N pin should be connected to VIO through a weak pull-up resistor. Connect the Reset_N pin to VIO through a weak pull-up resistor. The I2C lines, SCL and SDATA should be connected to the host. Connect the I2C lines, SCL and SDATA to the host. Both lines should have pull-up resistors to VCC. The ADDRESS pin should be connected to GND or VCC as per slave address chosen. Connect the ADRESS pin to GND or VCC according to the slave address chosen. This can also be accomplished by using external weak pull-up and pull-down resistors on those two pins or by driving directly from the host. Both VCC and VIO should be supplied through suitable decoupling capacitors. The INT pin should be pulled high to VIO through a weak pull-up resistor. Pull the INT pin high to VIO through a weak pull-up resistor. With these minimal connections, the device functions in normal mode providing I2C access to the internal registers. All GPIOs are in default input mode. Tips for hardware trouble shooting:
5. 6. 7.
If the device does not function at the end of the power-up sequence provided above, the following tips can be used for troubleshooting. 1. 2. All pins are provided with an internal reverse biased ESD protection diode to GND. The connectivity of the pins vs. GND can be verified. I2C clock frequency can be reduced or increased to observe the corresponding change in the current consumption of the device. If there is no change, the device connections should be verified again.
3
Conclusion
The STMPE801 is a very versatile device that can be used to reduce the load on the CPU and expand the number of IOs available for the processor. The small size and simple configuration makes it a very attractive proposition for high-end, portable applications like smart phones. This application note provided the setup information to interface this device to a digital engine. The GPIOs in STMPE801 can also be used to perform special functions like key-pad matrix scanning by using suitable software keypad controller routines on the host processor. (Refer also application note AN2421: Using the STMPE801 as a keypad controller)
4
Revision history
Table 9.
Date 23-Mar-2007
Revision history
Revision 1 Initial release Changes
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