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STR7 (ARM) - 32-bit Microcontrollers
STR75x low power modes
Application Note
Format:
(725 kb)
or
(75 kb)
Last Updated: 10/07/2007
Pages: 49
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ARM7TDMI-S™ 32-Bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
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AN2476 Application note
STR75x low power modes
Introduction
This application note is intended for system designers who require a hardware implementation overview of the low power modes of the STR75x product family. It describes how to use the STR75x product family and details the components of supply circuitry, clock systems, register settings and low power management in order to optimize the use of STR750 in applications where low power is key.
July 2007
Rev 2
1/49
www.st.com
Contents
AN2476
Contents
1 Power supply and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 1.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 1.3.2 1.3.3 1.3.4 Power scheme 1: single external 3.3V power source . . . . . . . . . . . . . . . 5 Power scheme 2: dual external 3.3V and 1.8V power sources . . . . . . . . 7 Power scheme 3: single external 5.0V power source . . . . . . . . . . . . . . . 8 Power scheme 4: dual external 5.0V and 1.8V power sources . . . . . . . . 9
1.4 1.5 1.6 1.7
Main voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Low power voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Regulator startup monitor (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7.1 1.7.2 Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Peripheral clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.8.1 1.8.2 1.8.3 1.8.4 1.8.5 1.8.6 1.8.7 Low power bit writing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SLOW mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PCG mode: peripherals clocks gated mode . . . . . . . . . . . . . . . . . . . . . 16 WFI mode: Wait For Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STANDBY mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Auto-Wake-Up (AWU) from low power mode . . . . . . . . . . . . . . . . . . . . . 25
2
STR750 library low power mode functions . . . . . . . . . . . . . . . . . . . . . . 26
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 MRCC_CKSYSConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MRCC_HCLKConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MRCC_CKTIMConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MRCC_PCLKConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MRCC_EnterWFIMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MRCC_EnterSTOPMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MRCC_EnterSTANDBYMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MRCC_PeripheralClockConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Contents
3
Operating measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 Setup board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.1 3.1.2 Measurement with STR750_EVAL Board . . . . . . . . . . . . . . . . . . . . . . . 33 Measurements with Uniboard QFP 100 in single supply (3.3V or 5V) . . 34
3.2
Software provided with this application note . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1 3.2.2 3.2.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 WFI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3
Measurement and typical value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/49
Power supply and clocks
AN2476
1
1.1
Power supply and clocks
Introduction
The device can be connected in any of the following schemes, depending on the application requirements:
Power scheme 1: Single external 3.3V power source Power scheme 2: Dual external 3.3V and 1.8V power sources Power scheme 3: Single external 5.0V power source Power scheme 4: Dual external 5.0V and 1.8V power sources
1.2
Power supplies
The device has five power pins:
VDD_IO: power supply for I/Os (3.3V 0.3V or 5V 0.5V). Must be kept on, even in STANDBY mode. V18 (pins V18REG and V18 which are internally shorted): Power Supply for Digital, SRAM and Flash: 1.8V 0.15V. V18_BKP: Backup Power Supply for STANDBY or STOP Mode
Two embedded regulators are available to supply the internal 1.8V digital power:
V18 and V18_BKP are normally generated internally by the embedded regulators: The Main Voltage Regulator (MVREG) supplies V18 and V18_BKP. It delivers a power supply of 1.8V. The Low Power Voltage Regulator (LPVREG) can supply V18_BKP or V18 in STOP or STANDBY mode (see Section 1.8: Low power modes on page 14). It delivers a power supply of 1.6V 0.2V. When the embedded regulators are used, the Main Digital part of the chip (V18) can be powered off (meaning V18 left hi-Z) while keeping the backup circuitry powered on (V18_BKP). It is also possible to supply V18 and V18_BKP externally. Two sensitive analog blocks have dedicated power pins:
VDDA_PLL: Analog Power supply for PLL (must have the same voltage level as VDD_IO) VDDA_ADC: Analog Power supply for ADC (must have the same voltage level as VDD_IO)
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Power supply and clocks
1.3
1.3.1
Power supply schemes
Power scheme 1: single external 3.3V power source
In this configuration, the internal voltage regulators are switched on by forcing the VREG_DIS pin to low level. The VCORE supply required for the kernel logic and the VBACKUP supply required for the backup circuitry are generated internally by the Main Voltage Regulator or the Low Power Voltage Regulator (depending on the selected low power mode). This scheme has the advantage of requiring only one power source. Refer to Figure 1 on page 5. At power-up and during NORMAL mode (all operating modes except STOP and STANDBY Modes):
The Main Voltage Regulator powers both VCORE supply required for the kernel logic and the VBACKUP supply required for the backup circuitry. The Low Power Regulator is not used Power supply scheme 1 (single 3.3V supply VREGDIS=0) in NORMAL mode
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
Figure 1.
V18_BKP 1F VSS_BKP VREG_DIS V18 33nF VSS18 V18REG 10F VSS18 VDD_IO 3.3V 1F VSS_IO V18
NORMAL MODE
VBACKUP
LOW POWER VLPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH
BACKUP CIRCUITRY OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
+/-0.3V
MAIN VMVREG = 1.8V VOLTAGE REGULATOR VIO=3.3V
OUT
VCORE
KERNEL LOGIC (CPU & DIGITAL & MEMORIES)
GP I/Os
IN
I/O LOGIC
VDD_PLL VSS_PLL
3.3V PLL
VDD_ADC
3.3V
VSS_ADC ADCIN
ADC
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Power supply and clocks In STANDBY mode (see Section 1.8.6: STANDBY mode on page 22):
AN2476
the Main Voltage Regulator is disabled (output VCORE is hi-Z), the kernel is powered-off the Low Power Voltage Regulator powers the backup circuitry. STANDBY mode in power supply scheme 1
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
V18_BKP
Figure 2.
STANDBY MODE
LOW POWER VLPVREG ~1.4V VOLTAGE REGULATOR V18 VDD_IO POWER SWITCH
VBACKUP
~1.6V
BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
UNPOWERED
OFF
MAIN VOLTAGE REGULATOR
VMVREG = HI-Z
VCORE = HI-Z
KERNEL LOGIC (CPU & DIGITAL & MEMORIES)
In STOP mode (where all clocks are disabled), it is possible to disable the Main Voltage Regulator and to power both the backup circuitry and the kernel logic with the Low Power Voltage Regulator (see Section 1.8.5: STOP mode on page 18) Figure 3.
V18_BKP VBACKUP LOW POWER VOLTAGE REGULATOR V18 VDD_IO VLPVREG
STOP MODE
Stop mode in power supply scheme 1 when MVREG is off
BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
POWER SWITCH
DISABLED (NO CLOCKS)
OFF
MAIN VOLTAGE REGULATOR
VMVREG = HI-Z
VCORE
KERNEL LOGIC (CPU & DIGITAL & MEMORIES)
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Power supply and clocks
1.3.2
Power scheme 2: dual external 3.3V and 1.8V power sources
In this configuration, the internal voltage regulators are switched off by forcing the VREG_DIS pin to high level. This scheme has the advantage of saving power consumption when the 1.8V power supply is already available in the application. V18 and V18_BKP are provided externally through the V18REG, V18 and V18_BKP power pins. VREG_DIS pin is tied to high level which disables the Main Voltage Regulator and the Low Power Voltage Regulator. All digital power pins (V18REG, V18 and V18_BKP) must be externally shorted to the same 1.8V power supply source. Internally, VCORE and VBACKUP are shorted by the Power Switch. In this scheme, STANDBY Mode is not available. Figure 4. Power supply scheme 2 (3.3V and 1.8V supplies, VREGDIS=1)
V18_BKP
VSS_BKP
VDD_IO
VREG_DIS
OFF
VBACKUP VLPVREG
V18 V18REG 1.8V VSS18 VDD_IO 3.3V
VSS_IO
LOW POWER VOLTAGE REGULATOR
BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
POWER SWITCH
OFF
+/-0.3V
MAIN VOLTAGE REGULATOR VIO=3.3V
OUT
VMVREG
VCORE
KERNEL (CORE & DIGITAL & MEMORIES)
GP I/Os I/O LOGIC
IN
VDD_PLL VSS_PLL
3.3V PLL
VDD_ADC
3.3V
VSS_ADC ADCIN
ADC
NOTE : THE EXTERNAL 3.3V POWER SUPPLY MUST ALWAYS BE KEPT ON
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Power supply and clocks
AN2476
1.3.3
Power scheme 3: single external 5.0V power source
This power scheme is equivalent to Power Scheme 1 with the exception that:
The external power supply is 5.0V +/-0.5V instead of 3.3V USB functionality is not available
STANDBY mode is supported in this scheme. Figure 5. Power supply scheme 3 (single 5.0V supply VREGDIS=0) in NORMAL mode
V18_BKP 1F VSS_BKP VREG_DIS V18 33nF VSS18 V18REG 10F VSS18 VDD_IO 5.0V 1F VSS_IO MAIN VMVREG = 1.8V VOLTAGE REGULATOR VIO=5.0V
OUT IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
NORMAL MODE
VBACKUP
LOW POWER V LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH V18
BACKUP CIRCUITRY OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
+/-0.5V
VCORE
KERNEL LOGIC (CPU & DIGITAL & MEMORIES)
GP I/Os
IN
I/O LOGIC
VDD_PLL VSS_PLL
5.0V PLL
VDD_ADC
5.0V
VSS_ADC ADCIN
ADC
8/49
AN2476
Power supply and clocks
1.3.4
Power scheme 4: dual external 5.0V and 1.8V power sources
In this configuration, the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high level. This scheme has the advantage of saving power consumption when the 1.8V power supply is already available in the application and providing 5V I/O capability. V18 and V18_BKP are provided externally through the V18REG, V18 and V18_BKP power pins. VREG_DIS pin is tied to high level which disables the Main Voltage Regulator and the Low Power Voltage Regulator. All digital power pins (V18REG, V18 and V18_BKP) must be externally shorted to the same 1.8V power supply source. Internally, VCORE and VBACKUP are also shorted by the power switch shown in Figure 6: Power supply scheme 4 (5V and 1.8V supplies, VREGDIS=1) on page 9. In this scheme:
STANDBY mode is not available USB functionality is not available Power supply scheme 4 (5V and 1.8V supplies, VREGDIS=1)
V18_BKP
VSS_BKP
Figure 6.
VDD_IO
VREG_DIS
OFF
VBACKUP VLPVREG
V18 V18REG 1.8V VSS18 VDD_IO 5.0V
VSS_IO
LOW POWER VOLTAGE REGULATOR
BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
POWER SWITCH
OFF
+/-0.5V
MAIN VOLTAGE REGULATOR VIO=5.0V
OUT
VMVREG
VCORE
KERNEL (CORE & DIGITAL & MEMORIES)
GP I/Os I/O LOGIC
IN
VDD_PLL VSS_PLL VDD_ADC
5.0V PLL
5.0V
VSS_ADC ADCIN
ADC
NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON
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Power supply and clocks
AN2476
1.4
Main voltage regulator
In power scheme 1 or 3 (see Section 1.3: Power supply schemes on page 5) the Main Voltage Regulator provides the 1.8V power supply starting from VDD_IO. The V18REG pin must be connected to external stabilization capacitors (min. 10 uF Tantalum, low series resistance, and 33nF ceramic). The V18 pin must be left unconnected. A decoupling capacitor of 1F must be added on the VDD_IO pin which is closest to the V18REG pin. Refer to the diagram in the application note, AN2419, STR75x hardware development getting started.
1.5
Low power voltage regulator
In power scheme 1 or 3 (see Section 1.3: Power supply schemes on page 5) the Low Power Voltage Regulator is used in STANDBY Mode and in STOP Mode (when MVREG is OFF in STOP mode). The V18_BKP pin must be connected to an external stabilization capacitor of 1F. It generates a non-stabilized and non-thermally-compensated voltage of approximately 1.4V. The output current is enough to power the backup circuitry (RTC and Wakeup Logic) or the VCORE supply required for the kernel logic in STOP mode (with the low power control parameters FLASH and OSC4M OFF, see Section 1.8.5: STOP mode on page 18).
In STANDBY mode, it provides the power supply starting from VDD_IO to the backup circuitry while the Kernel Logic is un-powered. In STOP mode, if you program the LP_PARAM13 control bit (MVREG OFF) to disable the Main Voltage Regulator, the Low Power Voltage Regulator powers the whole digital circuitry, saving the static consumption of the Main Voltage Regulator (~100A typical).
1.6
Regulator startup monitor (RSM)
The Main Voltage Regulator and the Low Power Voltage Regulator have an internal Regulator Startup Monitor (RSM) which monitors the regulated power supply. At power-up, the RSM extends the assertion of the RESET until the regulators are operating (until V18_BKP and V18 are at the right level). If there is a drop in the regulated power supply, the RSM automatically generates a RESET. This enhances the security of the system by preventing the MCU from going into an unpredictable state.
Note:
An external reset circuit must be used to provide the RESET at VDD_IO power-up. It is not sufficient to rely on the RESET generated by the RSM in this case. This is because RSM operation is guaranteed only when VDD_IO is within the specification (minimum 3.0V). When regulators are not used (VREG_DIS pin is tied to high level), the RSM is disabled.
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AN2476
Power supply and clocks
1.7
Clocks
The Clock controller provides the internal clocks needed by the different parts of the MCU:
HCLK clocks all the peripherals mapped on the AHB bus PCLK clocks all the peripherals mapped on the APB bus CK_TIM clocks several timer counters independently from the APB clock CK_USB clocks the USB interface kernel
1.7.1
Clock overview
Figure 7. Clock overview
~5 MHz UP TO 64 MHz
FREEOSC
4 MHz
PLL
48 MHz NCKD FLAG
4/8MHz
XT1 XT2
DIV2
1 0
CK_SYS
AHB & APB DIVIDERs
HCLK UP TO 64 MHz PCLK UP TO 32 MHz CK_TIM UP TO 64 MHz
OSC4M CLOCK DETECTOR /128
XRTC1 XRTC2
NCKD FLAG
CK_USB 48 MHz
OSC32K
32 kHz
RTC
ALARM WAKEUP
LPOSC
300 kHz
USB_CK
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Power supply and clocks
AN2476
Several on-chip oscillators can feed the MCU system clock (CK_SYS) from which the HCLK and PCLK derive:
FREEOSC: Internal Free Running Oscillator providing a clock of approximately 5 MHz, also used as emergency clock. It consists of the internal VCO of the PLL configured in free running mode OSC4M: 4 MHz Main Oscillator, based on: a 4 MHz Crystal/Ceramic oscillator connected to XT1/XT2 or an 8 MHz Crystal/Ceramic oscillator to XT1/XT2 followed by an embedded divider by 2 or external clock connected to XT1
which can be multiplied by the PLL to provide a wide range of frequencies (up to 64 MHz)
OSC32K: 32.768kHz Oscillator (Crystal or Ceramic oscillator) which can drive either the system clock and/or the RTC. LPOSC: Internal Low Power RC Oscillator providing a clock around 300 kHz which can drive either the system clock and/or the RTC.
Several configurable dividers provide a high degree of flexibility to the application in the choice of the APB or AHB frequency, while keeping a fixed frequency value for the USB clock (48 MHz). The Clock Detector (CKD) protects the Microcontroller against OSC4M or external clock failures. The RTC provides calendar, alarm and wake-up functions and can be clocked by any of the oscillators other than FREEOSC.
12/49
AN2476
Power supply and clocks
1.7.2
Peripheral clock scheme
Figure 8. Peripheral clock Scheme
UART2
HCLK (UP TO 64MHz) PCLK MRCC_PCLKEN(22) PCLK /16 APB PRESC CK_TIM (UP TO 64MHz) /(1,2,4,8) MRCC_PCLKEN(21) PCLK /16 REGISTERS DIVIDER 16-BIT INTEGER 6-BIT FRACTIONAL BAUD RATE
CK_SYS (UP TO 64MHz) AHB PRESC /(1,2,4,8)
UART1
REGISTERS DIVIDER 16-BIT INTEGER 6-BIT FRACTIONAL BAUD RATE
/2
PCLK (UP TO 32MHz)
ATM7TDMI-S GP-DMA
UART0
MRCC_PCLKEN(20) PCLK /16 REGISTERS DIVIDER 16-BIT INTEGER 6-BIT FRACTIONAL BAUD RATE
CK_TIM
PCLK
SRAM
HCLK
FLASH SMI
REGISTERS 7-BIT PRESC SMI_CK UP TO 48MHz MRCC_PCLKEN(14) PCLK
SSP1
REGISTERS /(CPSDVR(1+SCR) BIT RATE
PCLK
CPSDVR=2,4,6,8,10,12,...,254 (even number) SCR=0,1,2,3,..,255 - IN MASTER MODE: BIT RATE MAX = PCLK/2 - IN SLAVE MODE: BIT RATE MAX = PCLK/12
EIC MRCC REGISTERS
CK_USB (48MHz) P CL K
SSP0
MRCC_PCLKEN(13) PCLK REGISTERS /(CPSDVR(1+SCR) BIT RATE
CPSDVR=2,4,6,8,10,12,...,254 (even number) SCR=0,1,2,3,..,255 - IN MASTER MODE: BIT RATE MAX = PCLK/2 - IN SLAVE MODE: BIT RATE MAX = PCLK/12
USB PWM
PCLK MRCC_PCLKEN(5) CK_TIM REGISTERS MRCC_PCLKEN(9) PCLK CK_USB (48MHìz) REGISTERS & USB SRAM /4 or /8 FULL SPEED : 12Mbps
16-BIT PRESC
16-BIT COUNTER
I2C
REGISTERS
TIM2
PCLK MRCC_PCLKEN(4) CK_TIM 16-BIT PRESC CK_TIM 16-BIT COUNTER REGISTERS
MRCC_PCLKEN(18) PCLK /2(CC)+7
CC=2,3,4,..,4095
BAUD RATE IN STD MODE UP TO 100kHz BAUD RATE IN FAST MODE UP TO 400kHz
/3(CC)+9
CC=2,3,4,..,4095
PCLK
PCLK
CAN
MRCC_PCLKEN(16) PCLK REGISTERS & CAN SRAM 4 BITS 6 BITS BIT QUANTUM BAUD RATE UP TO 1MBps
TIM1
PCLK MRCC_PCLKEN(3) CK_TIM REGISTERS
BAUD-RATE PRESCALER
16-BIT PRESC
16-BIT COUNTER
WATCHDOG
REGISTERS PCLK 8-BIT PRESC 16-BIT COUNTER
TIM0
PCLK MRCC_PCLKEN(2) CK_TIM REGISTERS
RESET
ADC
16-BIT PRESC 16-BIT COUNTER MRCC_PCLKEN(0) PCLK REGISTERS ADC CK_ADC PRESCALER /1,2,4,6,8,10,12,14 up to TCONV=30xTADC 10MHz
TB
PCLK MRCC_PCLKEN(1) CK_TIM REGISTERS MRCC_PCLKEN(28) PCLK 16-BIT COUNTER MRCC_PCLKEN(24) PCLK
EXTIT REGISTERS GPIO REGISTERS
16-BIT PRESC
MRCC_PCLKEN(9) PCLK CK_RTC CK_RTC 20-BIT PRESC
RTC
REGISTERS 32-BIT COUNTER DATE ALARM
CK_RTC MUST BE AT LEAST 4X TIMES SLOWER THAN PCLK
13/49
Power supply and clocks
AN2476
1.8
Low power modes
Several low power modes are implemented to reach the best compromise between lowest power consumption, fastest start-up time and available wake-up sources:
SLOW MODE: System clock speed is reduced PCG MODE: APB Peripherals Clock Gating WFI MODE: Wait For Interrupts STOP MODE: All clocks are disabled STANDBY MODE: Part of the chip is unpowered
Software has to execute the low power bit writing sequence (see below) to enter WFI, STOP or STANDBY modes. This sequence protects the application from entering a low power mode unintentionally.
1.8.1
Low power bit writing sequence
WFI, STOP or STANDBY modes are entered by software writing the following specific sequence to the LP bit in the MRCC_PWRCTRL register. Before executing the sequence, LP_DONE bit status must be previously cleared.
Write LP bit to `1' Write LP bit to `1' Write LP bit to `0' Write LP bit to `1' Read LP: if successful, LP is first read at 1 and then cleared by hardware when entering in Low Power Mode.
This sequence is performed by internal function of the library Section 2: STR750 library low power mode functions on page 26. If this sequence is not performed correctly or if LP_DONE was not cleared, the sequence is automatically reset and must be re-executed from the beginning. To abort the sequence, simply write twice the LP bit to `0'. The LP_DONE status flag is set after a successful LP bit writing sequence (meaning that the system has entered and exited the low power mode). This information is useful to know if the low power mode has been effectively entered or not. As soon as the LP bit writing sequence is initiated:
The MRCC_PWRCTRL register is locked (any write access other than to the LP bit will be discarded) until the sequence is completed or aborted Interrupts are masked (IRQ and FIQ signals to the ARM CPU are gated) until the sequence is completed or aborted
Any interrupts which occur during this sequence will not be lost: they will be served after the sequence is completed or aborted. Before performing the sequence, all pending bit interrupts used to wake-up from STOP mode should be cleared. If any interrupts from an external interrupt line, an RTC alarm or NCKDF (no clock detected) event are still pending, the sequence will not performed correctly.
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AN2476
Power supply and clocks If an interrupt occurs during this sequence, the MCU will not enter Low Power Mode after completing the sequence, but will serve the interrupt instead. In both cases, software must then reexecute the low power bit writing sequence to effectively go into low power mode. It is possible to determine if the low power mode was entered by reading the LP and LP_DONE bits status after wake-up. It is mandatory to follow this flow chart to manage the low power mode: Figure 9. Mandatory software flow for entering low power mode
Main Program
1
Write LP to `1' Write LP to `1' Write LP to `0' Write LP to `1'
1
Read LP
Dedicated LP entry sequence Wait for Low Power entry time Low Power not executed, sequence should be re-done (bad sequence or IRQ during sequence) Low Power successfully executed LP_DONE should cleared.
2 2
N
LP='0' ? Y
3 4
Read LP_DONE
3
LP_DONE='1' ? N Interrupt Routine Y
4
Write LP_DONE to `0'
Main Program to be continued
The choice of low power mode entered with this sequence depends on the state of the LPMC bits described in the Table 1 on page 15. These bits can be set in the MRCC_PWRCTRL register. See Reference Manual for more detail. Table 1. Low Power mode selection
Control bits Low Power Mode Selected LPMC[1:0] 0 0 0 1 BURST WFI_FLASH_EN 0 0 1 0 1 1 1 1 0 1 Forbidden WFI, Flash enabled (DMA allowed in WFI) STANDBY Mode 0 1 STOP Mode Software Reset WFI, Flash disabled (DMA not allowed in WFI) WFI, Flash enabled (DMA allowed in WFI)
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1.8.2
SLOW mode
In SLOW mode, power consumption is reduced by slowing down the main clocks. Please refer to Section 2.1: MRCC_CKSYSConfig on page 26 to use dedicated function of the library. It is possible to use all the device functions of the chip, but at reduced speed. To enter Slow Mode, the HPRESC[1:0] and PPRESC[2:0] bits prescaler in the MRCC_PWRCTL register must be programmed to reduce the CPU and/or peripheral clock frequency. Please refer to the following sections to use dedicated function of the library: Section 2.2: MRCC_HCLKConfig on page 27 Section 2.3: MRCC_CKTIMConfig on page 28 Section 2.4: MRCC_PCLKConfig on page 29 It is also possible to use the RTC clock as system clock. This is done by programming the CKOSCSEL control bit with a special sequence of write instructions. In this configuration, the PLL can be disabled by software to reduce power consumption. When exiting from this mode, if the PLL has been disabled, the software must re-enable it in the same way as after a RESET.
1.8.3
PCG mode: peripherals clocks gated mode
It is possible to gate or ungate each clock feeding the APB peripherals independently. This is done by writing to the MRCC_PCLKEN register. This can be done at any time, allowing you to save power whenever these peripherals are not used, adapting dynamically to the needs of the application. To use a dedicated function of the library please refer to Section 2.8: MRCC_PeripheralClockConfig on page 31. By default, after reset, all APB peripherals are in PCG Mode (their clock is disabled). The clock to the Watchdog is an exception, it cannot be gated in PCG mode, it is always clocked by PCLK. Some peripherals (USB, TB, TIM, PWM ) use a clock source other than PCLK which can be gated using specific control bits:
CK_USB 48 MHz clock gated by the PLL2EN bit in the Clock Control Register (MRCC_CLKCTL). CK_TIM: clock to TB, TIM, PWM timers gated by specific bits in the Peripheral Clock Enable register (MRCC_PCLKEN).
1.8.4
WFI mode: Wait For Interrupt mode
In WFI mode power consumption is reduced by stopping the CPU. The program stops executing but peripherals are kept running and the register contents are preserved. Execution restarts when an interrupt request is sent to the EIC.
WFI mode entry procedure
Use the following procedure to enter WFI mode: 1. First select WFI Mode by programming the LPMC[1:0] and the WFI_FLASH_EN bits in the Power Management Control register (MRCC_PWRCTRL). Program the LP_PARAM bits in the MRCC_PWRCTRL register to enable or disable selected parts of the MCU circuitry in WFI mode Execute the Low Power Bit Writing Sequence as described in Section 1.8.1: Low power bit writing sequence on page 14.
2.
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Power supply and clocks This procedure is performed by the function of the library described in the Section 2.5: MRCC_EnterWFIMode on page 29.
LP mode control parameters
If the Flash is used in Burst mode, it must be kept enabled in WFI mode (WFI_FLASH_EN bit = 1).
If the WFI_FLASH_EN bit is set, the Flash memory is kept enabled in WFI mode and the system can perform DMA transfers. The LP_PARAM bits in the MRCC_PWRCTRL register have no effect in this case.
If the Flash is used in Non-Burst mode, the Flash may be disabled in WFI mode (WFI_FLASH_EN bit = 0) and the LP_PARAM bits in the MRCC_PWRCTRL register used to further reduce power consumption in WFI mode as follows:
If WFI_FLASH_EN is reset, DMA must be disabled when entering WFI mode. FLASH OFF (LP_PARAM14). The Flash can be put in low power mode (LP_PARAM14=0) or disabled (LP_PARAM14=1). In the second case, the static consumption of the Flash is removed, but latency is incurred when exiting WFI mode. Other LP_PARAM bits have no effect in WFI mode.
Wake-up events
Wake-up from WFI mode can be performed either by an external interrupt from an I/O pin or an internal interrupt generated by one of the internal peripherals (assuming that its clock has not been disabled by software) or by NCKDF (no clock detected) interrupt. DMA interrupts can also be used, but only if the WFI_FLASH_EN bit in the Power Management Control register (MRCC_PWRCTRL) has been previously set. You can also combine WFI mode with PCG mode. However in this case, the peripherals that are disabled cannot generate the interrupt used to exit from WFI mode and another interrupt source has to be available. It is also possible to wake-up from WFI when triggered by an external interrupt line (configured in the EXTIT registers) without having enabled the corresponding IRQ in the EIC. In this case, the external interrupt event will cause a wake-up from WFI, but no IRQ routine will be invoked. The program will simply resume execution. The RTC can wake up the MCU from WFI in two ways:
either using the global interrupt of the RTC (Alarm, Second or Overflow) or through external interrupt line #15 which is connected only to the RTC alarm. In this case, this external interrupt must be properly configured.
However, it is recommended to use the global interrupt of the RTC to wake-up from WFI.
Wake-up latency
If the Flash memory is kept enabled (WFI_FLASH_EN) or in low power mode (LP_PARAM14=0), there will be no latency when resuming after wake-up from WFI mode. If Flash memory is disabled in WFI Mode, using the LP_PARAM14 bit in the Power Management Control register (MRCC_PWRCTRL), latency occurs when restarting due to the Flash start-up time. Wait states are inserted until the Flash is ready. This latency is not deterministic and may vary, depending on temperature or process dispersion.
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This latency does not occur if the software fetches from SRAM when it restarts. Any access to Flash will be performed correctly, but will result in wait states being inserted if the Flash is not ready. The Flash must be configured all the above control parameters, even if SRAM is used to fetch parts of the software. Table 2.
Control bits PLL + Clock Detector (CKD) LP_PARAM14: Flash off
WFI mode functionality
Functionality in WFI mode Wake-up resources External interrupts Internal interrupts Clock Detector Yes No latency WakeClock up config. latency state after due to: wake-up
Voltage Regulators
OSC4M Oscillator
RTC clock source
RTC enabled
Flash
No 1 Yes No 0 Yes All Main VREG
Off (in On On non Burst mode) On (enabled On On or low power mode) Yes Yes if enabled All
No Flash Yes No Yes Unchanged
1.8.5
STOP mode
In this mode CK_SYS is stopped. This means that the CPU and all the peripherals clocked by CK_SYS or derived clocks are disabled. As a result, the AHB and APB peripherals are not clocked, so the digital part of the MCU consumes no power other than the leakage current due to the process technology. In STOP mode, all the registers and SRAM contents are preserved, the PLL and clock configuration can remain unchanged.
STOP mode entry procedure
Use the following procedure to enter STOP mode: 1. 2. 3. First select STOP Mode by programming the LPMC[1:0] bits in the MRCC_PWRCTRL register. Program the LP_PARAM bits in the MRCC_PWRCTRL register to enable or disable some peripherals in STOP mode Execute the Low Power Bit Writing Sequence as described in Section 1.8.1: Low power bit writing sequence on page 14.
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RTC Alarm
NRSTIN
AN2476
Power supply and clocks This procedure is performed by the function of the library described in the Section 2.6: MRCC_EnterSTOPMode on page 30
LP mode control parameters
To further reduce power consumption in STOP mode, additional parts of the MCU can be disabled when entering STOP Mode. This can be configured by programming the LP_PARAM[15:13] bits in the MRCC_PWRCTRL register:
OSC4M and PLL OFF (LP_PARAM15): This removes the power consumption of the PLL and the OSC4M oscillator, however the clock configuration returns to its reset state. So when resuming from Stop mode after a wake-up event, it is necessary to manage the start-up time for oscillator stabilization and to re-enable the PLL. FLASH OFF (LP_PARAM14): This saves the static power consumption of the Flash, but some latency for Flash start-up is incurred when waking up from STOP mode. MVREG OFF (LP_PARAM13): When this parameter is set, the LPVREG (Low Power Voltage Regulator) powers the whole circuit, saving the static consumption of the MVREG (Main Voltage Regulator). In addition, the OSC4M oscillator, PLL and Flash are also switched off (all three LP_PARAM bits 13, 14 and 14 are set) because the Low power regulator does not have enough power to drive them. When resuming from Stop mode after a wake-up event, start-up latency is incurred.
Note:
1
When using the LP_PARAM15 bit to switch off OSC4M in STOP mode, it is recommended to clear the NCKDF bit just before entering STOP mode. Otherwise, if NCKDF=1 when entering STOP mode, OSC4M will not be disabled and will continue to use power. If OSC4M is not used as the system clock source, it is strongly recommended to switch it off by setting the OSC4MOFF bin STOP mode even if LP_PARAM 15 is set and NCKDF is cleared as recommended in note 1 above.
2
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Power supply and clocks Table 3. STOP mode functionality
Functionality in STOP mode PLL + Clock Detector (CKD) Wake-up resources Clock Detector interrupt External interrupts Internal interrupts
AN2476
Control bits LP_PARAM13: MVREG off LP_PARAM15: OSC4M off
LP_PARAM14: Flash off
Voltage Regulators
OSC4M Oscillator
RTC clock source
RTC enabled
RTC Alarm
NRSTIN
Wake-up latency due to:
Clock configuration state after wake-up
Flash
No 1 1 1
None Off Off Off
No Yes No Off Off Off Yes Yes No Off Main VREG On On Off Yes Yes No On On On Yes Off On Yes No All No No
LP LPOSC, VREG Yes OSC32K No None
MVREG + Flash + OSC4M FLASH + OSC4M Reset State
1
1
LPOSC, Yes OSC32K No None LPOSC, OSC32K
1 0 0
0 Yes No 1 Yes
OSC4M
Flash Unchanged No latency
All No 0 0 Yes
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Power Consumption in STOP mode
Table 4 gives an approximate indication of the power savings that can be gained using the LP_PARAM15:13 bits in the Power Management Control register (MRCC_PWRCTRL). Table 4. Typical power consumption of circuits controlled by LP mode parameters
Circuit OSC4M oscillator and PLL Flash memory MVREG Main Voltage Regulator Power Consumption Saving (under typical conditions with 3.3V single power scheme)
Control bit LP_PARAM15 LP_PARAM14 LP_PARAM13
1.8 mA 515 A 130 A
When all the LP_PARAM bits are enabled, the MCU power consumption consists only of the static consumption of the Low Power Regulator (and the RSM) plus the leakage currents of the digital logic (a total of 20A typical at TA= 25 C for 3.3 V supply). In dual supply mode (VREG_DIS pin=1), the power consumption consists only of the leakage current (10 A typical at TA = 25 C on V18 supply). Note: The Low Power RC Oscillator (LPOSC) and the 32.768kHz crystal oscillator (OSC32K) are still active if previously programmed (RTC is still working if clocked by one of these two clocks). The ADC or USB can also consume power unless they are disabled before entering STOP mode.
Wake-up events
Wake-up from STOP mode can be triggered by a reset, an external interrupt event or an RTC alarm or NCKDF (no clock detected) interrupt. Refer to Table 3: STOP mode functionality on page 20. It is also possible to wake-up from STOP mode triggered by an external interrupt line (configured in the EXTIT registers) without having enabled the corresponding IRQ in the EIC. In this case, the External Interrupt Event will exit from STOP, but no IRQ routine will be invoked. The program will simply resume execution. The user program must clear the external interrupt line pending bit in the Pending Register (EXTIT_PR) which caused the wake-up from STOP mode. If this pending bit is not cleared, the next STOP mode entry procedure will be ignored and program execution will continue. The RTC can wake up the MCU from STOP mode only through external interrupt line #15 which is internally connected to the RTC alarm. In this case, this external interrupt must be properly configured. Note that only the RTC alarm is connected to external interrupt line #15 (not the RTC second or overflow interrupt).
Wake-up latency
When the OSC4M oscillator, the Flash memory and the MVREG voltage regulator are kept active, the application is able to restart immediately with almost no latency. If Flash memory is disabled in STOP Mode, using the LP_PARAM14 bit in the Power Management Control register (MRCC_PWRCTRL), latency occurs when restarting due to the Flash start-up time. Wait states are inserted until the Flash is ready. This latency is not deterministic and may vary, depending on temperature or process dispersion.
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This latency does not occur if the software fetches from SRAM when it restarts. Any access to Flash will be performed correctly, but will result in wait states being inserted if the Flash is not ready. If you disable the OSC4M oscillator in STOP Mode, using the LP_PARAM15 bit in the Power Management Control register (MRCC_PWRCTRL), the clock configuration is lost and returns to reset state. Software must re-configure the clocks when the MCU wakes-up from STOP mode.
Debug mode
If using the debug features of the ARM7TDMI-S, and the current application puts the MCU in STOP mode, the debug connection will be lost, because the ARM7TDMI-S core is no longer clocked. However, using Low Power Debug mode, the software can be debugged even with extensive use of STOP mode. To enable this feature, set the LPMC_DBG bit after RESET. In this configuration, whenever a STOP mode entry sequence is successfully executed, the MCU goes into WFI Mode instead of STOP mode, so the core keeps running and its debug features remain active. As WFI is performed instead of STOP mode, the WFI_FLASH_EN must be set (see Section 1.8.4: WFI mode: Wait For Interrupt mode on page 16);
1.8.6
STANDBY mode
This mode is only available when using the embedded regulators (pin VREG_DIS tied to 0). In STANDBY Mode, the MVREG (Main Voltage Regulator) is disabled and the internal power switch opened (see Figure 2: STANDBY mode in power supply scheme 1 on page 6). This powers off the kernel circuitry, reducing power consumption to almost zero. Only the backup circuitry remains powered by the LPVREG (Low Power Voltage Regulator). This mode is particularly important for applications requiring very low consumption even when a rise in temperature occurs: there is almost no dispersion in temperature because the leakage currents are very low (most of the digital part is not powered). The contents of the registers and SRAM are lost. The backup circuitry can be used to wakeup the microcontroller. Some backup registers also remain powered and can be used to store some parameters. This backup circuitry consists of:
RTC counter and alarm mechanism Wake-up logic Backup registers (8 bytes)
The Wake-up logic switches the power to the kernel back on. The kernel is kept under RESET until the internal voltage is correctly regulated; at this point the interface between the kernel and Backup block is reconnected, and the CPU restarts from its RESET sequence.
STANDBY mode entry procedure
Use the following procedure to enter STANDBY mode: 1. 2. First select STANDBY Mode by programming the LPMC[1:0] bits in the MRCC_PWRCTRL register. Execute the Low Power Bit Writing Sequence as described in Section 1.8.1: Low power bit writing sequence on page 14.
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Power supply and clocks This procedure is performed by the function of the library described in the Section 2.7: MRCC_EnterSTANDBYMode on page 31 The Low Power Mode Control Parameters (LP_PARAM bits in the MRCC_PWRCTRL) have no effect in STANDBY mode. To enter STANDBY mode, the WKPF bit must be reset. Otherwise, the STANDBY mode entry procedure will be ignored and program execution will continue. The user program should also take into account the case of a wake-up event occurring during the STANDBY mode entry procedure: in this case the STANDBY mode entry procedure will be ignored and program execution will continue.
Consumption in STANDBY mode
All the peripherals are disabled except the LPVREG (and its associated RSM). The RTC and its clock source (OSC32K or LPOSC) can be either kept disabled or activated. If the RTC is disabled, the consumption is reduced to the static consumption of the Low Power Regulator (and the RSM) which is typically 20A. The leakage currents due to the technology are negligible and there is almost no dispersion in temperature (most of the digital part is not powered)
Wake-up events
Wake-up from STANDBY mode can only be performed by:
A reset A rising edge RTC alarm event. See Figure 10: Wake-up from Standby mode on page 23 A rising edge on the WKP_STDBY pin
Refer to Table 5: STANDBY mode functionality on page 25. Figure 10. Wake-up from Standby mode
Cleared by software or at power-up CK_RTC
RTC
powered in STANDBY
RTC_ALARM
WKPF rising edge detection
Can be read by software EXIT FROM STANDBY
P1.15 (WKP_STDBY)
WKP_STDBY
After wake-up from STANDBY mode, program execution restarts in the same way as after a RESET (the vector reset will be fetched). However, if a wake-up event occurs during the STANDBY entry procedure, the STANDBY mode entry procedure is ignored and the program execution continues. The user program should take into account the case of a wake-up event occurring during the STANDBY mode entry procedure. Some status flags helps software to determine if it is resuming from RESET or from STANDBY mode and if STANDBY is exited because of a wake-up event or because of an external reset. Refer to the Reference manual for further information on the status bits STDBF and WKPF in the status register (MRCC_RFSR)
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The RTC can wake-up the MCU from STANDBY mode at each RTC alarm event, independently from external interrupt line #15 (no need to configure it). Note that the RTC Second or Overflow interrupts do not wake-up the MCU from STANDBY. The condition which wakes-up the MCU from STANDBY is a rising edge of the output of an OR gate between the P1.15 input pin and the RTC alarm event, see Figure 11: Internal connections of the external interrupt line #15 on page 24. Consequently, to wake-up from STANDBY by an RTC alarm, you must:
Apply low level to P1.15 pin. Configure the RTC to generate the RTC alarm.
Figure 11. Internal connections of the external interrupt line #15
CK_RTC
RTC
powered in STANDBY
RTC_ALARM LINE 15
EXTERNAL INTERRUPT CONTROLLER
P1.15 (WKP_STDBY)
WKP_STDBY
Wake-up latency
The latency is the same as when resuming from reset.
I/O states in STANDBY mode
In STANDBY mode, all GPIOs are configured in high impedance except the WKP_STDBY pin which is kept in input mode. All other pins are disabled (XT1, XT2, XRTC1/2, USB, etc.) except the NRSTIN and NRSTOUT pins which are still functional.
Debug mode
If using the debug features of the ARM7TDMI-S, and the current application puts the MCU in STANDBY mode, the debug connection will be lost, because the ARM7TDMI-S core is no longer powered.
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Power supply and clocks
Functionality in STANDBY mode Feature RTC enabled RTC clock source Voltage Regulators OSC4M oscillator PLL + Clock Detector (CKD) Flash memory Wakeup resources NRSTIN External Interrupts RTC Alarm Clock Detector Wake-up latency due to: Clock configuration state after wake-up Yes No MVREG + FLASH + OSC4M Reset state LPOSC or OSC32K LPVREG Not powered Not powered Not powered Yes WKP_STDBY pin No RTC disabled None
1.8.7
Auto-Wake-Up (AWU) from low power mode
The RTC can be used to wake-up the MCU from Low Power Mode without depending on an external interrupt (Auto-Wake-Up mode). The RTC provides a programmable time base for waking-up from STOP or STANDBY mode at selectable intervals (using the alarm event). For this purpose, two alternative RTC clock sources can be selected by programming the CKRTCSEL[1:0] bits in the MRCC_PWRCTRL register:
Low Power 32.768kHz crystal oscillator (OSC32K). This clock source provides a precise time base with very low power consumption (less than 1A added consumption in typical conditions)
Internal Low Power RC Oscillator (LPOSC) This clock source has the advantage of saving the cost of the 32.768kHz crystal. This internal RC Oscillator is designed to add minimum power consumption (2A added consumption in typical conditions).
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2
2.1
STR750 library low power mode functions
MRCC_CKSYSConfig
Function Name Function Prototype Behavior Description Input Parameter1 MRCC_CKSYSConfig
ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL)
Configures the system clock (CK_SYS). MRCC_CKSYS: specifies the clock source used as system clock. Refer to section "MRCC_CKSYS" for more details on the allowed values of this parameter. MRCC_PLL: specifies the PLL configuration. Refer to section "MRCC_PLL" for more details on the allowed values of this parameter. None An ErrorStatus enumeration value: SUCCESS: Clock configuration succeeded ERROR: Clock configuration failed To use the RTC clock as system clock, the RTC clock source must be previously configured using MRCC_CKRTCConfig() function. None
Input Parameter2 Output Parameter Return Parameter
Required preconditions Called functions
MRCC_CKSYS
To select the system clock, use one of the following values:
MRCC_CKSYS MRCC_CKSYS_FREEOSC MRCC_CKSYS_OSC4M MRCC_CKSYS_OSC4MPLL MRCC_CKSYS_RTC Meaning Internal VCO of the PLL configured in free running mode used as system clock 4MHz main oscillator (OSC4M) used as system clock 4MHz main oscillator (OSC4M) followed by PLL used as system clock RTC clock used as system clock
MRCC_PLL
To configure the PLL, use one of the following values:
MRCC_PLL MRCC_PLL_Disabled MRCC_PLL_NoChange MRCC_PLL_Mul_12 MRCC_PLL_Mul_14 MRCC_PLL_Mul_15 MRCC_PLL_Mul_16 Meaning PLL disabled No change on PLL configuration Multiplication by 12 Multiplication by 14 Multiplication by 15 Multiplication by 16
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STR750 library low power mode functions When fetching from internal Flash the max System Cock (CK_SYS) frequency is 60MHz (64MHz when fetching from SRAM). The table below describes the allowed combination of MRCC_CKSYS and MRCC_PLL parameters:
MRCC_CKSYS MRCC_CKSY S_FREEOSC MRCC_PLL_Disabled MRCC_PLL MRCC_PLL_NoChange MRCC_PLL_Mul_12 MRCC_PLL_Mul_14 MRCC_PLL_Mul_15 MRCC_PLL_Mul_16 X MRCC_CKSY S_OSC4M X X MRCC_CKSY S_OSC4MPLL X X X X MRCC_CKSY S_RTC X X -
Note:
"x:" allowed combination "-" : not allowed combination Example :
/* Set CK_SYS to 60 MHz */ if(MRCC_CKSYSConfig(MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15) == SUCCESS) { /* Place your code here */ } else { /* Add here some code to deal with this error */ }
2.2
MRCC_HCLKConfig
Function Name Function Prototype Behavior Description MRCC_HCLKConfig
void MRCC_HCLKConfig(u32 MRCC_HCLK)
Configures the AHB clock (HCLK). MRCC_HCLK: defines the AHB clock. This clock is derived from the system clock(CK_SYS). Refer to section "MRCC_HCLK" for more details on the allowed values of this parameter. None None None None
Input Parameter
Output Parameter Return Parameter Required preconditions Called functions
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MRCC_HCLK
To configure the AHB clock, use one of the following values:
MRCC_HCLK MRCC_CKSYS_Div1 MRCC_CKSYS_Div2 MRCC_CKSYS_Div4 MRCC_CKSYS_Div8 Meaning AHB clock = CK_SYS AHB clock = CK_SYS/2 AHB clock = CK_SYS/4 AHB clock = CK_SYS/8
Example :
/* Configure HCLK such as HCLK = CK_SYS */ MRCC_HCLKConfig(MRCC_CKSYS_Div1);
2.3
MRCC_CKTIMConfig
Function Name Function Prototype Behavior Description MRCC_CKTIMConfig
void MRCC_CKTIMConfig(u32 MRCC_CKTIM)
Configures the TIM clock (CK_TIM). MRCC_CKTIM: defines the TIM clock. This clock is derived from the AHB clock(HCLK). Refer to section "MRCC_CKTIM" for more details on the allowed values of this parameter. None None None None
Input Parameter
Output Parameter Return Parameter Required preconditions Called functions
MRCC_CKTIM
To configure the TIM clock, use one of the following values:
MRCC_CKTIM MRCC_HCLK_Div1 MRCC_HCLK_Div2 MRCC_HCLK_Div4 MRCC_HCLK_Div8 Meaning TIM clock = HCLK TIM clock = HCLK/2 TIM clock = HCLK/4 TIM clock = HCLK/8
Example:
/* Configure CKTIM such as CKTIM = HCLK/2 */ MRCC_CKTIMConfig(MRCC_HCLK_Div2);
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2.4
MRCC_PCLKConfig
Function Name Function Prototype Behavior Description MRCC_PCLKConfig
void MRCC_PCLKConfig(u32 MRCC_PCLK)
Configures the APB clock (PCLK). MRCC_PCLK: defines the APB clock. This clock is derived from the TIM clock(CK_TIM). Refer to section "MRCC_PCLK" for more details on the allowed values of this parameter. None None None None
Input Parameter
Output Parameter Return Parameter Required preconditions Called functions
MRCC_PCLK
To configure the APB clock, use one of the following values:
MRCC_PCLK MRCC_CKTIM_Div1 MRCC_CKTIM_Div2 M eaning APB clock = CKTIM APB clock = CKTIM/2
Example :
/* Configure PCLK such as PCLK = CKTIM */ MRCC_PCLKConfig(MRCC_CKTIM_Div1);
2.5
MRCC_EnterWFIMode
Function Name Function Prototype Behavior Description Input Parameter Output Parameter Return Parameter Required preconditions Called functions MRCC_EnterWFIMode
void MRCC_EnterWFIMode(u32 MRCC_WFIParam)
Enters WFI mode. MRCC_WFIParam: specifies the WFI mode control parameters. Refer to section "MRCC_WFIParam" for more details on the allowed values of this parameter. None None None None
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MRCC_WFIParam
To select the WFI mode control parameters, use one of the following values:
MRCC_WFIParam MRCC_WFIParam_Default MRCC_WFIParam_DMAEnabled1) MRCC_WFIParam_FLASHOff1) Meaning DMA disabled and FLASH enabled in WFI mode Enable DMA in WFI mode Disable FLASH in WFI mode
Note:
1
These two parameters can be used together. Example :
/* Enter WFI mode with DMA enabled */ MRCC_EnterWFIMode(MRCC_WFIParam_DMAEnabled);
2.6
MRCC_EnterSTOPMode
Function Name Function Prototype Behavior Description Input Parameter Output Parameter Return Parameter Required preconditions Called functions MRCC_EnterSTOPMode
void MRCC_EnterSTOPMode(u32 MRCC_STOPParam)
Enters STOP mode. MRCC_STOPParam: specifies the STOP mode control parameters. Refer to section "MRCC_STOPParam" for more details on the allowed values of this parameter. None None None None
MRCC_STOPParam
To select the STOP mode control parameters, use one of the following values:
MRCC_STOPParam MRCC_STOPParam_Default MRCC_STOPParam_OSC4MOff1) MRCC_STOPParam_FLASHOff1) MRCC_STOPParam_MVREGOff2) Meaning OSC4M, FLASH and MVREG enabled in STOP mode Disable OSC4M and PLL in STOP mode Disable FLASH in STOP mode Disable main voltage regulator in STOP mode
Note:
1 2
These two parameters can be used together. If this parameter is selected, OSC4M and FLASH are also disabled. Example:
/* Enter STOP mode with OSC4M and FLASH OFF */ MRCC_EnterSTOPMode(MRCC_STOPParam_FLASHOff | MRCC_STOPParam_OSC4MOff);
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2.7
MRCC_EnterSTANDBYMode
Function Name Function Prototype Behavior Description Input Parameter Output Parameter Return Parameter Required preconditions Called functions MRCC_EnterSTANDBYMode
void MRCC_EnterSTANDBYMode(void)
Enters STANDBY mode. None None None None None
Example:
/* Enter STANDBY mode */ MRCC_EnterSTANDBYMode();
2.8
MRCC_PeripheralClockConfig
Function Name Function Prototype Behavior Description Input Parameter1 MRCC_PeripheralClockConfig
void MRCC_PeripheralClockConfig( u32 MRCC_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral clock. MRCC_Peripheral: specifies the peripheral to gates its clock. Refer to section "MRCC_Peripheral" for more details on the allowed values of this parameter. NewState: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. None None None None
Input Parameter2 Output Parameter Return Parameter Required preconditions Called functions
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MRCC_Peripheral
To select the peripheral to gates its clock, use a combination of one or more of the following values:
MRCC_Peripheral MRCC_Peripheral_ALL MRCC_Peripheral_EXTIT MRCC_Peripheral_RTC MRCC_Peripheral_GPIO MRCC_Peripheral_UART2 MRCC_Peripheral_UART1 MRCC_Peripheral_UART0 MRCC_Peripheral_I2C MRCC_Peripheral_CAN MRCC_Peripheral_SSP1 MRCC_Peripheral_SSP0 MRCC_Peripheral_USB MRCC_Peripheral_PWM MRCC_Peripheral_TIM2 MRCC_Peripheral_TIM1 MRCC_Peripheral_TIM0 MRCC_Peripheral_TB MRCC_Peripheral_ADC Meaning All peripherals clock EXTIT clock RTC clock GPIO clock UART2 clock UART1 clock UART0 clock I2C clock CAN clock SSP1 clock SSP0 clock USB clock PWM clock TIM2 clock TIM1 clock TIM0 clock TB clock ADC clock
Example :
/* Enable GPIOs and TB clocks */ MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO | MRCC_Peripheral_TB, ENABLE);
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Operating measurements
3
3.1
Operating measurements
Setup board
The STR750 evaluation board (order code STR750-EVAL) and Uniboard (order code UBQFP100-1414O/ ) are available for evaluation and testing purposes. Contact your local ST sales office for further details.
3.1.1
Measurement with STR750_EVAL Board
Before starting the measurements, the potentiometer RV2 should be removed from the boards MB469 and MB469 rev. B. For correct usage instructions, refer to the User Manual STR750_EVAL Board, UM0268. With this board measurements can only be made at 3.3V (Single supply) or 3.3V and 1.8V (Dual supply).
Consumption measurements
In Single Supply: measurements can be made by replacing JP3 by an ampermeter. JP4, JP5, JP6 and JP13 must not be fitted. In Dual Supply: measurements can be made by replacing JP3 by an ampermeter, setting jumper JP4, and replacing JP5 and JP6 by an ampermeter to measure the consumption on V18BKP and V18 respectively. JP13 must not be fitted. Caution: the standby mode is not available in dual supply.
Wake-up time measurements
Definition: Two wake-up time measurements can be made. The STR75x can be restarted either from the low-power mode on the internal free oscillator (FREEOSC ) or on the main oscillator, restarting it if necessary (OSC4M PLL). FREEOSC: Time between wake-up trigger event and the first fetched instruction by the core. OSC4M PLL: Time between the wake-up trigger event and the execution of the instruction once the clock has been started by either the library function or in the interrupt handler routine. Pins P1.15 (WKP_STDBY pin) and P0.16 to measure the wake-up-time in a FREEOSC configuration. This time is measured between the rising edge on P1.15 and a falling edge on P0.16. Pins P1.15 (WKP_STDBY pin) and P2.18 to measure the wake-up-time in a OSC4M PLL configuration. This time is measured between the rising edge on P1.15 and a falling edge on P2.18.
Measurement: Place the oscilloscope on:
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3.1.2
Measurements with Uniboard QFP 100 in single supply (3.3V or 5V)
Figure 12. Uniboard QFP 100
Uniboard QFP 100
Close-up of JP1 and JP2 Before making measurements, the board must be configured as describe below:
First JP2 should be removed and JP1 set between VDD and VDD2_IN Don't use J4 to power supply the Board These external components are needed to update uniboard QFP100 Bill of material
Components UNIBOARD QFP 100 14x14 STR750 Chip Capacitor Capacitor Capacitor Capacitor Resistor Quar tz Value/Reference MB497 STR750FL2T6 1F 10F 33nF 22pF 10K 4MHz Quantity 1 1 2 1 1 4 9 1
Table 6.
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Operating measurements
Components Quar tz Connector
Value/Reference 32 KHz HE-20
Quantity 1 1
This table describes how the STR750 chip can be powered: Table 7. Power supply
Signal Name TEST VSS_IO VDD_IO VDDA_PLL VSS_IO VSSA_PLL VSS18 VSSBKP VDD_IO VDDA_ADC VSSA_ADC VSS_IO VREG_DIS VSS18 VSS_IO VDD_IO 99 69 70 73 74 75 97 98 44 45 48 49 53 54 pin n to VDD1 pin n to GND 9 10
This table describes how the STR750 chip can be decoupled Table 8. Decoupling capacitor
Pin 52 55 96 99 Connection Decoupling with 10F capacitor and VSS18 pin 53. Decoupling with 1F capacitor and VSSBKP pin 54. Decoupling with 33nF capacitor and VSS18 pin 97. Decoupling with 1F capacitor and VSS_IO pin 98.
SIgnal Name V18REG V18_BKP V18 VDD_IO
This table describes how to connect the Pull-up and Pull-down resistors: Table 9.
Boot 0 Boot 1
Pull-up and pull-down resistor
Pin 4 27 Connection Pull-down to GND via 10K resistor Pull-down to GND via 10K resistor
Signal Name
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Signal Name JTMS JTCK JTDI NJTSRST RTCK WKP_STDBY P1.05
Pin 18 19 21 22 25 60 90
Connection Pull-up to VDD1 via 10K resistor Pull-down to GND via 10K resistor Pull-up to VDD1 via 10K resistor Pull-up to VDD1 via 10K resistor Pull-down to GND via 10K resistor Pull-down to VDD1 via 10K resistor Pull-up to VDD1 via 10K resistor
This table describes how to connect the JTAG connector: Table 10. JTAG connection (J3)
Pin of HE20 connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connection to the Chip VDD1 VDD1 Pin 22 GND Pin 21 GND Pin 18 GND Pin 19 GND Pin 25 GND pin 20 GND pin 59 GND No connect GND No connect GND
Signal Name VTref GND NJTSRST GND JTDI GND JTMS GND JTCK GND RTCK GND JTDO GND RESET_IN GND DBGRQ GND DBGACK GND
This table describes how to connect the Reset Pin and Oscillators to the Chip
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RESET_IN X1, X2 MCU X1, X2 RTC
Operating measurements Other pin connections
Pin 59 46,47 56,57 RESET J8 4MHz quartz with two capacitor 22pF to GND see Figure5. 32KHz quartz with two capacitor 22pFto GND, see Figure6. Connection
Signal Name
Figure 13. Main Clock circuit
Pin46 Pin47
C2 5pF-25pF
Q1 4MHz
C3 5pF-25pF
Figure 14. Real time clock circuit
Pin56 Pin57
C4 22pF-46nF
Q2 32KHz
C5 22pF-46nF
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Operating measurements Table 12.
J8 J7 J7 J7 J7 J9 J9 J9 J9 J9 J9
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Other pin connections for the uniboard Pin VDD S1-1 S1-2 S2-1 S2-2 LED1-A LED1-K LED2-A LED2-K LED3-A LED3-K Connection VDD1 pin 60 of the chip VDD1 pin 90 of the chip GND VDD1 pin 32 VDD1 pin 31 VDD1 pin 42
Connector Name
Put the STR750 in the Socket Connect the JTAG link on J2 connector Connect the board to the power supply at 3.3V or 5V (GND black connector and VDD1_IN red connector)
Measurement with Uniboard QFP 100 in dual supply (3.3V or 5V and 1.8V)
To make measurements in dual supply mode the board must be configured as described before with the following modifications:
Signal Name VREG_DIS V18REG V18_BKP V18 pin n to VDD1 75 52 55 96 pin n to GND pin n to VDD2
Connect the board to the power supply at 3.3V or 5V (GND black connector and VDD1_IN red connector) and 1.8V to VDD2_IN ( Yellow connector).
Consumption measurements
In Single Supply: measurements can be made by placing an ampmeter between the power supply and the VDD1_IN. In Dual Supply: measurements can be made by placing an ampmeter between the power supply and the VDD1_IN (to determine the consumption at 3.3 V / 5 V) or between the power supply and the VDD2_IN (to determine the consumption at 1.8 V). Caution: the standby mode is not available in dual supply.
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Wake-up time measurements
Definition: Two wake-up time measurements can be made. The STR75x can be restarted either from the low-power mode on the internal free oscillator (FREEOSC ) or on the main oscillator, restarting it if necessary (OSC4M PLL). FREEOSC: Time between wake-up trigger event and the first fetched instruction by the core. OSC4M PLL: Time between the wake-up trigger event and the execution of the instruction once the clock has been started by either the library function or in the interrupt handler routine. Pin 60 (I/O P1.15: WKP_STDBY) and pin 42 (I/O P0.16) to measure the wake-uptime in a FREEOSC configuration. This time is measured between the rising edge on pin 60 and a falling edge on pin 42. Pin 60 (I/O P1.15: WKP_STDBY) and Pin 32 (I/O P2.18) to measure the wake-uptime in a OSC4M PLL configuration. This time is measured between the rising edge on pin 60 and a falling edge on pin 32.
Measurement: Place the oscilloscope on:
3.2
Software provided with this application note
There are 3 folders in the ZIP file provided with this application note:
3.2.1
Standby mode
This example shows how to put the system in STANDBY mode and how to wake-up again using external RESET, WKP_STDBY pin or RTC Alarm (if RTC_ON is set in 75x_conf.h file). Of course this software used the standard STR750 library and this example show how to used the function MRCC_EnterSTANDBYMode(). Refer to Chapter 2.7: MRCC_EnterSTANDBYMode on page 31 for further information.
Choose RTC using clock: Comment the following line in the 75x_conf.h file, if the RTC clock is not required in STANDBY mode in the application: #define RTC_ON In the associated software, the system clock is set to 60 MHz, the EXTIT line7 is configured to generate an interrupt on falling edge.
If RTC ON is set (by uncommenting the line #define RTC_ON in 75x_conf.h file): The RTC is programmed to generate an interrupt each 1 second. In the RTC interrupt handler, an LED connected to P2.18 pin is toggled, and an LED connected to P0.16 is on. This is used to indicate whether the MCU is in STANDBY or RUN mode. When a falling edge is detected on EXTIT line7, an interrupt is generated. In the EXTIT handler routine the RTC is configured to generate an alarm event after 10 seconds. Then the system enters STANDBY mode causing the P2.18 pin to stop toggling. A rising edge on WKP_STDBY pin or an external RESET will wake-up the system from STANDBY. If within 10 seconds neither rising edge on WKP_STDBY nor external RESET are generated, the RTC alarm wakes-up the system. After that
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the LED connected to P0.16 is switched on and the VCO of the PLL (FREEOSC) supplies the system clock. After The clock configuration (system clock set to 60 MHz), the P2.18 pin restarts toggling.
If RTC ON is not set (by commenting the line #define RTC_ON in 75x_conf.h file): An LED connected to P2.18 pin is on, to indicate the MCU is in RUN mode. When a falling edge is detected on EXTIT line7, an interrupt is generated, the system enters STANDBY mode causing the P2.18 pin to switch off. A rising edge on WKP_STDBY pin or an external RESET will wake-up the system from STANDBY. Then the LED connected to P0.16 is switched on and the VCO of the PLL(FREEOSC) supplies the system clock.
After The clock configuration (system clock set to 60 MHz), the P2.18 pin is switched on.
Directory contents: 75x_conf.h : Library Configuration file 75x_it.c : Interrupt handlers main.c : Main program Connect an LED to pin P0.16 (LD3 on STR75x-EVAL board). Connect an LED to pin P2.18 (LD4 on STR75x-EVAL board). Connect a push-button to the WKP_STDBY pin (P1.15) (the wake-up push-button on the STR75x-EVAL board). Connect a push-button to EXTIT line7 pin (P1.05) (the key push-button on the STR75x-EVAL board)
Hardware environment:
How to use it: In order to make the program work, you must do the following : a) b) Create a project and setup all your toolchain's start-up files Compile the directory content files and required Library files : 75x_lib.c 75x_r tc.c 75x_gpio.c 75x_mrcc.c 75x_eic.c 75x_extit.c 75x_cfg.c c) d) Link all compiled files and load your image into Flash Run the example
Note:
If the line #Define RTC_ON is modified through commenting or uncommenting in the file 75x_conf.h, the project must be rebuilt
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Operating measurements
3.2.2
STOP mode
This example shows how to put the system in STOP mode and then to wake-up from this mode using an external interrupt, an RTC alarm or an NCKD (no clock detected) interrupt.
Choose the Board: The choice of board to be used to perform the measurements is defined in the 75x_conf.h file. Comment/uncomment the appropriate lines, depending on the chosen board: #define STR750_EVAL //#define Uniboard
Choose the STOP mode: Uncomment one of these lines in the 75x_conf.h file to select the STOP mode configuration: //#define MRCC_STOP_Default //#define STOP_MVREG_Off //#define STOP_OSC4M_Off //#define STOP_FLASH_Off //#define STOP_FLASH_PLL_Off #define STOP_FLASH_OSC4M_Off
Choose RTC using clock: Comment the following line in the 75x_conf.h file if the RTC is not used to wake-up from STOP mode: #define RTC_ON In the associated software, the system clock is set to 60 MHz and an interrupt is generated if no clock is present on OSC4M.
If the RTC is on (by uncommenting the line #define RTC_ON in the 75x_conf.h file): The EXTIT line7(P1.05) and EXTIT line15 are configured to generate interrupts on a rising edge and the RTC is programmed to generate an interrupt each 1 second. The EXTIT line15 is shared between the RTC_Alarm event and the WKP_STDBY pin (P1.15). In the RTC interrupt handler, an LED connected to P2.18 pin is toggled and used to indicate whether the MCU is in STOP or RUN mode. The system enters mode as follows: a) b) c) a) b) c) After system power on, an LED connected to P2.18 pin is toggled each 1 second After 5 seconds the RTC is configured to generate an alarm event after a delay of 10 seconds The system then enters STOP mode causing the P2.18 pin to stop toggling. To wake-up from STOP mode either a rising edge can be applied on EXTIT line15, EXTIT line7 or the 4MHz external Quartz oscillator can be disconnected. If within 10 seconds none of those actions are performed, the RTC alarm wakesup the system. The LED connected to P0.16 is then switched on and the VCO of the PLL (FREEOSC) supplies the system clock.
The system exits STOP mode as follows:
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Operating measurements d)
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After the clock configuration (system clock set to 60 MHz), the P2.18 pin restarts toggling and in 5 seconds the system enters STOP mode again before exiting in the manner described above.
This behavior is repeated in an infinite loop.
If RTC is not on (by commenting the line #define RTC_ON in the 75x_conf.h file): The EXTIT line7(P1.05) and EXTIT line15 ( WKP_STDBY pin P1.15) are configured to generate interrupts on a rising edge. An LED connected to P2.18 pin is switched on to indicate when the MCU is in RUN mode. The system enters STOP mode as follows: a) b) After system power on, an LED connected to P2.18 pin is switched on. When a falling edge is detected on EXTIT line7 the system enters STOP mode causing the P2.18 pin to switch off the LED. To wake-up from STOP mode, either a rising edge can be applied on EXTIT line15, EXTIT line7 or the 4MHz external Quartz oscillator can be disconnected. The LED connected to P0.16 is switched on and the VCO of the PLL (FREEOSC) supplies the system clock. After the clock configuration (system clock set to 60 MHz), the LED connected to P2.18 pin is switched on.
The system exits STOP mode as follows: a) b) c)
When the 4MHz external Quartz oscillator is disconnected, the VCO of the PLL (FREEOSC) supplies the system clock. Once the 4MHz clock has recovered (by connecting the 4MHz Quartz oscillator) the system clock is reconfigured to 60 MHz. If the system fails to enter STOP mode, a led connected to P2.19 pin is turned on.
Directory contents: 75x_conf.h Library Configuration file 75x_it.c main.c Interrupt handlers Main program
Hardware environment: Connect three LEDS to P016, P2.18 and P2.19 pins (respectively LD3, LD4 and LD5 on STR75x-EVAL board). Connect a push-button to WKP_STDBY pin (P1.15) (the wakeup push-button on STR75x-EVAL board). Connect a push-button to EXTIT line7 pin (P1.05) (the key push-button on STR75x-EVAL board). On STR75x-EVAL board the 4MHz Quartz oscillator is mounted on socket so it is easy to disconnect.
How to use it: In order to make the program work, you must do the following : a) b) Create a project and setup all your toolchain's start-up files Compile the directory content files and required Library files : 75x_lib.c 75x_r tc.c 75x_gpio.c
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Operating measurements
If the line #Define RTC_ON is modified through commenting/uncommenting in the 75x_conf.h file, the project must be rebuilt.
3.2.3
WFI mode
This example shows how to enter the system to WFI mode and wake-up from this mode using an external Interrupt, an RTC Alarm or a NCKD(no clock detected) interrupt.
Choose the Board: The chosen board for measurements can be selected in the 75x_conf.h file. Uncomment the appropriate line: #define STR750_EVAL //#define Uniboard
Choose the WFI Mode: Uncomment one of these lines in the 75x_conf.h file, to choose the required WFI mode for the application: //#define WFI_FLASH_Off //#define WFI_FLASH_PowerDown #define WFI_FLASH_On
In the associated software, the system clock is set to 64 MHz and an interrupt is generated if no clock is present on OSC4M. The EXTIT line7(P1.05) and EXTIT line15 are configured to generate interrupts on a rising edge and the RTC is programmed to generate an interrupt each 1 second. The EXTIT line15 is shared between the RTC_Alarm event and the WKP_STDBY pin (P1.15). In the RTC interrupt handler, an LED connected to P2.18 pin is toggled and used to indicate whether the MCU is in WFI or RUN mode. The system enters WFI mode as follows: a) b) c) a) b) c) After system is powered on, an LED connected to P2.18 pin is toggled each 1 second After 5 seconds, the RTC is configured to generate an Alarm event with a trigger delay of 10 seconds. The system then enters WFI mode causing the P2.18 pin to stop toggling. To wake-up from WFI mode a rising edge can be applied on EXTIT line15, EXTIT line7 or the 4MHz external Quartz oscillator can be disconnected. If within 10 seconds none of those actions are performed, the RTC Alarm wakes the system up. The P2.18 pin then restarts toggling and after 5 seconds the system enters WFI mode again before exiting in the manner described above. This behavior is repeated in an infinite loop.
The system exits WFI mode as follows:
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When the 4MHz external Quartz oscillator is disconnected, the VCO of the PLL (FREEOSC) supplies the system clock. Once the 4MHz clock has recovered (by connecting the 4MHz Quartz oscillator) the system clock is reconfigured to 64 MHz. If the system fails to enter WFI mode, an LED connected to P2.19 pin is turned on.
Directory contents 75x_conf.h : Library Configuration file 75x_it.c : Interrupt handlers main.c : Main program Connect two LEDs to P2.18 and P2.19 pins (respectively LD4 and LD5 on STR75x-EVAL board). Connect a push-button to WKP_STDBY pin (P1.15) (Wakeup push-button on STR75x-EVAL board). Connect a push-button to EXTIT line7 pin (P1.05) (Key push-button on STR75xEVAL board). On the STR75x-EVAL board the 4MHz Quartz oscillator is mounted on socket so it is easy to disconnect it.
Hardware environment
How to use it In order to make the program work, you must do the following : a) b) Create a project and setup all your toolchain's start-up files Compile the directory content files and required Library files : 75x_lib.c 75x_r tc.c 75x_gpio.c 75x_mrcc.c 75x_eic.c 75x_extit.c 75x_cfg.c c) d) Link all compiled files and load your image into Flash Run the example
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3.3
Measurement and typical value
Table 13 below shows the low power mode configurations for the examples described in Section 3.2 on page 39. Table 13. Low power mode configurations for example measurements
Mode STANDBY from Flash MVREG OSC4M OFF OFF OFF OFF ON STOP from Flash ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON PLL OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON FLASH OFF OFF OFF OFF OFF ON OFF OFF ON OFF P DOWN ON RTC OFF ON 32k OFF ON 32k OFF OFF OFF OFF OFF ON 32k ON 32k ON 32k
Example mode name Standby Standby (with Define RTC_ON) STOP_MVREG_Off STOP_MVREG_Off (with Define RTC_ON) STOP_FLASH_OSC4M_Off STOP_OSC4M_Off STOP_FLASH_PLL_Off STOP_FLASH_Off STOP_Default WFI_FLASH_Off
WFI_FLASH_PowerDown 1) WFI from Flash WFI_FLASH_On
Note:
1
For this configuration, it is forbidden to put the Flash into BURST mode. Table 14 shows the typical consumption and timing values measured with these mode configurations. Table 14. Typical consumption and timing measurements
Consumption with TA= +25C (A) Dual Supply 3.3V Idd(V33)/ (V18) NA NA 0.3 / 2.4 3.0 / 2.6 Wake-up times (s)
2)
Example mode name
Single Supply 3.3V Idd(V33)
Single Supply 5V Idd(V33) 14.9 19.6 15.4 21.1
Dual Supply 5V Idd(V33)/ (V18) NA NA 0.8/ 2.4 5.3 / 2.6
OSC4M FREEOSC PLL
Standby Standby (with Define RTC_ON) STOP_MVREG_Off STOP_MVREG_Off (with Define RTC_ON)
10.8 14.1 11.9 15.8
3250 3250 3250 3250
85 85 38 40
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Operating measurements Table 14. Typical consumption and timing measurements
Consumption with TA= +25C (A) Dual Supply 3.3V Idd(V33)/ (V18) 0.3/ 2.4 0.3/ 507 878/ 114 1865/ 3860 1865/ 4352 1758/ 18466 1758/ 18914 1758/ 28130
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Wake-up times (s)
2)
Example mode name
Single Supply 3.3V Idd(V33)
Single Supply 5V Idd(V33) 118 626 1020 5849 6427 21950 22440 34160
Dual Supply 5V Idd(V33)/ (V18) 0.8 / 2.4 0.8/ 507 740/ 114 1782/ 3860 1782/ 4352 1666/ 18466 1666/ 18914 1666/ 28130
OSC4M FREEOSC PLL
STOP_FLASH_OSC4M_Off STOP_OSC4M_Off STOP_FLASH_PLL_Off STOP_FLASH_Off STOP_Default WFI_FLASH_Off WFI_FLASH_PowerDown1) WFI_FLASH_On
110 618 1104 5947 6458 21940 22480 34180
3380 3290 200 9.5 9 10.6 3.08 3.08
40 40 40 NA NA NA NA NA
Note:
1 2
For this configuration, it is forbidden to put the Flash into BURST mode. Measurements for the wake-up time have been made on pin 1.15. Refer for to Section 3.1 on page 33 for further details.
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Conclusion
4
Conclusion
Before choosing clock and regulator configuration it is important to verify the application requirements not only for the consumption but also in terms of the wake-up time, the peripheral availibilty and whether the RAM contents need to be preserved until wake-up. For example, in STOP mode the SRAM content is preserved, however in Standby mode, SRAM content is lost. There are therefore compromises to be made between firstly the wake-up time and the consumption, and secondly the preservation of the SRAM contents and the peripheral availability. For example, the measured mode STOP_FLASH_PLL_Off shown in Table 14 on page 45 uses roughly double the power consumption as the STOP_OSC4M_Off mode, however it is able to react faster by having a much reduced wake-up time.
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Revision history
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5
Revision history
Table 15.
Date 26-Mar-2007 09-Jul-2007
Document revision history
Revision 1 2 Initial release. Connections between VBACKUP and VCORE in Figure 1, Figure 5 updated Changes
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