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AN2534 Application note
STw4811N/STw4811M minimal operation mode
Introduction
This document provides guidance on how to use the STw4811N/STw4811M with minimal functions enabled (default startup operation).
Purpose and scope
This document describes:
How to use the STw4811N/STw4811M in minimal operation mode (startup operation). How to wire unused blocs and features, whether unused pins must be left open or connected to a defined level.
Software considerations, which bits must be left in default state, and which bits must be set to defined values.
September 2007
Rev 1
1/15
www.st.com
SMPS step-down converters
AN2534
1
1.1
SMPS step-down converters
Vcore
By default, the Vcore step-down regulator is on at startup, and set to 1.26 V. External components Vcore capacitor, Vcore coil and Vbat_Vcore capacitor are mandatory.
1.2
Vio_Vmem
By default, the Vio_Vmem step-down regulator is on at startup, with a fixed output voltage of 1.8 V. External components Vio_Vmem capacitor, Vio_Vmem coil and Vbat_Vio_Vmem capacitor are mandatory.
1.3
Application schematics and recommended components
Figure 1. Typical application schematics
VBAT VBAT _VCORE VBAT _VCORE
D10 D9 C1 D8 A10 L2 VCORE
VLX _ VCORE VLX _ VCORE
VCORE _ FB
C5
C4
VMINUS _VCORE VMINUS _VCORE
B10 C9
Figure 2.
Typical application schematics
VBAT
VBAT _VIOVMEM VBAT _ VIOVMEM VLX _VIOVMEM VLX _VIOVMEM VIOVMEM _FB
A4 B4 A3 C4 A5 C2 A2 B3 C1 L1 VIOVMEM
VMINUS _ VIOVMEM VMINUS _ VIOVMEM
2/15
AN2534 Table 1.
Name C1 22 F C4 C2 10 F C5 L1 4.7 H L2
SMPS step-down converters Component list
Typical value Comments See Table 4 for recommended DC/DC output filter capacitors Function VIO_VMEM output filter VCORE output filter
VBAT_VIOVMEM decoupling See Table 4 for recommended DC/DC input decoupling capacitors VBAT_VCORE decoupling See Table 4 for recommended DC/DC coils VIOVMEM DC/DC coil VCORE DC/DC coil
Table 2.
Supplier Murata
Recommended DC/DC output filter capacitors (22F)
Part number GRM21BR60J226 Voltage (V) 6 .3 TC Code X5R Package 0805
Table 3.
Supplier Murata Murata
Recommended DC/DC input decoupling capacitors (10F)
Part number GRM188R60J106 GRM21BR60J106 Voltage (V) 6.3 6.3 TC code X5R X5R Package 0603 0805
Table 4.
Supplier
Recommended DC/DC coils (4.7H)
Part number VLF3010AT-4R7MR70 DCR () 0.28 0.16 0.14 0.18 0.15 0.32 0.19 Irms (A) 0.7 0.74 1.1 1 1.1 1 .1 1.1 Lxlxh (mm) 2.8 x 2.6 x 1.0 2.8 x 2.6 x 1.2 3.7 x 3.5 x 1.2 3.2 x 2.5 x 1.55 5.5 x 4.2 x 1.8 3.3 x 2.2 x 1.4 3.2 x 2.5 x 2.0
TDK
VLF3012AT-4R7MR74 VLF4012AT-4R7M1R1
Murata
LQH32PN4R7NN0 DO1605T-472MX
Coilcraft
DO3314-472ML ME3320-472MX
3/15
Low drop output regulators
AN2534
2
2.1
Low drop output regulators
VPLL
By default, VPLL is on at startup and set to 1.8 V, output VPLL capacitor is mandatory.
2.2
VANA
By default, VANA is on at startup and output voltage is fixed to 2.5 V, output VANA capacitor is mandatory.
2.3
VBAT_VPLL_VANA
As VPLL and VANA are on at start up, the VBAT_VPLL_VANA input capacitor is mandatory.
2.4
VAUX on STw4811N
By default on the STW4811N, VAUX is on and set to 1.5 V, output capacitor is mandatory.
2.5
VAUX on STw4811M
By default on the STw4811M, VAUX is off. If VAUX is never used and never turned on in the application:
VAUX output ball must be left open. VAUX output capacitor is not needed.
Pdn_vaux (configuration register 1, bit 7) and vaux_sel bits (power control register 06h, bit 2 and bit 3) must be left to default state 0.
2.6
Typical application schematic for minimal use on STw4811N
Figure 3. Typical application schematic for minimal use on STw4811N
VBAT
D 10 C7 B6
VBAT_ ANA VBAT_ VPLL _ VANA VBAT_ VAUX
VPLL VANA VAUX
A8 A7 A6
VPLL VANA VAUX
C3
C 14
C 15
VREF
A9
C8 B6 VMINUS _ ANA
C13
C7
C6
4/15
AN2534
Low drop output regulators
2.7
Typical application schematic for minimal use on STw4811M
Figure 4. Typical application schematic for minimal use on STw4811M
VBAT D10 C7 B6 C3 C14
VBAT_ ANA VBAT_VPLL _ VANA VBAT_VAUX
VPLL VANA VAUX
A8 A7 A6 A9 C8 C7 C6
VPLL VANA
VREF
B6
VMINUS _ ANA
Table 5.
Name C3 C14
Component list
Typ. 10 F 1 F See Table 6 for recommended LDO input decoupling capacitors Comments Function VBAT_ANA decoupling VBAT_VPLL_VANA decoupling VBAT_VAUX decoupling VPLL output filter 1 F See Table 7 for recommended LDO / reference output filter capacitors ANA output filter VREF output filter VAUX output filter
C15 C6 C7 C8 C13
Table 6.
Supplier Murata Murata
Recommended LDO input decoupling capacitors (10F)
Part number GRM188R60J106 GRM21BR60J106 Voltage (V) 6.3 6.3 TC code X5R X5R Package 0603 0805
Table 7.
Supplier Murata Murata Murata
Recommended LDO input decoupling capacitors / output filtering (1F)
Part number GRM155R60J105 GRM185R60J105 GRM188R60J105 Voltage (V) 6.3 6.3 6.3 TC code X5R X5R X5R Package 0402 0603 0603
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USB/OTG module
AN2534
3
3.1
USB/OTG module
LDO regulator
VUSB is off at startup, so output VUSB must be left open and the VUSB capacitor is not mandatory. When the USB registers are accessed, VUSB is turned on, so if no capacitor is connected to VUSB, the USB registers must not be accessed. Three conditions must be respected: 1. 2. 3. Do not use the USB I2C bus. Do not control the I2C registers by the main I2C interface, always leave usb_i2c_ctrl bit (power control register at address 06h, bit 1) at default state 0. Leave VBUS floating and leave ID either open or connected to VBAT.
3.2
Charge pump
At startup, the VBUS charge pump is off. If VBUS is never turned on:
the VBUS capacitors are not needed and VBUS must be left open the charge pump capacitor is not needed
3.3
3.3.1
USB OTG transceiver
I2C interface
If the USB OTG transceiver is never used, USBSDA and USBSCL lines are not used by the application. Those wires must be connected to a high level (VIO_VMEM). Never access the USB registers through the main I2C interface, always leave usb_i2c_ctrl bit (power control register at address 0x06, bit 1) at default state 0.
3.3.2
Digital signals
USBOEn: when not used, the USB transceiver is clamped in data transmit mode. As the USBOEn ball is pulled down internally by a 1.5 M resistor, this ball can be connected to a low level or can be left open. USBVP and USBVM: as the USB transceiver is clamped in transmit mode, the level on these balls must be defined. These balls are internally pulled down by 1.5 M resistors, so they can either be left open or be connected to ground. USBRCV: this ball is always in output mode. When not used, it must be left open. IT_WAKE_UP: this ball is in output mode. When not used, it must be left open. USB_INTn: this ball is in output mode. When not used, it must be left open.
3.3.3
USB signals
DP and DM: as the USB transceiver is clamped in transmit mode, these balls must be left open. ID: this input ball is internally pulled up to VBAT_USB. It can be either left open, or connected to VBAT_USB.
6/15
AN2534
USB/OTG module
3.4
Typical application schematic for non-use of USB OTG transceiver
Figure 5. Typical application schematic for non-use of USB OTG transceiver
VBAT
D1 P9
VBAT _ DIG VBAT _ USB
CP CM
H10 J10
C18
C3 J9 VMINUS VMINUS
_ DIG _ USB
VBUS VUSB
G10 F10
G9 VIO_MEM H9
USBSCL USBSDA D+ DID E9 E10 E8
VBAT
J7 J8 K8 K7 C2
USBVP USBVM USBOEn USBRCV IT
_ WAKE _ UP
Table 8.
Name C18
Components list
Typ. 1 F Comments See Table 9 for recommended VBAT decoupling capacitors Function VBAT_DIG decoupling
Table 9.
Supplier Murata Murata
Recommended VBAT decoupling capacitors (1F)
Part number GRM185R06J105 GRM188R06J105 Voltage (V) 6.3 6.3 TC code X5R X5R Package 0603 0603
7/15
SD/MMC/SDIO module
AN2534
4
4.1
SD/MMC/SDIO module
Linear regulator
The VMMC is off at startup, output VMMC must be left opened and the VMMC capacitor is not mandatory. To avoid issues, VBAT_MMC must be connected to the other VBAT balls. Pdn_vmmc and vmmc_sel bits (configuration 1 register, address 11h, bit 0 to 3) must be left in default state 0.
4.2
Level shifters
As level shifters are not used, their input levels must be controlled. When the VMMC regulator is not enabled, its output level is internally pulled down. mmc_ls_status bit (configuration 1 register, address 11h, bit 4) must be left in its default state 0 (enabled) to keep pull-up/pull-down resistors.
4.2.1
Direction signals
The MMC interface direction balls are internally pulled down and the SD/MMC interface is in CARD to APE direction. These four balls MCCMDDIR, MCDATA0DIR, MCDATA31DIR and MCDATA2DIR can be left open.
4.2.2
MCCLK/CLKOUT signals
MCCLK is internally pulled down. This ball is always an input so it can be left open. CLKOUT ball is set to 0 so this ball must be left open.
4.2.3
LATCHCLK/MCFBCLK signals
LATCHCLK is internally pulled down. This ball is always an input so it can be left open. MCFBCLK is in output mode ball must be left open.
4.2.4
Bidirectional signals
As level shifters directions are CARD to APE, CMDOUT and DATAOUT[0:3] balls are in input mode, and MCCMD and MCDATA[0:3] are in output mode because mmc_ls_status bit is set to 0 and direction signals are at low level. CMDOUT and DATAOUT[0:3] balls are internally pulled to VMMC so they should be left open. MCCMD and MCDAT[0:3] balls are in output mode, and so must be left open.
8/15
AN2534
SD/MMC/SDIO module
4.3
Typical application schematic for non-use of SD/MMC/SDIO module
Figure 6. Typical application schematic for non use of SD/MMC/SDIO module
VBAT
J4
VBAT _VMMC VMMC
K5
G3 K2 K9 H4 G2 H1 K1 H3 J1 H2 H5
MCCMDDIR MCDATA 0DIR MCDATA 2 DIR MCDATA 3 DIR MCCLK MCCMD MCDATA 0 MCDATA 1 MCDATA 2 MCDATA 3 MCFBCLK CLKOUT CMDOUT DATAOUT 0 DATAOUT 1 DATAOUT 2 DATAOUT 3 LATCHCLK
G1 F2 E1 E2 E3 F1 F3
9/15
Digital control
AN2534
5
5.1
5.1.1
Digital control
Mandatory static control signals
PON
The PON signal is mandatory for the STw4811N/STw4811M to startup. The IC can operate when PON is connected to high (VBAT) level.
5.1.2
SWRESETn
The SWRESETn ball controls the internal registers (except power control registers). Registers are reset to their default state when this ball is at a low level.
5.1.3
PORn
The PORn output ball is used to reset the application processor in the case of an issue (under voltage on VCORE/VIO_VMEM or high temperature interrupt).
5.1.4
PWREN
The PWREN input ball controls normal mode / sleep mode. If this ball is left open, the STw4811N/STw4811M is always in high power mode.
5.1.5
CLK32K_IN
This ball (32 kHz input) must be connected to 1.8 V 32 kHz clock signal.
5.1.6
I2C interface
The I2C interface is industry standard compliant, and must be connected to an I2C bus.
5.1.7
Reserved pins
Reserved balls B9 and D3 must be connected to ground. Reserved balls B1, B7, B8, C5, F8, G8 and K10 must be left open.
10/15
AN2534
Digital control
5.2
5.2.1
Other signals
Master clock
When the master clock is not used, MASTER_CLK input ball must be connected to ground. The REQUEST_MC output ball and TCXO_EN input ball (pulled down) can be left open.
5.2.2
GPO
When not used, the GPO1 and GPO2 output balls can be left open.
5.2.3
32 kHz output
If CLK32K is not used in the application, this ball can be left open.
5.3
Typical application schematic for minimal use of digital interface
Figure 7. Typical application schematic for minimal use of digital interface
C8 A1
PON CLK 32 KIN SW RESETn VDDOK PORn PW REN SCL SDA
MASTER_CLK
TCXO _EN REQUEST _ MC CLK 32 K GPO 1 GPO 2
C1 B2 K3 J5 K6
Digital control
K4 J2 J3 H6 J6 H7 D2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
G8
B9
B1
B7
B8
C5
F8
K10
D3
Reserved
11/15
Summary
AN2534
6
6.1
Summary
Unused ball status
Table 10.
Ball Control balls C1 B2 D2 K3 TCXO_EN REQUEST_MC MASTER_CLK CLK32K To GND O PEN To GND OPEN Output Internal pull down Output
Unused ball status
Ball name S t a tu s Comment
Regulator balls B6 A6 USB balls C2 K8 J7 J8 K7 E9 E10 E8 H10 J10 G10 F10 G9 H9 H8 IT_WAKE_UP USBOEn USBVP USBVM USBRCV DP DN ID CP CN VBUS VUSB USBSCL USBSDA USBINTn O PEN To GND To GND To GND O PEN O PEN O PEN To VBAT O PEN OPEN OPEN O PEN To VIOVMEM USB I2C bus must not be used To VIOVMEM O PEN Output No output capacitor needed if not used No capacitor needed if charge pump is not used Output Internal pull down Internal pull down Internal pull down Output Output Output Internal pull up VBAT_VAUX VAUX To VBAT OPEN(1) Connected with other VBAT No output capacitor needed if not used
SD/MMC/SDIO balls G3 K2 K9 H4 G2 MCCMDDIR MCDAT0DIR MCDAT2DIR MCDAT31DIR MCCLK To GND To GND To GND To GND To GND Internal pull down Internal pull down Internal pull down Internal pull down Internal pull down
12/15
AN2534 Table 10.
Ball H5 H1 K1 J1 H2 F3 G1 F2 E1 E2 E3 F1 J4 K5 Other balls J5 K6 B9 D3 B1 B7 B8 C5 F8 G8 K10 GPO1 GPO2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OPEN OPEN To GND To GND O PEN O PEN O PEN OPEN O PEN OPEN O PEN Output Output
Summary Unused ball status (continued)
Ball name MCFBCLK MCCMD MCDATA1 MCDATA2 MCDATA3 LATCHCLK CLKOUT CMDOUT DATAOUT0 DATAOUT1 DATAOUT2 DATAOUT3 VBAT_MMC VMMC OPEN OPEN O PEN O PEN O PEN To GND OPEN To VMMC To VMMC To VMMC To VMMC To VMMC To VBAT OPEN S t a tu s Output Output Output Output Output Internal pull down Output Internal pull to VMMC Internal pull to VMMC Internal pull to VMMC Internal pull to VMMC Internal pull to VMMC Connected with other VBAT No output capacitor needed if not used Comment
1. STw4811M only
6.2
Software considerations
usb_i2c_ctrl bit (power control register at address 06h, bit 1) must be left at default state 0. Pdn_vmmc, vmmc_sel and mmc_ls_status bits (configuration 1 register, address 11h, bit 0 to 4) must be left in default state 0. On the STw4811M, if VAUX is not used, pdn_vaux (configuration register 1, bit 7) and vaux_sel bits (power control register 06h, bits 2 and 3) must be left at default state 0.
13/15
Revision history
AN2534
7
Revision history
Table 11.
Date 27-Sep-2007
Document revision history
Revision 1 Initial release. Changes
14/15
AN2534
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