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AN2535 Application note
Generating a 32 kHz signal for a processor before PORn goes high
Introduction
This document provides guidance on generating a stable 32 kHz clock at VIO_VMEM level for a processor, before the PORn signal goes to a high level.
September 2007
Rev 1
1 /7
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Initial states and startup conditions
AN2535
1
Initial states and startup conditions
Handheld devices which use both application processor systems and an STw481x power management integrated circuit require a low power oscillator clock (LPO) to run properly. The possible ways to obtain a stable 32 kHz LPO clock are:
from a dedicated oscillator, or from the regular RTC output which normally runs all the time.
Since this LPO clock runs permanently, it should be powered by VBAT or some other backup battery.
1.1
Battery powered 32 kHz oscillator without open-drain output
The circuit shown in Figure 1 is powered from a battery using a dedicated 32 kHz oscillator or an RTC with a 32 kHz output. When the application is ready to start, VIO_VMEM is present and the single-gate open-drain buffer shown in Figure 1 drives the clock to the devices with the appropriate level. In the STw481x, VIO_VMEM supplies the CLK32K_IN pin. This input is referenced to VIO_VMEM. Figure 1. Battery powered 32 kHz oscillator without open-drain output
VBAT VIO_VMEM
74LX1G07 VCC 47K
A VCC OUT NC
Y
STw481x CLK32K_IN
GND
ENA
GND
32 . 768 kHz
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AN2535
Initial states and startup conditions
1.2
Battery powered 32 kHz oscillator with open-drain output
Figure 2. Battery powered 32 kHz oscillator with open-drain output
VBAT VIO_VMEM
47K
STw481x CLK32K_IN Open drain output VCC OUT
ENA
GND
32.768kHz
When a permanent 32 kHz signal from an RTC is used, the input level of this clock is VBAT unless there is an open-drain capability versus another supply such as VIO_VMEM. Care must be taken since pin CLK32K_IN depends on VIO_VMEM which is only present if PON has been issued. The following conditions must be respected: 1. 2. If the clock has VBAT level or any other non-VIO_VMEM level, level shifting should be added while applying the LPO clock to the device. No input should be applied to a device that is not powered or partially powered. This condition arises when STw481x is OFF (PON = 0) as there is no VIO_VMEM. Thus, the interface between clock and device requires an open-drain type device, otherwise there is a possible back-drive condition by one of the devices inputs.
Early stability of the 32 kHz signal can be an issue since most of the oscillator IPs require between 300 ms and (possibly more than) 800 ms to stabilize. Since in many applications this clock measures the system clock, this clock must be within the specifications whenever an application processor goes out of reset. Therefore, the use of a permanent LPO clock is of interest if an immediate stable frequency is required.
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Initial states and startup conditions
AN2535
1.3
Measurements with the STw4811N/STw4811M
Figure 3 shows the STw4811N/STw4811M configuration at startup with 32 kHz output of a single open-drain gate permanently supplied pulled-up by the STw4811N/STw4811M VIO_VMEM power supply.
Figure 3.
VBAT
Measurement set-up and results: open-drain buffer, VIO_VMEM pull-up
VIO_VMEM Chan_2 Chan_1 74LX1G07 VCC 47K VIO_VMEM PORn
STw481x
CLK32K CLK32_ _OUT K
Chan_4
A VCC OUT NC
Y Chan_3 GND
ENA
GND
32.768kHz
PC00185
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AN2535
Application processor considerations
2
Application processor considerations
Some application processors need a 32 kHz clock to be present before de-asserting the reset. On the STw481x, CLK32K output is only present when the reset signal PORn releases the processor from a reset condition. This issue can be solved with an open-drain buffer (either a low-power oscillator with opendrain capability or a single gate such as 74_1G_07) which uses the VIO_VMEM level to propagate this clock permanently whenever VIO_VMEM is on. If the RTC or 32 kHz oscillator has open-drain capability, the additional single-gate buffer is not required. Figure 4. Battery powered 32 kHz oscillator without open-drain output
VBAT VIO_VMEM
74LX1G07 VCC 47K
A VCC OUT NC
Y
STw481x CLK32K_IN Application processor 32kHz clock input
GND
ENA
GND
32 . 768 kHz
The value of the resistor used in the open-drain feature is a compromise between consumption and signal quality. Actually, the output follows an RC time constant context, where R is the pull-up value and C is the capacitance of PCB tracks and IOs.
High R value leads to lower consumption but the signal rise and fall times can be out of specification ranges since the time constant is high. Low R value leads to a nicer signal shape with a low time constant but with increased consumption.
If the device clock inputs have Schmitt trigger capability, the value can be very high and no issue should arise.
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Conclusion
AN2535
3
Conclusion
Care should be taken about where the 32 kHz oscillator output comes from, and its level: from modem or oscillator, and with or without open-drain capability. STw481x's CLK32K_IN should not be driven when VIO_VMEM is off. Level shifters should be inserted if there is a mismatch. When the application processor requires a 32 kHz clock signal before de-asserting a reset, CLK32K should be supplied to the processor following the configurations illustrated in this document prior to PORn toggling high (and not using the CLK32K_OUT from STw481x).
4
Revision history
Table 1.
Date 27-Sept-2007
Document revision history
Revision 1 Initial release. Changes
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AN2535
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