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AN2536 Application note
STw481x SD/MMC interface Interfacing a mass storage card with the STw481x
Introduction
This document provides guidance on how to interface the STw481x with both secured digital (SD) cards and MultiMedia mass storage cards (MMC). STw481x covers STw4810, STw4811N and STw4811M part numbers. It details:
The STw481x SD/MMC interface Feedback clock usage and direction switching Interfacing between the digital control, the STw481x and the SD/MMC card Application schematics High speed interface layout constraints
September 2007
Rev 1
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SD/MMC interface considerations
AN2536
1
SD/MMC interface considerations
Secured digital cards and MultiMedia cards use the same bus topology:
One clock line One bidirectional command (CMD) line One or four bidirectional data lines (DATA0 to DATA3)
As the CMD and DATA lines are bidirectional, two clock cycles are allowed to change the direction of the interface buffers. See pages 70 to 76 in MultiMedia Card System Specification Version 4.1 and pages 75 to 80 in SD Specifications Part 1, physical layer version 1.1. When bidirectional lines are idle, they are pulled-up.
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STw481x considerations
The STw481x SD/MMC interface is composed of level shifters, drivers and an LDO to interface various voltage cards to the 1.8 V APE interface. Figure 1. STw481x block diagram
MCCMDDIR MCDATA 0 DIR MCDATA 2 DIR VBAT _ VMMC
VIO_VMEM
MCDATA 31 DIR
VMMC LDO
VMMC
STw4811 only
MCCLK
CLKOUT
MCCMD
CMDOUT
MCDATA 0
DATAOUT 0
MCDATA 1
DATAOUT 1
MCDATA 2
DATAOUT 2
MCDATA 3
DATAOUT 3
MCFBCLK
LATCHCLK
2.1
VMMC LDO signal from the STw4810
The card power supply is provided by the VMMC LDO, with a voltage range of 1.8 V to 3.0 V. This regulator also supplies the interface drivers on the card side of the transceiver. The voltage value is selected by bits vmmc_sel[1:0] (bits 2 to 1 in the SD MMC control register at address 11h). The regulator is turned on by setting bit pdn_vmmc (bit 0 in the SD MMC control register at address 11h).
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2.2
VMMC LDO signal from the STw4811
The card power supply is provided by the VMMC LDO, with a voltage range of 1.8 V to 3.3 V. This regulator also supplies the interface drivers on the card side of the transceiver. Input of this regulator VBAT_VMMC can be greater than other VBAT levels, for example via an external step-up converter, to keep high voltage output (ex: 3.3V) even if the battery voltage is too low. The voltage value is selected by bits vmmc_sel[2:0] (bits 3 to 1 in the configuration 1 register at address 11h). The regulator is turned on by setting bit pdn_vmmc (bit 0 in the configuration 1 register at address 11h). Level shifters operate when bit mmc_ls_status is set to 0 (bit 4 in the configuration 1 register at address 11h). When this bit is set to 1, level shifters are in high impedance status. An external regulator can be used instead of the internal VMMC LDO to supply interface drivers and level shifters on the card side. To enable this feature (and so disconnect VMMC LDO output), bit 1 of configuration 2 register (address 20h) external_vmmc must be set to 1.
2.3
Level shifters and drivers
One unidirectional line MCCLK:CLKOUT for clock from the application processor engine (APE) to the card. One bidirectional line MCCMD:CMDOUT for commands between the APE and the card, with its direction control signal MCCMDDIR. When MCCMDDIR is at a low level, the driver is in the position Card to APE. Four bidirectional lines MCDATA[0:3]:DATAOUT[0:3] for data between the APE and the card, with three direction control signals MCDATA0DIR, MCDATA2DIR and MCDATA31DIR. When the direction control balls are at a low level, the drivers are in the position Card to APE. One unidirectional line MCFBCLK:LATCHCLK for the feedback clock. MCCMD and MCDATA[0:3] lines are internally pulled up to VIO_VMEM level. MCCLK line is pulled down. CMDOUT and DATAOUT[0:3] are internally pulled up to VMMC level. LATCHCLK line is pulled down.
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Feedback clock usage
3
3.1
Feedback clock usage
APE to card transfer
On the application processor engine (APE) side, during command or data transmit; MCCLK and MCCMD/MCDATA are synchronized. As propagation delays are matched in the STw481x, CLKOUT and CMDOUT/DATAOUT are synchronized. Figure 2. APE to card transfer
MCCLK MCCMD / MCDATA Propagation delay APE to CARD CLKOUT CMDOUT /DATAOUT
3.2
Card to APE transfer
During data receive from the card, command/data CMDOUT/DATAOUTx from the card are synchronized by the card with the CLKOUT signal. But the CLKOUT signal is delayed from the MCCLK signal, due to propagation delay in the STw481x. Command/data are delayed in the paths CMDOUT:MCCMD and DATAOUTx:MCDATAx, therefore on the APE side, the MCCMD and MCDATAx signals are not synchronized with the MCCLK clock, due to two propagation delays, one for the clock and one for command/data. As propagation delays at high frequencies are large compared to the clock period, command/data can be invalid during sampling from the APE, and undefined due to the dependency on the period of clock signal. To avoid such problems the feedback clock must be used, to provide a delayed clock signal in the path CARD:APE. This path is LATCHCLK:MCFBCLK. On the card side, the CLKOUT and LATCHCLK balls must be connected together. As the CMDOUT/DATAOUTx signals are synchronized with the CLKOUT signal (and LATCHCLK signal), all signals are also delayed in the path CARD:APE, and MCCMD and MCDATAx are synchronized with the MCFBCLK signal. On the APE side, from a digital point of view, commands and data from the card must be sampled on the MCFBCLK clock, and not on the MCCLK clock. Figure 3. Card to APE transfer
MCCLK Propagation delay APE to CARD CLKOUT CMDOUT / DATAOUT LATCHCLK Propagation delay CARD to APE MCCMD / MCDATA MCFBCLK
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Direction switch considerations
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4
Direction switch considerations
As the STw481x requires some time to switch direction on level shifters and drivers, the direction must be set at least one clock cycle before command/data transmission. SD card and MMC norms allow two HighZ periods to switch direction of interfaces. As soon as the last bit is sent from the APE, the direction must be switched to prepare to receive from card. Figure 4. Timing diagrams conventions
z STw 481 x direction change. Host line must be in HighZ state Data
Z S S P Z T T P
High impedance state Data from host (APE ) to Card Data from Card to host (APE) Line pulled up by Card
4.1
CMD line, response after command
Figure 5. CMD line response after command
CLK CMD content Z ZST Content CRC Host (APE) active EZ ZP *** PST Content Card active Z Z
CMDDIR CMD
4.2
CMD and DATA lines, block read
Figure 6. CMD and data lines block read
CLK CMD content Z DATA content Z Z Z ST Z Z Z Content *** CRC Z EZ Z Z Z Z P P *** PST Content Card active *** PSDD Card active Z Z
Host (APE) active Host (APE) active CMDDIR DATADIR CMD DATA
***
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4.3
CMD and data lines, single block write
Figure 7.
CLK CMD content CRC E Z Card active DATA content P *P Z Z ZPP P *P S Data + CRC EZ Host (APE) active Z S *** Status ES L*L Card active EZ P *P
CMD and data lines single block write
CMDDIR DATADIR CMD DATA
4.4
CMD and DATA lines, multiple block write
Figure 8.
CLK DATA content Data + CRC E Z Host (APE) active DATADIR DATA ZS Status + Busy Card active EZ P *P S Data + CRC Host (APE) active EZ ZS Status Card active
CMD and DATA lines, multiple block write
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Digital / STw481x / SD/MMC card interfacing
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5
5.1
Figure 9.
Digital / STw481x / SD/MMC card interfacing
Interface schematics
Interface schematics
VBAT J4 C17 G3 K2 K9 H4 G2 H1 K1 H3 J1 H2 H5 VBAT _ VMMC VMMC MCCMDDIR MCDATA 0 DIR MCDATA 2 DIR MCDATA 3 1 DIR MCCLK MCCMD MCDATA 0 MCDATA 1 MCDATA 2 MCDATA 3 MCFBCLK CLKOUT CMDOUT DATAOUT 0 DATAOUT 1 DATAOUT 2 DATAOUT 3 LATCHCLK G1 F2 E1 E2 E3 F1 F3 A4 B4 C4 C3 D4 D3 MMCclk MMCcmd MMCdat 0 MMCdat 1 MMCdat 2 A3 VMMC K5 C12
to be as close as possible to the card
Digital control
dat 1 dat 0 clk cmd dat 3
B1 B2 A2 A1
D1 EMIF 06 C1 MMCdat 3 HMC 01 F 2 dat 2 G ND G ND G ND
8 7 6 5 4 3 2 1 9
DAT 1 DAT 0 VSS CLK VDD VSS CMD DAT3 DAT2
C2
B3
5.2
Layout constraints
As the interface speed can be as high as 52 MHz the routing of the interface is important. It is recommended to minimize vias and PCB layers change. Track lengths should be kept as short as possible. If vias are used on signal paths, it is recommended to have the same number of vias on all lines (clock, command and data lines), in order to have the same behavior on all lines.
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Revision history
6
Revision history
Table 1.
Date 27-Sep-2007
Document revision history
Revision 1 Initial release. Changes
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