AN2559 Application note
System power supply board for digital solutions
Introduction
This document describes a power supply reference board designed for powering digital applications, such as CPUs, FPGAs, memories, etc. The main purpose of the board is to illustrate the basic principles used for the design of the power supply and to give designers a usable prototype for testing and use. The trend in recent years in the supplying of power to MCUs, CPUs, memories, FPGAs, etc. is to reduce the supply voltage, increase the supply current and provide different voltage levels for different devices in one platform. A typical example of this situation is the FPGA. The FPGA contains a core part which works at a low level voltage, the interface part placed between the core and the output, the system part, etc. It is important to note that each FPGA family has a slightly different voltage level and the trend is to decrease the voltage for each new family. The lowest operating voltage currently available is 1 V, and this can be expected to decrease to 0.9 V or 0.8 V in the near future. A similar situation exists with other digital applications. Typically, the main CPU, memory and interfaces require different supply voltage levels. Low operating voltages also present another challenge - transient. Digital devices are typically sensitive to voltage level. If the voltage drops below or crosses over a specific limit, the device is reset. This limit is typically 3 or 5%. On the other hand, digital device consumption can change very quickly (several amps in a few hundred nanoseconds). A power supply must be able to react very quickly with a minimum of over (or under) voltage, especially in cases where very low output voltage is required. There is additional stress placed on power supplies for digital applications in the industrial environment. The industrial standard bus is 24 V, but this voltage fluctuates and the maximum input voltage level required can reach 36 V. Additional surge protection is also a mandatory part of power supply input for industrial applications. The goal of the board described in this application note is to cover all of the issues outlined above. It is intended mainly to satisfy industrial input requirements (operating voltages up to 36 V) and generate several output voltages for mid-range power applications (up to several amps). The main output voltage level can simply be set.
September 2007
Rev 1
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www.st.com
Contents
AN2559
Contents
1 2 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Input part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
PM6680A block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.0.1 3.0.2 3.0.3 Power management block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Star t-up/enable block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Step-down parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2
DC-DC converters based on the L5970AD . . . . . . . . . . . . . . . . . . . . . . . 14 Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 5 6
PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 PM6680A block - measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.1 6.1.2 6.1.3 6.1.4 Efficiency and light load consumption modes . . . . . . . . . . . . . . . . . . . . 23 Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Star t-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2
L5970AD blocks - measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.1 6.2.2 6.2.3 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 8
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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AN2559
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. The STEVAL-PSQ001V1 demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block diagram of System Supply board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Schematic of input part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Location and correct polarity of the input supply connector on the board . . . . . . . . . . . . . . 6 Electrical diagram of the PM6680A section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 The placement of the jumpers for start-up/enable settings. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Skip mode connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Jumper placement for VCORE voltage level setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Jumper placement for VI/O voltage level setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output voltages of L5970A parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Schematic of the two SMPS's based on the L5970AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Jumper placement for enable/disable function of analog output and output3 . . . . . . . . . . 16 Schematic of the reset circuit and board placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCB top layer layout and first internal layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PCB second internal layer and bottom layer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Efficiency of the dual step-down converter at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PM6680A consumption at no load condition, in the different modes . . . . . . . . . . . . . . . . . 24 Output voltage ripple in different modes of light load operation . . . . . . . . . . . . . . . . . . . . . 24 Output voltage ripple of VCORE at the minimum input voltage (5 V) . . . . . . . . . . . . . . . . . . 25 Output voltage ripple of VCORE at the maximum output voltage (36 V) . . . . . . . . . . . . . . . 25 Output voltage ripple of VI/O at the minimum input voltage (5 V) . . . . . . . . . . . . . . . . . . . . 25 Output voltage ripple of VI/O at the maximum input voltage (36 V). . . . . . . . . . . . . . . . . . . 26 Start-up without setting the sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Start-up with a set sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Load transient response on VCORE output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Load transient response on VI/O output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Efficiency of output 3, by input voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Efficiency of analog output, by input voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Analog 5 V - output voltage ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VSYS - output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Analog 3.3 V - output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VAUX 2.5 V - output voltage ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Transient response of VSYS based on the L5970AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Transient response of VAUX generated by the LDO KF25 . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Main characteristics
AN2559
1
Main characteristics
The main characteristics of the SMPS are listed below:
Input: 5 V - 36 V DC, surge protection Outputs: the performance of the 6 outputs are described in Table 1 below. Output voltages (positive version)
VOUT Selectable from: 0.9, 1.0, 1.2, 1.5, 1.8 or 2.5 V Selectable from: 1.0, 1.2, 1.5, 1.8, 2.5 V or 3.3 V 3.3 V 2.5 V 5V 3.3 V IOUT max 4 A continuous 6 A peak 2 A continuous 3 A peak 0.4 A (0.8 A peak) 0.4 A 0.8 A 0.15 A Tolerance 3% 3% 4% 2% 4% 2%
Table 1.
Label
Output1 (VCORE) Output2 (VI/O) Output3 VSYS Output3 VAUX Analog 5 V Analog 3.3 V
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AN2559
Description
2
Description
The System Supply board described in this application note is a dedicated design which illustrates a typical solution for complete system supply, and can also be used as a direct supply for customer solutions during the design process. Figure 1. The STEVAL-PSQ001V1 demo board
The block diagram of the System Supply board is shown in Figure 2. There are four DC-DC converters, two linear regulators and a reset circuit. These parts are split into five relatively independent units: the input part, a dual DC-DC converter based on the PM6680A and generating 2 outputs (Output 1 and Output 2), two single DC-DC converters based on the L5970A (Output 3 and Output 4) with linear regulator, and the reset circuit. Figure 2. Block diagram of System Supply board
STM6719 Reset signal
Input 5 - 36 V
Input
protection
E/D analog L5970AD Analog 5 V analog 500 mA 3.3 V analog 150 mA Output 3 Vsys 3.3 V 400 mA Vaux 2.5 V 400 mA Output 2 Vi/o 1.0 - 3.3 V 2 A Vi/o voltage settings Output 1 Vcore 0.9 - 2.5 V 4 A Vcore voltage settings
AI12693
LK112 M33
L5970AD Skip mode settings KF25 E/D Vsys + Vaux FB Vi/o
Vcore Vi/o
PM6680A
E/D + start up sequence settings
FB Vcore
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Description
AN2559
2.1
Input part
The input part shown in Figure 3 consists of the input connectors (industrial - J16 or power jack - J3), input storage capacitor (C1) and transil (D1). The input electrolytic capacitor and transil serve to reduce input voltage spikes (surge). Figure 3. Schematic of input part
Vin J16 J3 1 2 3 D1 SM6T39A C1 47 F / 50 V
AI12691
Figure 4 displays the placement of the input connectors on the board. The board can be supplied either from the jack connector (J3) or the industrial removable terminal plate (J16). The polarity of the input voltage must be correctly applied in accordance with the illustration in Figure 4. If the connection is made incorrectly, the input protection D1 shorts the input voltage. It should be pointed out that the total input current is about 4 A at maximum output power and minimum input voltage. Figure 4. Location and correct polarity of the input supply connector on the board
+ +
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3
Figure 5.
AN2559
VLD O
Vin
R9 3.3 C 17 100 nF R 29 51 k SH DN
PM6680A block
C 14 4. 7 F / 1 0 V C 15 470 nF C 16 3. 3 F / 3 5 V
R 37 47R Vin C 31 220 nF Q1 ST S4DN F 60 C 18 4.7 F / 50 V/X7R 6 5 9 4 3 ST PS1L40 11 PH ASE2 LGAT E2 C SENSE2 14 V5SW R 39 3.3 k R 11 560 R 2 C 20 1.8 nF PGOO D2 F B2 C21 91 pF U5 PM 6680 SH DN 5 SH DN 28 F B1 1 SGN D1 16 SGN D2 PGOO D1 7 VLD O R 28 10 k 27 26 C OMP2 C OMP1 30 VLD O R 32 10 k OU T2 OU T1 29 C 22 330 F / 6.3 V 8 PGN D Q3 ST S7NF 60L C SENSE1 20 R 19 1 k D9 ST PS1L40 C 26 2.2 nF R 20 680 R LGAT E1 15 R 22 0R PH ASE1 8 7 R 24 0R 13 2 1 17 R 10 1.8 k 12 D8 21 L4 3. 8 H / 6 A R 27 62 k C 34 12 nF C 29 330 F / 6.3 V R 38 3.3 k C 28 330 F / 6.3 V L3 C 35 10 nF R 40 100 k 5. 0 H / 3 A H GATE2 H GATE1 R 23 0R 10 22 BOOT 2 C 19 100 nF R 25 10R R 26 10R 23 BOOT 1 R 21 0R C 23 4.7F / 50 V / X7R C 25 100 nF Q2 ST S7NF 60L Vin D7 BAW 56/ SOT
D 10 4V7
C 41 4.7 F / 50 V/X7R
31 VCC Vi n LD O 5
18 19
C 24 4.7F / 50 V / X7R V c ore R 206 6.8 k S17 2. 5 V S16 1. 8 V S15 1. 5 V S14 1. 2 V S13 1V
Vio
S9 1V
S10 1. 2 V
S11 1. 5 V
S12 1. 8 V
S8 2. 5 V R 109 3.3 k
R 110 4.7 k
R 105 200 R
C 39 22 F / 6.3 V
R 205 200 R C 40 22 F / 6.3 V R 204 3 k C 27 120 pF R 203 3 k R 202 R 201 2 k 1 k R 207 9.1 k R 208 820 k
Electrical diagram of the PM6680A section
R 101 1 k
R 102 2 k
R 103 R 106 R 104 3 k 6.8 k 3 k
R 107 9.1 k
R 108 820 k
EN 2 4 25
S5 S6 S7
EN 1 SK I P VR E F F SE L N C 32 24 3 6
3
VLD O S3 1 C H2 EN/SUS R 31 10 k
VLD O
2
3
R 34 10 k R 35 51 k
2 S4 1
SKI P mode
C H1 EN/SUS R 36 51 k C 30 100 nF
AI14512
PM6680A block
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PM6680A block
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The PM6680A block is most important part of board. It contains two DC-DC converters. Each output has a selectable output voltage level. The first converter is capable of delivering up to 4 A for each voltage level, while the second converter can deliver up to 2 A on the output. Both converters are controlled by the PM6680A device. The PM6680A is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. The pulse skipping technique increases efficiency at very light loads. Moreover, a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues. The PM6680A provides a selectable switching frequency, allowing either 200 / 300 kHz, 300 / 400 kHz or 400 / 500 kHz operation of the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0.9 V to 5 V and from 0.9 V to 3.3 V, respectively. A detailed description of this device can be found in the datasheet. Figure 5 shows the full electrical diagram of the block with the PM6680A that controls the two DC-DC converters. The components around the PM6680A form several functional blocks: the power management block, VCORE step down block, VI/O step down block and start-up/enable control system block.
3.0.1
Power management block
The PM6680A has two supply voltage inputs - VCC and VIN. The VCC pin should be connected to the 5 V bus (maximum input voltage is 6 V, minimum 4.5 V) and it is dedicated for the supply of the chip itself. The VIN pin should be connected to the input power bus and it is used inside the chip for two reasons. The first is to supply the integrated LDO. The second is the fact that the controller must sense the converter input voltage level for proper functioning of the converter. The VCC pin is supplied from the integrated LDO (connected output of LDO and VCC) on the reference board. The V5SW feature of the LDO is disabled. The power management block consists of components C14 - C17, C31, R9, R29, R37 and D10. The important parts of the power management block of the device are the low pass filters (R9, C16, C17 and R37, C31) applied to reduce the influence of transience on the device VCC and VIN main power inputs. The resistor R29 and the diode D10 generate the SHDN (shut down) signal, which is active in low level. This signal activates the PM6680A immediately after VIN is connected to the input. The VREF and LDO signals start to work simultaneously with activation of the SHDN pin.
3.0.2
Start-up/enable block
The PM6680A has several inputs and outputs dedicated to the control of each channel. Each channel has an independent Enable signal (EN - active in high level) and "power good" signal (PGOOD - open collector) activated by channel in cases where the output voltage is within 10% tolerance. These control pins can be used either for simple enabling/disabling or for delaying the start-up of one channel rather than another. The jumpers S3 and S4 with resistors R28, R31, R32, R34, R35 and R36 are used for systems independently allowing either enabling or disabling of each channel or setting up a different start-up sequence of both channels. Figure 6 displays the placement of jumpers S3 and S4 on the board, and the settings are shown in Table 2.
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AN2559 Figure 6. The placement of the jumpers for start-up/enable settings
PM6680A block
Table 2.
V c o re 1st
Start-up/enable jumper settings
Function Both channels are disabled. An open connector for each channel means that the channel is disabled.
V c o re 1st
Jumper settings
V i/o
1st
V i/ o
Both channels are disabled.
V c o re 1st
1st
V i/o
Both channels are enabled and start at same time.
V c o re 1st
1st
V i/ o
VCORE voltage starts first, and VI/O starts second.
V c o re 1st
1st
V i/ o
VI/O voltage starts first, and VCORE starts second.
1st
The Skip mode connector (shown in the schematic as S5 - S7) is dedicated for the control of Skip mode. This connector setting is common for both channels. Figure 7 shows the placement of the Skip mode connector, while the settings are shown in Table 3. There are three possible settings. Standard Skip mode, No Audible mode or PWM mode. In Standard Skip mode the converter reduces the switching frequency at light load to maintain good efficiency even in this condition. There is no lower limit for switching frequency. In No Audible mode the converter reduces switching frequency at light load, but this frequency never drops below 30 kHz to avoid possible audible noise caused by the mechanical
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PM6680A block
AN2559
construction of passive components (inductors or ceramic capacitors). In PWM mode the converter maintains a constant switching frequency independently on the load. The FSEL pin the PM6680A dedicated for operating frequency setting is connected to GND. This means that the switching frequency of the VCORE branch is 200 kHz and switching frequency of VI/O is 300 kHz. Figure 7. Skip mode connector
Table 3.
Skip mode connector jumper settings
Function Skip mode at light load.
Jumper settings
S k ip A u d io PW M
S k ip
A u d io PWM
No Audible Skip mode at light load (frequency never drops below 30 kHz).
S k ip
A u d io PW M
PWM mode. Constant frequency even at light or zero load.
3.0.3
Step-down parts
The PM6680A is a dual step-down controller and drives two step-down converters. The schematic of both channels are almost identical, with only a few small differences. Since each channel is for a different output power, the main difference is in the components' values. Figure 8 displays the output connector polarities of the PM6680A section.
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AN2559 Figure 8. Output connector
PM6680A block
The power components of the step-down part are input capacitors (C23, C24 or C18, C41), the half bridge driver containing two N-channel MOSFETs (Q2, Q3 or Q1), inductors (L4 or L3) and output capacitors (C28, C29, C40 or C22, C39). Ceramic high-capacitance capacitors are used as input capacitors. 60 V MOSFETs are used for the half bridge driver. A relatively high breakdown voltage is used to guarantee operation in industrial applications. Because the VI/O output is designed for lower currents (2 A), both MOSFETs are integrated in one SO-8 package (Q1 - STS4NF60). This helps to reduce the size on the PCB. Two discrete MOSFETs (STS7NF60) are used for the VCORE higher power output (4 A). Schottky diodes are also used in each channel (D9 or D8). These diodes work mainly during dead time and are not mandatory for proper functioning, but their application increases efficiency. The 5 H inductor (L3) is used for the VI/O output with saturation current at 3 A. The inductor L4 has value of 3.8 H with saturation current at 6 A. A combination of tantalum low ESR and ceramic type are used as output capacitors. Ceramic capacitors help to reduce total output ESR and reduce total output voltage ripple. The PM6680A includes a half bridge driver for each channel. The external bootstrap diode and capacitor must be applied (D7, C19 or C25) in order to drive the gates of the high side MOSFETs. The feedback signal is generated by the output voltage divider (R10x or R20x). The board allows the setting of different output voltages for both channels. Figure 9 and Figure 10 display the output voltage connector placement on the board for each channel. The jumper settings are shown in Table 4 and Table 5, respectively. In classic Constant On Time control, the system regulates the valley value of the output voltage and not the average value. In this condition, the output voltage ripple is a source of DC static error. To compensate for this error, an integrator network is introduced in the control loop by connecting the signal output voltage to the COMP1/COMP2 pin through a capacitor (C20 or C26). An additional R-C network (R11 and C21 or R20 and C27) is implemented as a low pass filter to reduce noise on the input of the COMP pin. Since the feedback signal of the SMPS working in Constant On Time control is directly connected to the PWM comparator, the stability of the SMPS is more sensitive to noise injected into the FB signal. It is possible to attenuate the affect of the noise to stabilize the SMPS by implementing the so called "Virtual ESR" network, which increases the amplitude of the feedback ripple voltage and improves signal-to-noise ratio. The Virtual ESR network does not increase the output ripple voltage. It is recommended to use the Virtual ESR network in cases where the output voltage ripple is below 30 mV. However, it is necessary to
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PM6680A block
AN2559
take into consideration that the influence of noise on the performance of the SMPS strictly depends on the PCB layout. Therefore, the 30 mV is an indicative value. Virtual ESR Networks are applied for each channel on the reference board described in this application note. The main reason for this is the fact that the SMPS based on the PM6680A device can generate different output voltages at a wide input voltage range. As output voltage ripple depends also on input and output voltage level, there are configurations where the Virtual ESR network could be mandatory. Virtual ESR networks consists of R40, R39, C35 or R27, R38 or C34. The ESR network can be removed to observe influence of ESR network to board function. To remove the Virtual ESR Network, R40 and R27 must be removed and R39 and R38, respectively, must be shorted. Figure 9. Jumper placement for VCORE voltage level setting
Table 4.
VCORE voltage level jumper settings
Jumper settings VCORE 2.5 V 1.8 V 1.5 V 1.2 V 1.0 V 0.9 V
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AN2559 Figure 10. Jumper placement for VI/O voltage level setting
PM6680A block
Table 5.
VI/O voltage level jumper settings
Jumper settings VCORE 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V 1.0 V
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PM6680A block
AN2559
3.1
DC-DC converters based on the L5970AD
There are two converters based on the L5970AD on the System Supply board: the analog output and VSYS output voltage. Figure 11 shows the arrangement of output voltages on connector J18. Figure 11. Output voltages of L5970A parts
The L5970AD is a step-down monolithic power switching regulator with a switch current limit of 1.5 A, capable of delivering more than 1 A of DC current to the load depending on the application conditions. The output voltage can be set from 1.235 V to 35 V. The device uses an internal P-channel D-MOS transistor (with a typical RDSON of 200 m) as a switching element to avoid the use of a bootstrap capacitor and to guarantee high efficiency. An internal oscillator fixes the switching frequency at 500 kHz to minimize the size of external components. Having a minimum input voltage of only 4.4 V, it is particularly suitable for 5 V buses, found in all computer-related applications. Pulse-by-pulse current limiting with internal frequency modulation offers effective constant current short circuit protection. The schematic of both SMPS's is displayed in Figure 12. As the schematic shows, designing with the L5970AD is very simple. It consists of a power part, feedback and enable/disable connectors. The power part contains an input capacitor (C2 or C8 - ceramic is recommended), an inductor (L1 or L2), an output capacitor (C5 or C11) and a freewheeling diode (D4 or D6). The feedback part consists of a voltage divider (R2, R3, R4 or R6, R7, R8) and a compensation RC network (R1, C3, C4 or R5, C9, C10).
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AN2559
V in U 1 L 59 70 A D L 1 3 3 H / 1.5 A OU T 5 R2 1 20 k R3 2 0 k 1 U 2 L K 1 12 _3 3 5 1 3 B YPA SS C6 10 0 nF 2 GN D G N DA D4 S T P S 2 L4 0 R4 5.6 k C5 4 7 F / 10 V IN S H DN C7 1 0 F / 6 V OU T 4 V3 A3 V 5A 8 VCC C O MP FB V R EF S YN C G N D INH 2 6 7 3 4
C2 4. 7 F / 50 V C3 2 20 pF C4 2 2 nF S1 V a na log EN R 4 1 5 1 k V in L5 1 0 H / 1 A
R1 4.7 k
U 3 L 59 70 A D 8 VCC C O MP FB V R EF S YN C G N D INH 2 6 7 3 5 OU T 1 4
L2 33 H / 1.5 A U4 R6 18 k R7 2 40 k D6 S T P S 2 L4 0 R8 10 k C 11 10 0 F / 6 V C 12 10 0 nF 8 5 VIN I NH K F 25 _S O I C8 VO U T G ND G ND G ND G ND 236 7 1
V s ys V au x
C8 4. 7 F / 50 V C9 2 20 pF C 10 2 2 nF R5 4.7 k
C 13 1 0 F / 4 V
Figure 12. Schematic of the two SMPS's based on the L5970AD
S 2 V s ys EN
R 42 51 k
V in
Both converters can be switched on or off using the inhibit pin of L5970AD connected to jumpers S1 and S2. If the jumper is left open, the DC-DC converter will not operate. Thus the jumper must be shorted for the converter to operate (see Figure 13 for board placement of the jumper and Table 6 for the jumper settings).
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PM6680A block
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PM6680A block
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Figure 13. Jumper placement for enable/disable function of analog output and output3
Table 6.
Jumper settings for enable/disable function of analog output and output3
Jumper settings VCORE Analog disable
E /D
Analog enable
E /D
Output3 disable
E /D
Output3 enable
E /D
There is an LDO linear regulator (U2 and U4) on the output of each DC-DC converter. The LK112_33 is a 3.3 V linear regulator in a SOT23-5 package. The KF25 is a very low dropout regulator with an output voltage of 2.5 V and output current of up to 400 mA.
3.2
Reset circuit
The board also features a reset circuit which supervises the output voltages. It is based on the STM6719 series of low voltage / low supply supervisors, which are designed to monitor three system power supply voltages. Two monitored supplies (VCC1 and VCC2) have fixed (factory trimmed) thresholds (VRST1 and VRST2). The third voltage is monitored using an externally adjustable RSTIN threshold (0.626 V internal reference). If any of the three monitored voltages drop below its factory-trimmed or adjustable thresholds, or if MR is asserted to logic low, an RST is asserted (driven low). Once asserted, RST is maintained at Low for a minimum delay period after ALL supplies rise above their respective thresholds and MR returns to High. This device is guaranteed to be in the correct reset output logic state when VCC1 and / or VCC2 is greater than 0.8 V. This device is available in a standard 6pin SOT23 package.
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PM6680A block Figure 14 shows the schematic and placement of the reset part on the board. Typically in real applications the reset circuit senses if the supply voltage drops below about 10% of nominal value. This feature cannot be implemented on the System Supply board due to the fact that the output voltage is selectable, while the reset voltage is factory set. There are several types of reset circuits in the STM6719 family (see datasheet). Of these, the STM6719TGWB6F was selected as optimal. The voltage thresholds of this device are 3.075 V, 1.11 V and 0.626 V. Figure 14. Schematic of the reset circuit and board placement
Vsys U6 STM6719TEWB6F 6 Vio Vcore 4 5 3 MR C32 1 nF C33 1 nF J15
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R209 110 k 1 J14 Reset
VCC1 VCC2
RST
RSTIN VSS 2
Reset GND
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PCB layout
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4
PCB layout
The System Supply board utilizes a four-layer PCB. The copper layout of each layer is shown in Figure 15 and Figure 16. The top and bottom layers show also the placement of the components. To reduce the size of board while maintaining the ability to change some components, size 0603 was used for the majority of the passive components. All views of the PCB are from top side. Figure 15. PCB top layer layout and first internal layer
Figure 16. PCB second internal layer and bottom layer layout
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Bill of materials
5
Table 7.
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Bill of materials
Bill of materials
Part C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 Description 47 F / 50 V 4.7 F / 50 V 220 pF 22 nF 100 F / 10 V N.A. 10 F / 6 V 4.7 F / 50 V 220 pF 22 nF 100 F / 10 V 100 nF 10 F / 6.3 V 6.8 F / 10 V 470 nF 3.3 F / 50 V 100 nF 4.7 F / 50 V / X7R 100 nF 1.8 nF 100 pF 330 F / 6.3 V 4.7 F / 50 V / X7R 4.7 F / 50 V / X7R 100 nF 2.2 nF 120 pF 330 F / 6.3 V / 45 m 330 F / 6.3 V / 45 m 100 nF 220 nF 1 nF SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD B 1812 0603 0603 C 0805 B B 0805 1812 0603 1812 0603 0603 0603 D 1812 1812 0603 0603 0603 D D 0603 0805 0603 AVX AVX TPSD337M006X0045 TPSD337M006X0045 AVX AVX AVX TPSD337M006X0045 18125C475KAT2A 18125C475KAT2A AVX 18125C475KAT2A C1210C335K5RAC CTS 10 M / 6.3 V CTS 6 M 8 / 10 V AVX TPSC107M010X0150 AVX CTS 10M / 6.3 V 18125C475KAT2A Type TH SMD SMD SMD SMD Size 6.3 x 11 1812 0603 0603 C AVX TPSC107M010X0150 AVX Manufacturer Part number E47M/50VMXA RM5 18125C475KAT2A
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Bill of materials Table 7.
Item 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
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Bill of materials (continued)
Part C33 C34 C35 C39 C40 C41 D1 D4 D6 D7 D8 D9 D10 S1 S2 S3 S4 Description 1 nF 12 nF 10 nF 22 F / 6.3 V 100 F / 6.3 V 4 F 7 / 50 V / X7R SM6T39A STPS2L40 STPS2L40 BAW56/SOT STPS1L40M STPS1L40M 4.7 V Header 1 x 2 Header 1 x 2 Header 1 x 3 Header 1 x 3 Header 2 x 5 Header 2 x 5 Header 2 x 3 Jack - PCB Header 1 x 1 Header 1 x 1 Ind. Con. 2 Ind. Con. 4 Ind. Con. 6 33 H / 1.5 A 33 H / 1.5 A 5.0 H / 3 A 3.8 H / 6 A 1 H / 1 A STS4DNF60 STS7NF60L STS7NF60L 4. 7 k Type SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD TH TH TH TH TH TH TH TH TH TH TH TH TH SMD SMD SMD SMD SMD SMD SMD SMD SMD 0603 Ph. Con. Ph. Con. Ph. Con Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft ST ST ST MSTBA 2,5 / 2-G-5,08 MSTBA 2,5 / 4-G-5,08 MSTBA 2,5 / 6-G-5,08 MSS7341-333MLB MSS7341-333MLB MSS7341-502MLB MSS1038-382NLB ME3220-102MLB STS4DNF60L STS7NF60L STS7NF60L Size 0603 0603 0603 1206 1210 1812 SMB SMB SMB SOT23 DO216-AA DO216-AA SOD80 ST ST STPS1L40M STPS1L40M AVX AVX AVX ST ST ST 12066D226KAT2A 12104D107MAT2A 18125C475KAT2A SMA6T39A STPS2L40 STPS2L40 Manufacturer Part number
VI/O level VCORE level Skip J3 J14 J15 J16 J17 J18 L1 L2 L3 L4 L5 Q1 Q2 Q3 R1
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AN2559 Table 7.
Item 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
Bill of materials Bill of materials (continued)
Part R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R110 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R31 R32 R34 R35 R36 R37 R38 R39 R40 R41 R42 R101 R102 Description 36 k / 1% 200 k/ 1% 10 k / 1% 4.7 k 18 k / 1% 240 k / 1% 10 k / 1% 3.3 1.8 k 560 4.7 k / 1% 1 k 680 0 0 0 0 10 10 62 k 10 k 51 k 10 k 10 k 10 k 51 k 51 k 47 3.3 k 3.3 k 100 k 51 k 51 k 1 k / 1% 2 k / 1% Type SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD Size 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 Manufacturer Part number
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Bill of materials Table 7.
Item 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124
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Bill of materials (continued)
Part R103 R104 R105 R106 R107 R108 R109 R201 R202 R203 R204 R205 R206 R207 R208 R209 U1 U2 U3 U4 U5 U6 Description 3 k / 1% 3 k / 1% 200 / 1% 6.8 k / 1% 9.1 k / 1% 820 k / 1% 3.3 k / 1% 1 k / 1% 2 k / 1% 3 k / 1% 3 k / 1% 200 / 1% 6.8 k / 1% 9.1 k / 1% 820 k / 1% 51 k L5970AD LK112_33 L5970AD KF25_SOIC8 PM6680A STM6719TEWB6F Type SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD Size 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 SO-8 SOT23-5 SO-8 SO-8 VFQFPN32 5X5 SOT23-6 ST ST ST ST ST ST L5970AD LK112M33TR L5970AD KF25BD-TR PM6680A STM6719TGWB6F Manufacturer Part number
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Measurements
6
Measurements
The performance and properties of each part of the board is indicated in the measurements below. These measurements were performed for the PM6680A and L5971AD blocks independently.
6.1
PM6680A block - measurements
The performance measurements of the PM6680A part focus mainly on efficiency, light load consumption, output ripple and transients.
6.1.1
Efficiency and light load consumption modes
Since the device consists of three power parts (two controllers and one LDO) it makes sense to measure total efficiency. Figure 17 displays how efficiency depends on input voltage level at full load output (VCORE 2.5 V / 4 A, VI/O 3.3 V / 2 A). Figure 17. Efficiency of the dual step-down converter at full load
Efficency (%) 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0 5 10 15 20 25 30 35 40 Vin (V)
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The efficiency is in the range of 83 - 91%. It should be noted that the total efficiency strictly depends on the performance of each component. The System Supply board was designed to satisfy a wide input voltage range. Therefore, 60 V MOSFETS are used on the board. If the input voltage of the end application is less (up to 30 V for instance), efficiency can be improved by using lower RDSON 30 V MOSFETs in the same package. The expected efficiency gain is about 3 - 4%. The PM6680A can work in several modes with regard to light load. These options are mainly used for battery applications where relatively high consumption at light load can drain the battery even when no power is requested. The PM6680A allows three modes (see 3.0.2): PWM, No Audible Noise and Skip. Figure 18 shows the consumption of the board for different modes of the PM6680A. There is no load on the output and other parts of the SMPS are disabled.
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Measurements Figure 18. PM6680A consumption at no load condition, in the different modes
lin (mA) 70.0 60.0 50.0 40.0 30.0 20.0 No Audible 10.0 SKIP 0.0 0 5 10 15 20 25 30 35 40 Vin (V)
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PWM
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In analyzing the data in Figure 18, it should be noted that the consumption is slightly increased by several passive components which generate inhibit of the L5970ADs. Total consumption of these parts at 35 V on the input is about 1.5 mA. This is not compensated for in the chart in Figure 18. It is possible to see the effect of the different operating modes of the converter by observing the output ripple voltage waveforms in Figure 19. These measurements are made under the following conditions: VCORE output set to 2.5 V, no load, at 12 V on the input. Figure 19. Output voltage ripple in different modes of light load operation
6.1.2
Output voltage ripple
Output voltage ripple depends on the current ripple flowing through the choke. The current ripple depends on the input and output voltage levels. Therefore, it is mandatory to measure the output voltage ripple for different input and output voltage conditions. Figure 20 shows the output voltage ripple of VCORE at the minimum input voltage (5 V), while Figure 21 displays the output voltage ripple of VCORE at the maximum output voltage (36 V). Figure 22 shows the output voltage ripple of VI/O at the minimum input voltage (5 V), and Figure 20 displays the output voltage ripple of VI/O at the maximum input voltage (36 V). All of the figures represent the minimum and maximum output voltages at maximum load (0.9 V and 2.5 V at 4 A for VCORE, and 1 V and 3.3 V at 2 A for VI/O).
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AN2559 Figure 20. Output voltage ripple of VCORE at the minimum input voltage (5 V)
Measurements
Figure 21. Output voltage ripple of VCORE at the maximum output voltage (36 V)
Figure 22. Output voltage ripple of VI/O at the minimum input voltage (5 V)
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Measurements Figure 23. Output voltage ripple of VI/O at the maximum input voltage (36 V)
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Figure 24. Start-up without setting the sequence
Figure 25. Start-up with a set sequence
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Measurements
6.1.3
Start-up sequence
The correct start-up sequence of the supply voltage is typically requested by the FPGA device. Therefore, there it is possible to set a dedicated start-up sequence on the System Supply board (see 3.0.2. Figure 24) shows the start-up sequence waveform of VCORE and VI/O outputs when the jumpers described in Table 2 are set in accordance with line 3 in the table. The waveforms shown in Figure 25 illustrate different start-up sequences in accordance with the jumper settings displayed in Table 2, lines 4 and 5.
6.1.4
Transient response
Transient response refers to the behavior of the output voltage when the load changes fast. This test was also performed on the outputs of the PM6680A branch. The load was changed between maximum and zero load (0 2 A on VI/O output and 0 4 A on the VCORE output). The input voltage was 12 V and output voltage was 3.3 V and 2.5 V, respectively. The repetition of load change was 500 Hz. The results of the measurements are shown in Figure 26 and Figure 27. The voltage spikes caused by increasing the load are quite low. It is possible to observe that the converter reacts very fast to a rising load and the undervoltage is small (left waveform in figures). If the load is decreasing fast the overvoltage spikes appear on the output (right side of picture). This effect depends partly on the reaction of the controller and partly on the parameters of the output filter. There is remaining energy stored in the inductor and if the load decreases this energy should be stored in the output capacitor. This effect can be reduced by either reducing the value of the inductor (to reduce the amount of energy stored in the inductor), or by increasing the value of the output capacitor (a higher capacitance is capable of absorbing more energy from the inductor).
Figure 26. Load transient response on VCORE output
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Measurements Figure 27. Load transient response on VI/O output
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Measurements
6.2
6.2.1
L5970AD blocks - measurements
Efficiency
The L5970AD is a powerful converter with very good performance and efficiency. Because a diode is used as a low side switch, however, the efficiency is a slightly less compared to a synchronous converter such as the PM6680A. Theoretically, the efficiency declines when output voltage is decreasing and input voltage is increasing. Figure 28 displays the efficiency of Output 3, depending on the input voltage at full load (800 mA). Figure 29 displays the same measurement for the Analog output. The efficiency of the Analog output is better thanks to the higher output voltage level. The efficiency of the Analog output voltage was measured in a range of 7 - 35 V. It should be noted that the output voltage is 5 V, so the device does not work as a switching converter in cases where the input and output voltage are similar or lower than the required output. In this case the L5973AD works with 100% duty cycle. Figure 28. Efficiency of output 3, by input voltage level
Efficency (%) 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0 5 10 15 20 25 30 35 40 Vin (V)
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Measurements Figure 29. Efficiency of analog output, by input voltage level
Efficency (%) 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0 5 10 15 20 25 30 35 40 Vin (V)
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6.2.2
Output voltage ripple
The output voltage ripple of the switching parts of the Analog and VSYS outputs are shown in Figure 30 and Figure 31. The measurements were made for different input voltages, because the current ripple influence on the output voltage ripple depends on the input voltage level. The output voltage ripple on the 3.3 V Analog output and the VAUX output are displayed in Figure 32 and Figure 33. As these outputs are generated by LDOs, the output voltage ripple is the same (independent) for all input voltages, and is very low. Therefore, only one output voltage ripple image is shown in the figures 32 and 33. All of the measurements were taken at full output load.
Figure 30. Analog 5 V - output voltage ripple
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Measurements
Figure 32. Analog 3.3 V - output voltage ripple
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Measurements Figure 33. VAUX 2.5 V - output voltage ripple
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Measurements
6.2.3
Transient
Transient responses were measured only for VAUX and VSYS. The transient responses are displayed in Figure 34 and Figure 35. The transient waveforms of the L5970AD section show the response time. The most visible difference between the L5970AD in classic voltage mode and the PM6680A working in Constant On Time mode is the reaction when there is a fast load increase. Whereas the PM6680A reacts asfast as possible on the rising load, the L5970AD will wait short time as the compensation network is implemented in feedback loop (see Figure 24 and Figure 25).
Figure 34. Transient response of VSYS based on the L5970AD
Figure 35. Transient response of VAUX generated by the LDO KF25
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References
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7
References
1. 2. 3. 4. 5. 6. Datasheet PM6680A Datasheet L5970AD Datasheet LK112 Datasheet KF25 STM6719 AN1330 - designing with the L5970D, 1 A high efficiency DC-DC converter.
8
Revision history
Table 8.
Date 25-Sep-2007
Document revision history
Revision 1 Initial release Changes
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