AN2771 Application note
2x58 W/T8 or 2x36 W/T8 ballast demonstration board driven by L6585D
Introduction
This application note describes a demonstration board able to drive 2x58 W linear T8 fluorescent tubes. In addition, the modifications needed to adapt the same board for 2x36 W linear T8 fluorescent tubes are specified. The ballast is controlled by STMicroelectronics' L6585D which integrates PFC and halfbridge control circuits, the relevant drivers, and the circuitry able to manage all lamp operating phases (preheating, ignition and run mode). Protections against primary failures (lamp disconnection, anti-capacitive mode, PFC overvoltage) are guaranteed and obtained with a minimum number of external components. After presenting the circuit description and design criteria, a short overview of the ballast performances is given. Fluorescent lamps are driven more and more by electronic, rather than electromagnetic ballast, primarily because fluorescent lamps can produce around 20 % more light for the same input power when driven above 20 kHz instead of 50/60 Hz. Operation at this frequency also eliminates both light flickering (the response time of the discharge is too slow for the lamp to have a chance to extinguish during each cycle) and audible noise. An electronic ballast consumes less power and therefore dissipates less heat than an electromagnetic ballast. The energy saved can be estimated in the range of 20-25% for a given lamp power. Finally the electronic solution allows better control of the filament current and lamp voltage during preheating with the unquestionable benefit of increasing the mean lamp life. Figure 1. 2x58W T8 ballast demonstration board
August 2008
Rev 1
1/27
www.st.com
Contents
AN2771
Contents
1 2 3 Basis of half-bridge inverter topology . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ballast design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 3.3 3.4 L6585D biasing circuitry (pin by pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PFC power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Half-bridge inverter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Symmetrical and asymmetrical EOL protection: improvements . . . . . . . . 13
4 5 6
Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Conduction emissions test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Adapting the design for a 2x36 W T8 electronic ballast . . . . . . . . . . . . . . 21
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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AN2771
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. 2x58W T8 ballast demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Electronic lamp ballast - capacitor-to-ground configuration . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electronic lamp ballast - lamp-to-ground configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dual lamp ballast series configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dual lamp ballast parallel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical schematic 2x58 W T8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TSM101 window comparator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External symmetrical EOL protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 L6585 startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 One lamp ignition phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Low-side current in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage and current lamp in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Asymmetrical EOL protection with broken cathode during run mode . . . . . . . . . . . . . . . . . 19 Symmetrical EOL protection behavior during ignition phase . . . . . . . . . . . . . . . . . . . . . . . 20 Conducted emissions at 230 Vac 50 Hz - line 1 peak detector . . . . . . . . . . . . . . . . . . . . . 21 Conducted emissions at 230 Vac 50 Hz - line 2 peak detector . . . . . . . . . . . . . . . . . . . . . 21
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Basis of half-bridge inverter topology
AN2771
1
Basis of half-bridge inverter topology
The half-bridge inverter operates in zero voltage switching (ZVS) resonant mode, to reduce the switching losses and the electromagnetic interference generated by the output wiring and the lamp. Voltage-fed series resonant half-bridge inverters are currently used for compact fluorescent lamp ballasts (CFL) and for many European tube lamp (TL) ballasts. Generally, for lighting applications, considering the current preheating, it's possible to choose between two different topologies of the resonant circuit: capacitor-to-ground (Figure 2) or lamp-to-ground (Figure 3).
Figure 2.
Electronic lamp ballast - capacitor- Figure 3. to-ground configuration
Electronic lamp ballast - lamp-toground configuration
+
CRES
+
LRES Vdc CBlock _ _ Vdc
LrRES
CBlock CRES
In the design presented in this application note, a capacitor-to-ground configuration was used. For dual lamp ballast the lamps can be connected in series (Figure 4) or in parallel (Figure 5). In the system presented here, a parallel configuration was chosen for the following reasons:
lower voltage stress on the ballast output stage components, on the wiring, and on the fixture sockets the resonant L and C associated with the lamps are less sensitive to component tolerances due to the lower operating lamp voltages compared to the series configuration better lamp control as it is possible to independently monitor both lamp operations Figure 5. Dual lamp ballast parallel configuration
CRES LrRES
Figure 4.
Dual lamp ballast series configuration
CRES
+
+
LrRES LrPRE
-
CBlock
-
CBlock
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AN2771
Main characteristics
2
Main characteristics
The electrical specifications for the electronic lamp ballast are given in Table 1 and the schematic for the 2x58 W T8 is presented in Figure 6. The ballast design procedure is detailed in the following section. Table 1. Input and output parameters
Input parameters VIN fline Input voltage range Line frequency Tube lamp Number Type Power 2 T8 in parallel configuration 58 W or 36 W Target output parameters PF THD% % Power factor Total harmonic distortion Efficiency 185 to 265 VRMS 50/60 Hz
0.9
10
90 %
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8
3
5
1
D3 GF1M C8 R18 18 kOhm Q2 R20 62 Ohm STD8NM60N INV Comp Mult CTR EOL-R EOLP TCH EOI RF Osc 10 nF R19 13 kOhm U1 L6585D R17 20//11 kOhm
D4 GF1M
R10 15 kOhm
10 9 8 7 6 5 4 3 2 1
1
4
2
3
F1
3A
11 12 13 14 15 16 17 18 19 20
CON3
D5 GF1M D7 BAT46Z
D6 GF1M
ZCD PFCS PFG HBCS GND LSD VCC Out HSD Boot
3
1
3
3
Q8 BC847 2
1
3
R50 56k R55 470
2
2
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Main characteristics Figure 6.
D10 1N4007
D2 STTH1L06 R3 560 kOhm 0.8 mH LPFC1 C1 + R12 R11 1.5 MOhm 910 kOhm R30 56K R14 20 kOhm C7 R15 240 kOhm C6 470//150 1.2 MOhm 70//220 nF R16 4 C3 33 nF R8 16 kOhm C2 470//100 nF R13 30 KOhm C21 47uF 450V 100nF 630V R32 0 C5 1.8 nF R6 R7 1.5 MOhm 910 kOhm R27 56K
R4 560 kOhm
R5 1 MOhm C4 470 nF R9 390 kOhm
R33 0
J1
LPFC2
C22 220 pF 1kV
R34 180k
C9 10 nF 1600V
2 1 3
C10 100nF 275V X2
C11 100nF 275V X2
LA MP 1 L1 1 1.8 mH R36 68k 5 1 2 T8 Lamp1-58W 4 3 C12 100 nF, 400V
2x39 mH/0.7A
C20 Q3 STD6NK50Z R21 10 Ohm C13 100nF 50V
1nF 275 VAC Y1
R37 56k
R35 180k
C14 10 nF 1600V
R53 R22 0.33 ohm 1% 1W C25 CAP NP
0 L2 1 1.8 mH Q4 R23 62 Ohm R40 68k STD8NM60N R41 56k 5 4 3
Electrical schematic 2x58 W T8
LA MP 2 1 2 T8 Lamp1-58W C15 R24 1.802 MOhm 100 nF, 400V
R25 1.6 kOhm R54 0R C16
D8
1N4148
R29 10 Ohm
U2 1 nF 1kV C18 100nF D9 16V 1 D13 LL4148 R31 0.33 ohm 1% 1W C19 R56 18k R52 0 D11 BAT46Z 2 3 100 nF 4 Vref Csense Crref GND TSM101 +Vcc Vrin Output Crin 8 7 6 5 R26 10 kOhm C17 4.7uF 50V
D12 BAT46Z R49 330k R51 2k 2 Q7 XO205MA R48 1 BC847 Q6 10 R47 330k
1 BC847 Q5 R46 470k
AN2771
AN2771
Ballast design
3
Ballast design
The design of the major parts of the circuit is described in this section.
3.1
L6585D biasing circuitry (pin by pin)
Designed in high-voltage BCD offline technology, the L6585D embeds a PFC controller, a half-bridge controller, the relevant drivers and the logic necessary to build an electronic ballast.
Pin 1 OSC is one of the two oscillator inputs. The value of the capacitor connected to ground defines the half-bridge switching frequency in each operating state. A value of 1.8 nF was chosen. Pin 2 RF. The component choice with oscillator capacitance defines the half-bridge switching frequency in each operating state. A resistor R14 connected to ground sets the run frequency while during preheating the switching frequency is set by the parallel of R14 with R13 connected between pins RF and EOI (short-circuit during preheating).
Choosing the following frequencies and ignition time:
frun = 39 kHz
fpre = 65 kHz
t ign = 60 ms
we can immediately calculate R14 with the following formula: Equation 1
R14 =
and for the value of R13: Equation 2
R13 =
1.326 = 20 k frun C 5
1.326 R14 = 30 k fpre C 5 R14 - 1.41
Pin 3 EOI is a multifunction pin. During preheating the pin is internally shorted to ground by the logic, so the resistor (RPRE//RRUN) connected between the RF pin and ground sets the preheating switching frequency. During ignition pin EOI becomes high impedance. The ignition time is the time necessary for the pin voltage to exponentially rise from zero to 1.9 V. The growth is steered by the C6* R13 time constant. As the value of R13 has already been calculated and tign at start is fixed, the value of C6 is calculated by the following formula:
Equation 3
C6 =
t ign 3 R13
= 666 nF
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Ballast design
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The value C6=620 nF was chosen. In order to have this value, two capacitors in parallel were mounted C6=470//150 nF.
Pin 4 TCH is the time counter and it is necessary to establish the preheating time and the protection intervention time (either overcurrent or EOL). To implement the time counter, a R15C7 parallel network is connected between this pin and ground. Choosing C7=690 nF and tpre=1 sec and considering the internal current generator ICH=34 A, we can calculate R15 as follows:
Equation 4
t pre - R15 =
C7 4.63 ICH = 1.2 M 4.63 C 7 ln 1. 5
Pin 5 EOLP is a 2 V reference and allows programming the window comparator of pin 6 (EOLR) according to table 5 of the L6585D datasheet. Choosing a reference tracking with the CTR pin and a window voltage amplitude 220 mV, we chose R16=240 k. Pin 6 EOLR is the input of both the window comparator and a re-lamp comparator. Concerning the window comparator (choosing tracking with CTR pin), the center is the same voltage as the CTR pin so the resistive divider connected across the block capacitor (see Cblock in Figure 2) is set such that under normal conditions:
Equation 5
VCTR = VBUSpfc VBUSpfc 2
R19 + (R 7 + R12 ) R8 R 8 + (R 3 + R 4 )
R19
VEOLR =
VEOLR = VCTR
(R7 + R12 ) = 2 (R3 + R4 ) + 1
R19 R8
To determine the resistance values of (R7+R12), R19, (R3+R4), R8, decisions concerning pin 7 CTR are needed.
Pin 7 CTR is a multifunction pin (PFC overvoltage, feedback disconnection, reference for EOL in case of tracking reading), connected to a resistive divider to the PFC output bus. Establishing the maximum PFC overvoltage (PFC output overshoot e.g. at startup) at VOVPBUSpfc = 480 V and considering that the correspondent threshold on the CTR pin must be VthrCTR = 3.4 V, we can immediately calculate R7+R12 = 1.82 M and R19 = 13 k. From Equation 5, fixing R3+R4 = 1120 k, the following resistance value is obtained R8 = 16 k. Pin 8 MULT. Assuming a peak value of VmultpkMax = 1.8 V (at VAC = 265 V) on the multiplier input (MULT, pin 8), the peak value at minimum line voltage is VMULTpkmin = 1.8 × 185/265 = 1.25 V which, multiplied by the maximum slope of the multiplier, 0.75, gives 0.94 V peak voltage on current sense (CS, pin 4). Since the linearity limit (1 V) is not exceeded, this is acceptable. Considering about 250 A current for the divider, the lower resistor is 7.14 k (20//11 k ). To establish the upper resistance value (referring to the PFC section of the L6585D datasheet), the ratio between Vmult and Vin for different input voltage must be evaluated:
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AN2771 Equation 6
Ballast design
VinMax
VinMin
where:
R17
V R17 = multPK max = 4.8 10 -3 + (R 5 + R9 ) 2 VinMax
1 2 VinMin = 5.1 10 -3
R17
VmultSlopeMax VCSclamp R17 = = + (R 5 + R9 ) max slope 2 VinMin
VCSclamp is the clamp value of the voltage current sense for L6585D max slope is the maximum slope of the multiplier characteristic family for L6585D VmultSlopeMax is the maximum voltage in the mult pin with Vin=VinMin
To work in the linear area of the multiplier characteristic family, the upper resistance choice is made considering the lowest of ratios calculated in Equation 6 R5+R9=1.487 M. R5+R9 = 1.390 M was mounted.
Pin 9 COMP is the output of the E/A and also one of the two inputs of the multiplier. The feedback compensation network, placed between this pin and INV (10), is simply a capacitor calculated as follows (considering R6+R11 is the upper resistance of the voltage divider between the PFC bus and COMP pin):
Equation 7
C2 =
A value of C2=560 nF was chosen.
10 = 530 nF 2 (R 6 + R11 )
Pin 10 INV. To implement the voltage control loop, a resistive divider (Figure 6) is connected between the regulated output voltage VBUSpfc = 420 V of the boost and the pin. The internal reference on the noninverting input of the E/A is 2.5 V, so R6 and R11 (Figure 6) are then selected, establishing a max overvoltage VOVPBUSpfc = 60 V, as follows:
Equation 8
R 6 + R11 VBUSpfc = -1 R18 2 .5
R 6 + R11 =
VOVPBUSpfc IOVPth
= 3 M
R18 = 17.964 k 18 k
where IOVPth = 20 A is the threshold current flowing through the compensation network in case an abrupt load drop happens.
Pin 11 ZCD is the input to the zero current detector circuit. The ZCD pin is connected to the auxiliary winding of the boost inductor through a limiting resistor. The ZCD circuit is negative-going edge-triggered: when the voltage on the pin falls below 0.7 V, the PWM latch is set and the MOSFET is turned on. To do so, however, the circuit must first be armed. Prior to falling below 0.7 V, the voltage on pin 11 must experience a positivegoing edge exceeding 1.4 V (due to the MOSFET's turnoff). The maximum main-to-
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auxiliary winding turn ratio, m, has to ensure that the voltage delivered to the pin during the MOSFET's OFF-time is sufficient to arm the ZCD circuit. Then:
Equation 9
m We chose m=10.
VBUSpfc - 2 VinRMS(max) 1 .4
= 33.10
Considering the upper and lower clamp voltage of the ZCD pin, its minimum current sink current capability, according to the max and min voltage of the PFC bus, we can immediately calculate and choose R10 = 15 k.
Pin12 PFCS is the inverting input of the current sense comparator. As the voltage across the sense resistor (proportional to the instantaneous inductor current) crosses the threshold set by the multiplier output, the power MOSFET is turned off. Following the indication given in AN966, page 13, considering the max peak current absorbed by two lamps, it is possible to determine the following PFC sense resistor:
Equation 10
R 22 340 m We chose R22=330 m with a power rating of 0.5 W. Considering the clamp value voltage on this pin, VCSclamp = 1.16 V, it was possible to determine the maximum inductor current ILmax = 3.5 A.
Pin13 PFG. To correctly drive the external MOSFET, a resistor R21=10 was used. Pin 14 HBCS. Establishing during ignition, for each lamp, a maximum current of IIGNmax = 2.5 A and considering the HBCS threshold during ignition phase VHBCS-ign = 1.6 V, we can calculate RsenseHB=R31:
Equation 11
R 31 = We chose R31 = 0.33 .
VHBCS -ign IIGN max TOT
= 0.32
Pin 15 GND: ground Pin 16 LSD. To correctly drive the external half-bridge low-side MOSFET, a resistor R23=62 was used. Pin 17 Vcc. This pin is externally connected to the startup circuit (by means of R34, R35, R37, R40, R41) and to the self-supply circuit consisting of a charge pump composed of the net C16, C17, C18, D8, D9, R29. Pin 18 Out: high-side driver floating reference. This pin is connected close to the source of the high-side power MOSFET. Pin 19 HSD. To correctly drive the external half-bridge low-side MOSFET a resistor R20=62 was used. Pin 20 Boot. For the high-side section a Cboot = 100 nF was selected.
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AN2771
Ballast design
3.2
PFC power section design
Input capacitor
The input high-frequency filter capacitor C4 has to attenuate the switching noise due to the high-frequency inductor current ripple. The worst conditions occur on the peak of the minimum rated input voltage Vinmin = 185 V where:
the coefficient of maximum high frequency voltage ripple r = 0.05 total system efficiency is possible, considering the minimum half-bridge switching frequency fswmin = 39 kHz and the total output power PoutTOT = 2*58 = 116 W, to determine the input capacitor C4 as follows:
Equation 12
PoutTOT Vin min C4 = = 307 nF 2 fsw min Vin min r
C4=470 nF was chosen.
Output capacitor
The output bulk capacitor C1 selection depends on the DC output voltage, the admitted overvoltage, the output power and the desired voltage ripple where:
PFC output voltage VbusPFC = 420 V the coefficient of low-frequency (twice the mains frequency fmin = 50 Hz ) voltage ripple r1 = 0.05
We can calculate the bulk capacitor in Equation 13:
Equation 13
PoutTOT VbusPFC = 21 F C1 = 2 2fmain VbusPFC r1
To have the smallest ripple and good reliability, we chose capacitor C1 =47 F, 450 V.
Boost inductor
The inductance Lpfc is usually determined so that the minimum switching frequency fmin pfc is greater than the maximum frequency of the internal starter in order to ensure a correct TM operation. Considering the minimum suggested value for the PFC section fmin pfc = 20 kHz and that it can occur at the either the maximum VinrmsMax = 265 V or the minimum VinrmsMin = 185 V mains voltage, the inductor value is defined by:
Equation 14
L pfc =
Vi2rms VbusPFC - 2 Vinrms n P 2 fmin pfc out VbusPFC
(
)
To obtain a margin from fmin pfc we chose fpfc = 33 kHz. In this condition the lower value for the inductor is determined by Vinrms = VinrmsMax and Lpfc = 0.8 mH with, as previously stated in the PFCS pin description, a maximum current ILmax = 3.5 A.
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Ballast design
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Power MOSFET
The choice of the MOSFET concerns mainly its RDS(on), which depends on the output power, and its breakdown voltage. This last voltage is fixed just by the output voltage Vbuspfc = 420 V, plus the overvoltage VOVPpfc = 60 V allowed and a safety margin. The MOSFET's power dissipation depends on the conduction and switching losses. Establishing maximum total power losses PlossesAdm = 1% and PoutTOT = 1.16 W, it is easy to verify that in choosing SuperMesh power MOSFET STD6NK50Z, the estimated total MOSFET power losses, in the worst case, is about PlossesEst = 0.6 W, so this choice was the definitive one.
Boost diode
The boost freewheeling diode is a fast recovery one. The breakdown voltage is fixed with the same criterion as the MOSFET. The values of its DC and RMS current, which are needed to choose the current rating of the diode, are given as follows:
Equation 15
ID2dc =
PoutTOT = 0.276 A VBUSpfc
ID2rms = 2 2 Irms
4 2 Vinrms = 0 .6 A 9 VBUSpfc
Since the PFC works in transition mode, the Turbo 2 Ultrafast high-voltage rectifier STTH1L06 was selected.
3.3
Half-bridge inverter design
Concerning the resonant circuit design, according the criteria described in AN993 section 5, we chose the following:
L res = L1 = L 2 = 1.8 mH
Cres = C9 = C14 = 10 nF / 1600 V
Cblock = C12 = C15 = 100 nF / 400 V
The P-Mos selection in the half-bridge section is performed mainly considering the max power losses admitted on each switch PlossesAdm1 = 0.5% PoutTOT 0.6 W and the rms current through it IrmsMOS 0.6 A. Concerning half-bridge devices, using the second generation MDmesh Power MOSFET STD8NM60N, the estimated power losses in it result in PlossesEstHB 0.468 W.
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AN2771
Ballast design
3.4
Symmetrical and asymmetrical EOL protection: improvements
As previously stated, the L6585D includes two functions concerning EOL protections which are summarized as follows: a) The first function has been designed to detect the ageing of the lamp with particular attention to the effect appearing as asymmetric rectification. The idea is to measure the variation of the DC component of the lamp voltage that can be either positive or negative. A window comparator has been introduced (centered around Vref with amplitude "Vw") that triggers when the EOL-R voltage is higher than Vset+ Vw/2 or lower than Vref- Vw/2. This kind of protection is compliant to the two standard ballast configurations (lamp-to-ground and block capacitor-toground). b) Concerning the second function, as soon as a fault due to broken lamp in ignition mode (1.6 V threshold crossing) or a symmetrical EOL in run mode (0.9 V threshold crossing) triggers the TCH timer, the frequency control starts. When the timer ends, the current is monitored on the HBCS pin at the first cycle. In both conditions if the HBCS threshold is still crossed, the oscillator stops, the chip enters low-consumption mode /shutdown mode and this condition is latched until the mains supply is removed or re-lamp is detected. The following improvements in the protection functions have been implemented: The asymmetric rectification protection, described above, was implemented to monitor the status of only one lamp. To protect the second lamp with the same criteria (voltage window comparator) as the first one, a voltage and current control TSM101 in the configuration shown in Figure 7 was used. With this circuit it was possible to obtain the asymmetric rectification protection in a reliable and independent manner for each lamp.
Figure 7. TSM101 window comparator configuration
The design criteria for TSM101 in window comparator configuration is described in the following paragraphs. By means of a voltage divider R24, R25, R54+R26, from the block
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Ballast design
AN2771
capacitor of the second lamp, TSM101 checks that the average voltage value on the capacitor is VAVE = 210 V. Considering that the voltage window used for the first lamp is Vwindow1 = 2*220 mV 15%VCTR, for the second lamp a similar percent voltage window Vwindow2 15%VAVE = 31 V was chosen. Establishing the second voltage window and considering that the voltage reference in TSM101 is Vref = 1.24 V, it is easy to calculate the resistance value of the voltage divider mentioned in the previous paragraph (presuming, in normal conditions, an absorbed current in it of IVdivider 116 A ) as follows:
Equation 16
R tot = R 24 + R 25 + R 54 + R 26 =
R 54 + R 26 = Vref VAVE
VAVE = 1.81 M IVdivider
R tot = 9954 R 54 + R 26 = 10 k Vwindow 2 + 2
Vref R 25 =
Vwindow 2 VAVE - 2 - (R 54 + R 26 ) R tot = 1540 R 25 = 1.6 k Vwindow 2 VAVE - 2 R tot
R 24 = R tot - (R 25 + R 54 + R 26 ) = 1.798 M 1.8 M
The symmetrical EOL protection described in paragraph b of this section was improved because for a two-lamp application an event such as the breaking of one lamp and the ignition of the other one may not activate the embedded device protection quickly enough.
To avoid this type of issue and in order to increase the reliability of the protection, an external circuit as shown in Figure 8 was implemented.
Figure 8. External symmetrical EOL protection
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Ballast design
This circuit (considering that it is possible to latch the device maintaining the CTR pin to zero voltage), by means of an inverting logic made by Q5 and Q6, is activated by the voltage on the half-bridge current sense resistor VR31. Overcoming a fixed voltage threshold on the HB current sense, the X0205MA SCR is activated which consequently activates Q8 and causes the CTR pin to go down to zero voltage. The device is latched until the main supply is removed.
15/27
Experimental results
AN2771
4
Experimental results
The schematic of the tested board is shown in Figure 6 . The board was first tested in terms of efficiency, power factor, total harmonic distortion and thermal behavior for the input voltage range. Table 2 and Table 3 show the results obtained for testing during 45 minutes.
Table 2.
VIN (V) 185 230 265
2x58 W T8 board performance
PIN (W) 115.5 112.5 113.5 POUTlamp1 (W) 52 52 52 0.90 0.92 0.91 IIN (A) 0.645 0.515 0.455 PF 0.995 0.992 0.988 THD (%) 7.9 8 10
All results obtained are very good. Efficiency is about 90%, the power factor corrector is constantly 0.99, and THD is about 8%.
Table 3. 2x58 W T8 thermal results of critical system components
Temp MOSLowSide Temp MOSHighSide Temp MOSPFC (C) Temp L6585D (C) (C) (C) 71 71 71 79 79 78 58 47 44 49 47 47
VIN (V) Ambient temp (C) 185 230 265 23 23 23
Concerning thermal behavior, from the results given in Table 3, it is easy to deduce, considering the highest ambient temperature, that there is a good safety margin from the max junction temperature of the MOS. Star tup sequence
Figure 9 shows the startup sequence: the IC supply voltage VCC reaches VCCon, the halfbridge starts oscillating and starts the charge capacitor connected to TCH. When the voltage at the TCH pin reaches VCHP (4.63 V), the same capacitor is discharged following an exponential decrease steered by the time constant, which defines the preheating time.
During this time, the EOI pin is forced to ground and the switching frequency is set by the oscillator at the preheating value. When the voltage at the TCH pin drops down to 1.53 V, the EOI pin is exponentially charged according to a time constant that defines the ignition time. At the same time the TCH pin goes down to ground. During this phase the oscillator generates a reduction of the switching frequency. As the voltage at EOI exceeds 1.9 V, the chip enters run mode.
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AN2771 Figure 9. L6585 startup sequence
Experimental results
Figure 10 shows the lamp ignition phase. The voltage across it increases linearly as well as the current flowing through it. Figure 10. One lamp ignition phase
17/27
Experimental results Figure 11. Low-side current in run mode
AN2771
Figure 12. Voltage and current lamp in run mode
18/27
AN2771
Protections
5
Protections
As previously stated in Section 3.4, due to the presence of two lamps, TSM101 must be added to implement the asymmetric EOL protection, and inverter logic with a SCR must be added to implement the symmetrical EOL protection. The following failures were simulated to test these: Cathode breaking in run mode Broken tube or failure to strike during ignition phase As shown in Figure 13, as soon as a cathode of one lamp is broken, the voltage on the EOLR pin goes out from the valid voltage window and the L6585D stops switching.
Figure 13. Asymmetrical EOL protection with broken cathode during run mode
When one of the two lamps is broken or the the gas inside is exhausted, during the ignition phase, as illustrated in Figure 14, the right lamp is ignited normally, but the voltage across the broken lamp rises up continually until an established threshold is exceeded that activates the SCR, by means of an inverter logic, and moves the CTR pin down to ground. In this condition the L6585D is latched.
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Protections Figure 14. Symmetrical EOL protection behavior during ignition phase
AN2771
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AN2771
Conduction emissions test
6
Conduction emissions test
Conducted emissions have been measured in neutral and line wires using peak detector and considering the limits for lighting applications i.e. EN55015. The measurements have been performed at 230 Vac line. The results are shown in Figure 15 and Figure 16. Since the emission level is below both the quasi-peak and average limits with an acceptable margin, the power supply passes the precompliance test.
Figure 15. Conducted emissions at 230 Vac 50 Hz - line 1 peak detector
02:15:56 Feb 11, 2008 Ref 75 dBV Peak Log 10 dB/ Atten 0 dB Mkr1 22.03 MHz 30.66 dBV
1
W1 S2 S3 FC AA
Start 150 kHz Res BW 9 kHz
VBW 30 kHz
Stop 30 MHz Sweep 881.3 ms (2115 pts)
Figure 16. Conducted emissions at 230 Vac 50 Hz - line 2 peak detector
02:21:25 Feb 11, 2008 Ref 75 dBV Peak Log 10 dB/ Atten 0 dB Cntr1 22.034 MHz 31.67 dBV
Marker Count: Widen Res BW
1
W1 S2 S3 FC AA
Start 150 kHz Res BW 9 kHz
VBW 30 kHz
Stop 30 MHz Sweep 881.3 ms (2115 pts)
6.1
Adapting the design for a 2x36 W T8 electronic ballast
Using a developed design for 2x58 W T8 tubes, it was possible to do some simple adjustments to adapt the same design for 2x36 W T8 tubes. Using the same resonant
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Conduction emissions test
AN2771
circuit, the adjustments concern only the operating frequencies of the lamp, setting the following ones at: frun = 49 kHz fpreh = 65 kHz
we can immediately calculate, by means of Equation 1 and Equation 2, the following value resistances: R14 = 15 k R13 = 47 k
In addition a new calibration for the symmetric end-of-life operation is needed, changing the following resistance to: R 56 = 75 Testing the board with these modifications the experimental results are given below in Table 4:
Table 4.
VIN (V) 185 230 265
2x36W T8 board performance
PIN (W) 74 73.5 73.4 POUTlamp1 (W) 33 33 33 0.89 0.89 0.89 IIN (A) 0.39 0.315 0.275 PF 0.994 0.987 0.979 THD (%) 6.9 7.6 8.7
Table 5.
Item Qty
Bill of material
Ref. Part/value Tolerance Voltage (%) current Watt Technology information Package footprint Manufacturer Manufacturer code RS/ distrelec /other code
1
1
C1
47 F, 098 A 560 nF (470//100 nF) 33 nF
20%
450 V
Electrolytic capacitor COG ceramic capacitor COG ceramic capacitor Polyester capacitor COG ceramic capacitor COG ceramic capacitor COG ceramic capacitor COG ceramic capacitor
EPCOS
B43858C5476M 000
2
1
C2
5%
50 V
SMD 0805
3
1
C3
5%
50 V
SMD 0806 Radial 22.5 mm lead spacing SMD 0805 B32523Q8474K 000
4
1
C4
470 nF
10%
630 V
EPCOS
5
1
C5
1.8 nF 660 nF (470//150) nF- ceramic 680 nF (470//220) nF-ceramic 10 nFceramic-
5%
50 V
6
1
C6
5%
50 V
SMD 0805
7
1
C7
5%
50 V
SMD 0805
8
1
C8
5%
50 V
SMD 0805
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AN2771 Table 5.
Item Qty
Conduction emissions test Bill of material (continued)
Ref. Part/value Tolerance Voltage (%) current Watt Technology information Package footprint Manufacturer Manufacturer code RS/ distrelec /other code
9
2
C9, C14
10 nF
5%
1600 V
Metallized Radial polypropylene 22.5mm lead film capacitors spacing X2 polypropylene capacitor Metallized polyester film capacitors Ceramic capacitor Polypropylene capacitor Electrolytic capacitor COG Ceramic capacitor Y1 Ceramic capacitor polypropylene capacitor Radial 10mm lead spacing
EPCOS
B32653A1103J 000 RS: 4419616
10
2
C10,C11
100 nF
10%
300 Vac
11
2
100 nF, 400 VC12, C15 polyesterlead spacing 10mm C13 C16 100 nF50V- 10% 1 nF
10%
400 V
EPCOS
B32561J6104K 000
12 13
1 1
10% 5%
50 V 630 V
SMD 1206 Radial 5mm lead spacing Cylindrical 2.5 mm lead spacing SMD 0805 Radial 9.5 mm lead spacing Radial 15 mm lead spacing Radial 5mm lead spacing CERA MITE 440LD10-AD 10PCM RS: 2145896 RS: 1908371 EVOX RIFA PFR5 102J630J11L4 RS: 2404836
14
1
C17
4.7 F 100 nFceramic 1 nF Y1
20%
50 V
15
2
C18, C19
5%
50 V
16
1
C20
20%
250 Vac
17
1
C21
100 nF 220 pF ceramiclead spacing 5 mm Not mounted BAT46
10%
630 V
EPCOS
B32652A6104K
18
1
C22
10%
1 kV
Ceramic disc capacitor
Panasonic
ECKA3A221KB P
RS: 4730373
19 20
1 3
C25 D7,D11, D12
150 mA
Small signal Schottky diode Ultrafast high voltage rectifier
SMD SOD323
STMicroelectronics STMicroelectronics
BAT46JFILM
21
1
D2 D3,D4, D5,D6 D8, D13 D9 D10
STTH1L06 1000 V 1 A 75 V 150 mA 5% 16 V 1000 V 1A 250 V 500 mW
DO-41 SMD DO214BA SMD SOD80 SMD SOD123 DO-41
STTH1L06 RS: 269451
22 23 24 25
4 2 1 1
GF1M-1A LL4148 16 V 1N4007
Rectifier diode Switching diode Zener diodes Rectifier diode TR5 quick acting submin PCB F fuse 3 way screw terminal block 7.5 mm pitch
RS: 4471838
26
1
F1
3,15 A
RADIAL
RS: 2266549 RS: 5487317 WAGO (www. wago.it)
27
1
J1
CON3
THT 7.5 mm lead spacing THT 5 mm lead spacing
28
Lamp, Lamp2
T8 Lamp158 W
250V
4 pins PCB terminal strip
739-104
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Conduction emissions test Table 5.
Item Qty
AN2771
Bill of material (continued)
Ref. Part/value Tolerance Voltage (%) current Watt Technology information Package footprint Manufacturer Manufacturer code RS/ distrelec /other code
29 30 31 32
1 Note(1) 1 2 Note(1) 3
LPFC1 LPFC2 L1, L2 Q5, Q6, Q8 Q2, Q4
0.8 mH 2x39 mH/0.7 A 1.8 mH +/5% BC847 STD8NM60 N STD6NK50Z 5% 100 mA 600 V 7A 500 V 6A 600 V 0.050 mA 1% 1% 1% 1% 1% 1% 5% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1/4 W 1/4 W 1/4 W 1/4 W 1/8 W 1/4 W 1/4 W 1/8 W 1/8 W 1/8 W 1/8 W 1/4 W 1/4 W 1/4 W 1/8 W 1/8 W 1/4 W NPN transistor MDmeshTM Power MOSFET Supermesh MOSFET SCRs Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Carbon film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor SMD SOT-23 STMicroelectronics STMicroelectronics STMicroelectronics Common mode choke EPCOS B82732R2701B 030
33
2
SMD DPAK
STD8NM60N
34
1
Q3
SMD DPAK
STD6NK50Z
35
1
Q7
X0205MA
TO92
X0205MA
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
2 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 1
R3, R4 R5 , R7, R12 R6, R11 R8 R9 R10 R13 R14 R15 R16 R17 R18 R19 R20, R23 R21, R48 R29
560 k 1 M 910 k 1.5 M 16 k 390 k 15 k 30 K 20 k 1.2 M 240 k 20//11 k parallelo18 k 13 k 62 10 10
SMD 1206 SMD 1206 SMD 1206 SMD 1206 SMD 0805 SMD 1206 axial SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 1206 SMD 1206 SMD 1206 SMD 0805 SMD 0805 SMD 1206
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AN2771 Table 5.
Item Qty
Conduction emissions test Bill of material (continued)
Ref. Part/value Tolerance Voltage (%) current Watt Technology information Package footprint Manufacturer Manufacturer code RS/ distrelec /other code Distrele: 720643
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
2 1 1 1 4 1 3 2 2 2 1 2 1 1 1
R22, R31 R24 R25 R26 R27,R3, R37,R41 R50 R32,R33, R52 R53, R54 R34,R35 R36,R40 R46 R47,R49 R51 R55 R56
0.33 1.8 M 1.6 k 10 k 56 k 56 k 0 jumper 0 jumper 180 k 68 k 470 k 330 k 2 k 470 18 k
1% 1% 1% 1% 5% 1%
1W 1/4 W 1/4 W 1/4 W 1/4 W 1/8 W
Precision wire resistors Metal film resistor Metal film resistor Metal film resistor Carbon film resistor Metal film resistor
axial SMD 1206 SMD 1206 SMD 1206 axial SMD 0805 SMD 1206 SMD 0805
1% 5% 1% 1% 1% 1% 1%
1/4 W 1/4 W 1/8 W 1/8 W 1/8 W 1/8 W 1/4 W
Metal film resistor Carbon film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Metal film resistor Combo IC for PFC and ballast control Voltage and current controller
SMD 1206 axial SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 1206 STMicroelectronics STMicroelectronics
68
1
U1
L6585D
SMD SO-20
L6585D
69
1
U2
TS M 1 0 1 Insulate wire- jump Note(2) Spacer/ distanziatori
SMD SO-8
TSM101AIDT
70
15
JUMP
Wire 0.6 mm 10 mm
Wire 0.6 mm
71
4
S pacer
Nylon
1. Nostra Fornitura max 50 pcs 2. The wire-jump must be insulated
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Revision history
AN2771
7
Revision history
Table 6.
Date 06-Aug-2008
Document revision history
Revision 1 Initial release Changes
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AN2771
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