AN2783 Application note
PM8800 demonstration kit for standard and high power PoE PD interface and power supply, with auxiliary sources
Introduction
This document details the characteristics and performances of the PM8800 demonstration kit which has been designed to cover a broad range of power over Ethernet (PoE) applications. PM8800 is a highly integrated device embedding an IEEE802.3af compliant powered device (PD) interface together with a PWM controller and support for auxiliary sources. Even though PM8800 can be configured to work in both isolated and non-isolated topologies, this application note focuses on an isolated topology only, in two different output power configurations (10 W and 20 W) and 2 different output voltages (5 V and 3.3 V). The PM8800 demonstration kit supports diode as well as synchronous rectification. Auxiliar y sources can be connected to the board on 2 input points. One input allows prevalence of the auxiliary sources with respect to the PoE, while the other input allows the usage of a wall adaptor with voltage lower than the internal PoE UVLO threshold and still benefits from the inherent inrush and DC current limit. The above mentioned configurations are all supported by the PM8800 demonstration kit as options on the same PCB. The bill of material (BOM) (see Section 5 on page 12) provides the list of components to be mounted for each of the targeted configurations. Figure 1. PM8800 demonstration kit
The high-power board appears on the left of the photo and standard board is on the right.
September 2008
Rev 2
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www.st.com
Contents
AN2783
Contents
1 2 3 4 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 4.2 Input/output connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 6 7
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 7.2 7.3 Diode bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transient voltage suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
PoE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1 8.2 8.3 8.4 8.5 8.6 8.7 Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 UVLO and power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Inrush current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AUXI input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AUXII input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9 10
Power transformer and operating input voltage . . . . . . . . . . . . . . . . . . 22 Power converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.1 10.2 10.3 Flyback continuous conduction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Main switch current and current sensing . . . . . . . . . . . . . . . . . . . . . . . . . 24 Main switch power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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AN2783
Contents
10.4 10.5
Rectifier diode dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PM8800 internal power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11 12
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.1 12.2 12.3 12.4 Efficiency measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 V high-power board measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3 V standard-power board measurements . . . . . . . . . . . . . . . . . . . . . . 36 IEEE 802.3af compatibility test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Appendix A Schematic of high-power board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Appendix B Schematic of standard-power board . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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List of figures
AN2783
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. PM8800 demonstration kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Demonstration kit schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Assembly view: top and bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Inner layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Inner layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Inrush current limit vs. RIRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC current limit vs. RDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output power vs. VAUXII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 V out - standard board with diode rectification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 V out - high-power board with synchronous rectification . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 V out - standard board with diode rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3 V out - high-power board with synchronous rectification . . . . . . . . . . . . . . . . . . . . . . . 30 Startup of the PM8800 demonstration kit with 5 V 1 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Startup of the PM8800 demonstration kit with 5 V 4 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Details of the inrush phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Details of the soft-start phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VDS and VGS of the primary MOSFET for 5 V 1 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 VDS and VGS of the primary MOSFET for 5 V 4 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Details of the synchronous rectifier MOSFET voltage with 48 V and 4 A out . . . . . . . . . . 32 Output voltage ripple at 4 A output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output voltage ripple at 4 A output current (1 sec persistence) . . . . . . . . . . . . . . . . . . . . . 33 Dynamic load 1 A to 4 A: output voltage (up) and output current (down) . . . . . . . . . . . . . 33 PM8800A response to a 6 A overload condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PM8800A recovering from a 6 A overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PM8800A response to a short on the load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PM8800A recovering from a short on the load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Internal short on the secondary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Switch between 48 V PoE and 24 V AUXII with 5 V at 2 A . . . . . . . . . . . . . . . . . . . . . . . . 35 back to 48 V removing the 24 V AUXII voltage with 5 V at 2 A . . . . . . . . . . . . . . . . . . . . . 35 Switch between 48 V PoE and 12 V AUXII with 5 V at 2 A . . . . . . . . . . . . . . . . . . . . . . . . 36 Back to 48 V removing the 12 V AUXII voltage with 5 V at 2 A . . . . . . . . . . . . . . . . . . . . . 36 Startup of the PM8800 demonstration kit with 3.3 V, 1 A . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Startup of the PM8800 demonstration kit with 3.3 V, 3 A . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Details of the inrush phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Details of the soft-start phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 VDS and VGS of the primary MOSFET for 3.3 V 1 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 VDS and VGS of the primary MOSFET for 3.3 V 3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Details of the synchronous rectifier MOSFET voltage with 48 V and 3 A output current . . 38 Output voltage ripple at 3 A output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Output voltage ripple at 3 A output current (1 sec persistence) . . . . . . . . . . . . . . . . . . . . . 38 Dynamic load 1 to 3 A: output voltage (up) and output current (down) . . . . . . . . . . . . . . . 39 PM8800A response to a 5 A overload condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PM8800A recovering from a 5 A overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PM8800A response to a short on the load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PM8800A recovering from a short on the load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Internal short on the secondary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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AN2783 Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54.
List of figures Switch between 48 V PoE and 24 V AUXII with 3.3 V at 2 A . . . . . . . . . . . . . . . . . . . . . . . 41 Back to 48 V removing the 24 V AUXII voltage with 3.3 V at 2 A . . . . . . . . . . . . . . . . . . . . 41 Switch between 48 V PoE and 12 V AUXII with 3.3 V at 2 A . . . . . . . . . . . . . . . . . . . . . . . 41 Back to 48 V removing the 12 V AUXII voltage with 3.3 V at 2 A . . . . . . . . . . . . . . . . . . . . 41 Schematic of the 3.3/5 Vout high power with synchronous rectification . . . . . . . . . . . . . . . 44 Schematic of the 3.3/5 Vout standard power with diode rectification . . . . . . . . . . . . . . . . . 45
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Main features
AN2783
1
Main features
The PM8800 demonstration kit has been designed to cover several PoE configurations with easy customization.
Basic configuration: (high-power applications) 5 V output Up to 4 A output 250 kHz operating switching frequency Flyback topology DCM/CCM
Board size 70 x 90 mm Power Good indication Overall efficiency of 85% at full-load condition (Figure 12) Prevalence of the auxiliary source with respect to the PoE line (Section 8.7) 1500 Vrms isolation ensured by the power transformer Suppor t for (see BOM options in Section 5): 5 V and 3.3V output diode or synchronous rectification standard IEEE802.3af or high-power applications non-isolated flyback topology
Suppor t for class 0-3 (IEEE802.3af) and class 4 (pre-standard modes)
The following 2 basic board configurations are addressed with the same PCB and referred in the rest of the text as: Standard power: this configuration covers IEEE802.3af applications and it is based on flyback topology with diode rectification. High power: this configuration targets applications with output power in excess of the IEEE802.3af standard up to 20 W as output. This configuration is based on flyback topology with synchronous rectification. The same configuration can be used in PoE designs targeting high efficiency and/or with wide range auxiliary input (down to 12 V with prevalence of the auxiliary with respect to PoE).
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AN2783
Electrical specifications
2
Electrical specifications
Table 1. Specifications
10 W 30 V to 60 V at 10 W output 18 V to 60 V 12 V to 60 V 3.35 V +/- 100 mV at 3 A VOUT 5.05 V +/- 100 mV at 2 A Peak-to-peak output ripple Efficiency DC-DC only 87% typ at 5 V 2 A 78% typ at 3.3 V 3 A Overall efficiency 81% typ at 5 V 2 A Switching frequency Dynamic current step 1- 2 A max at 5 V Maximum overshoot Maximum overshoot time duration Maximum undershoot Maximum undershoot time duration Maximum DC test current Minimum DC test current 200 mV 200 ms 200 mV 200 ms 3.5 A at 3.3 V 2.5 A at 5 V 0 1- 4 A max at 5 V 400 mV 300 ms 400 mV 300 ms 6.5 A at 3.3 V 4.5 A at 5 V 0 250 kHz typ +/- 10% 1- 3 A max at 3.3 V 84% typ at 5 V 4 A 250 kHz typ +/- 10% 1- 6 A max at 3.3 V 88% typ at 5 V 4 A 81% typ at 3.3 V 6 A 10 mVpp 83% typ at 3.3 V 3 A 5.05 V +/- 100 mV at 4 A 20 mVpp 86% typ at 3.3 V 6 A 20 W 30 V to 60 V at 20 W output 18 V to 60 V 12 V to 60 V 3.35 V +/- 100 mV at 6 A
Parameter VIN Auxiliary VIN AUXI Auxiliary VIN AUXII
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3
8/47
Chassis
RJ45 Data and Power Jac
k
Chassis
T3
10
1312 5 4
RJ45 Data Jac k
10
16
1
2 3 6 7 8
H2019 / TLA-6T127LF
R6 NM 080 5
R7 NM 080 5
C7
Figure 2.
1 2 3 4 5 6 7 8
15 14 11
1 2 3 4 5 6 7 8
R1
9
9
J2
J1
10 9
0 0805
Chassis
Chassis
OUTPU T
INPU T
TP1
R2
Demonstration kit schematic
R3
R4 NM 080 5
NM 0805
9 6 10 5 11 4
12
R5
NM 0805 200V
NM 0805 200V
8
7
T4
C6
D18 STPS1H10 0 SM A
1
1
NM 0805
NM 0805
C3 NM 0805 200V
Chassis
Ter mination To be placed on solder side
R30 0 1206 Chassis
+
4
D22 STPS1H10 0 SM A
+
D24 STPS1H10 0 SM A
3
D20 STPS1H10 0 SM A 4
D3 SMAJ58 A
3 2
13
3
C1 0.1u 0805 100V
C2 NM 0805 200V
C8
NM 0805 200V
NM 0805 200V
C4
C5
D1 D19 DF01S N M D21 STPS1H10 0 2 STPS1H10 0 SMA SMA
TP 2
1
14
15 16
ETH1-230LD
D2 D25 D23 DF01S N M STPS1H10 0 STPS1H10 0 2 SM A SMA
SEE BO M
NM 1808 2K V
Chassis
R8
NM 251 2
NOTE for 2512 Power Resistors The resistors must be placed on solder side, belhind the SO8 body.
R9
STS10PF30L
NM 251 2
NOTE for dataTransformer s The H2019 footprint will be placed inside the ETH1-230LD one
Ter minatio n To be placed on solder sid e
DC Power Jac k
3 2 1 8 7 6 5
TP3
D4
AUX II
SO8 Q1
1 2 3
3
D5
J4
BZX84C15 SOT23 R5 0
C27 0.1u
R10 4 330 K 080 5
STTH302 S SMC
NOTE for Power Transformer The 13P footprint will be placed inside the FA2706 footprint
R11 15K 080 5
D6
1
T2
3
10 9
NOTE for Output Inductor The 1206 footprint will be placed between the inductor pad s
0
C41 0.1u 080 5 100V
BAT46J NM SOD323
R12 330 K 080 5
4 1
8 7
NOTE for Output Rectifier The DPack footprint for the diode will be on top side. The Power SO8 footprint of the mosfet and the Snubber on solder side.
R13 15 120 6 1 C11 470p 0805
TP4
Demonstration kit schematic
DC Power Jac k
2
COILCRAFT POE13P
D7
GND
SMC STTH302 S
TP5
R1 4 NM 1206
AUXI_IRL
L1
1 2 3
1
2
TP6
3
SEE BO M
SEE BO M
4
STPS15L30CB DPac k D8 TP 7
J3
3.3uH ME3220-332ML
C13
1
Demonstration kit schematic
R15 15K
C14
2.2u 1812 100V 2.2u 1812 100V
C15 C17
T1
NM
TP14
OU T
0805
22u 100 V 8x10.2
D9 SMAJ58 A
3 4
R16 NM 1206
C16 NM 080 5
DC OUTPU T
3 2 1
10 9
2.2u 1812 100V
D10 STPS1H100 SM A
8 7 6 5 4
SEE BO M
BAS21 SOT2 3
GND
L3 NM SEE BO M 2 0.33uH DO1813H-331ML L2 2 1 0.33uH LPS401 2-331 L
Q2 STSJ60NH3LL PowerSO 8
R17 1k
D2 6
5 6
C18
C1 9
C20
C21
C23
R49 NM SEE BO M
SOD323 BAT46J
R1 8
11 12
C24
10u 6.3 V 1206
10u 6.3 V 1206
10u 6.3 V 1206
10u 6.3 V 1206
C39
Green LED
1
J5
0.1u
330u 6.3 V 8x10.5
D11
TP9
R23 10k
10u 6.3 V 1206
2
2
R19 3.3k
7
D14
10
1
8
COILCRAFT FA2706 -BL
D12 3
D1 3
R TN
11 BZX84C18 SOT23
3 BZX84C18 SOT23
TP8
D15
TP13
C40
C2 6
C42 NM
Green LED
C25 1u 16V 060 3
Sync Input
C34
100p N M R48 NM
R21 88.7K 1%
0.1u
AGN D
C28
0.1u
0.1u
GND
NOTE PowerSO8 footprint will be placed on the solder side behind the DPack one
R22 NM
R24
U1
AGN D
R25
BAT46 J
TP10
U2
SOD323 BAT46J D17 N M
0
0
R26 10
SOD323
CS nP GD
VCC
D16
5678
TP11
4
1
SEE BO M
4
2
R27 10k
R28 1k
3
2
Q3A N M
10 080 5
Sharp PC3H7
C30 1u 16V 0603
123
1
R33 100
PowerSO 8
R31
3
C31 NM
AGN D
C32 0.1u
GD GND
Q3 STD22NM20L DPac k
R29 1k
R34
R32 21k 1%
R41
C33 470p
NM
R36 NM
C36
R35 080 5 NM 1%
16 R T 1 RT AGND SS 15 2 VFB SS AUXII 14 3 COM P AUXII VIN 13 4 CS VIN 12 5 nPGD RCLAS S RCLASS 11 6 VCC AUXI_I RL AUXI_IRL 7 Ex Pad GD 10 DCCL DCC L 9 VSS 8 VS S GND 17 PM8800 R37 HTSSO1 6 15k 1%
R38 10k
R40 R39 0.47 ohm 0.47 ohm 1206 1206
R4 6 NM 1206
TP1 2
R42 0
NM 120 6
C37
C35 SEE BO M 22n
R43
3
4.7n
0.1u NM 080 5 D27 NM 100V
STPS1H100 SM A
GND
AGN D
U3 TS431 SOT23-5
4 5
R2 0 NM 1206 C29
SEE BO M
10k 1%
R47 NM 1%
R44 12.4 k 1%
NOTE for Resistors Where not indicated the bod y is 0603 and tolerance 5 %
NOTE for Capacitors Where not indicated the bod y is 0603 and the volta ge is 50 V
NOTE The AGND is a dedicated plane of si gnal ground that will be connected to th e GND power ground plane close to pin 9 of PM880 0
GND
AN2783
AM01333v1
2.2n 1812 2KV
NOTE Those components will be placed on the solder sid e
AN2783
Board layout
4
Board layout
Figure 3. Assembly view: top and bottom layer
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Board layout Figure 4. Top layer
AN2783
Figure 5.
Inner layer 1
Figure 6.
Inner layer 2
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AN2783 Figure 7. Bottom layer
Board layout
4.1
Input/output connectors
In Figure 3 the main input / output connections of the reference board are presented:
J1 is the RJ45 connector for the PoE input, with data and power applied through the CAT5 cable (as an alternative, a positive voltage between 30 V and 60 V can be applied to test points TP1 + and TP2 -) J2 is the RJ45 data output J3 is the power jack for AUXI input (as an alternative, the test points TP 3 + and TP4 can be used) J4 is the power jack for AUXII input (as an alternative, the test points TP5 + and TP9 can be used) J5 is the DC output connector
4.2
Notes
Please note that the use of TP1 and TP2 limits the voltage polarity applied and that these points are after the data transformer and diode bridges. AUXII is not protected against reverse polarity applied to it. For synchronization tests the capacitor C40 =100 pF must be mounted. Please take care when using test point TP13 because this is a high impedance point that can easily pick up noise from the board. Resistive or electronic loads can be used as loads. Limit the output capacitance externally applied in order to not impact the loop compensation. As an input source a DC power supply with 60 V and 2 A capability is required. For auxiliary inputs a DC source of 60 V and 3 A capability is recommended.
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Bill of material
AN2783
5
Table 2.
3.3 V high power 3.3 V std power
Bill of material
Components for the 4 isolated configurations possible with the PM8800
5 V high power 5 V std power
Reference
Description
Pkg
Manufacturer
Qty
Qty
Qty
Qty
Printed circuit board 1 1 1 1 PM8800 eval kit(1)
Capacitors 1 NM NM NM NM NM 1 1 2 NM NM 2 3 NM NM NM 1 2 5 1 NM 1 1 NM NM NM NM NM 1 1 2 1 NM 2 3 NM NM NM 1 2 5 1 NM 1 1 NM NM NM NM NM 1 1 2 NM NM NM NM 2 3 NM 1 2 5 1 NM 1 1 NM NM NM NM NM 1 1 2 1 NM NM NM 2 3 NM 1 2 5 1 NM 1 C1 C36 C2, C7 C8 C9 C10, C12 C11 C13 C14, C15 C17 C16 C18, C19 C20, C21, C23 C18, C19 C20, C21, C23 C22, C38 C24 C25, C30 C26, C27, C28, C34, C39 C29 C31 C32 Ceramic cap 0.1 F 100 V Ceramic cap 0.1 F 100 V Ceramic cap 200 V Ceramic cap 2 kV Ceramic cap Ceramic cap Ceramic cap 470 pF 50 V Electrolytic cap 22 F 100 V KX Ceramic cap 2.2 F 100 V Ceramic cap 2.2 F 100 V Ceramic cap Ceramic cap 10 F 6.3 V Ceramic cap 10 F 6.3 V Ceramic cap 10 F 16 V Ceramic cap 10 F 16 V Ceramic cap Electrolytic cap 330 F 6.3 V EX Ceramic cap 1 F 16 V Ceramic cap 0.1 F 50 V Ceramic cap 2.2 nF 2 kV Ceramic cap Ceramic cap 0.1 F 50 V 805 805 805 1812 805 805 805 8 x 10.2 1812 1812 805 1206 1206 1206 1206 1206 8 x 10.5 603 603 1812 603 603 TDK NM NM NM NM NM Std SANYO TDK TDK NM TDK TDK TDK TDK NM SANYO TDK Std TDK Std Std
12/47
AN2783 Table 2.
3.3 V high power 3.3 V std power
Bill of material Components for the 4 isolated configurations possible with the PM8800 (continued)
5 V high power 5 V std power
Reference
Description
Pkg
Manufacturer
Qty 1 1 NM 1 NM 1
Qty 1 NM 1 1 NM 1
Qty 1 1 NM 1 NM 1
Qty 1 NM 1 1 NM 1 C33 C35 C35 C37 C40 C41 Ceramic cap 470 pF 50 V Ceramic cap 1 nF 50 V Ceramic cap 22 nF 50 V Ceramic cap 4.7 nF 50 V Ceramic cap 100 pF 50 V Ceramic cap 0.1 F 100 V 603 603 603 603 603 805 Std Std Std Std Std TDK
Diodes NM 2 1 2 1 NM 1 1 1 2 2 1 1 NM NM NM NM NM NM 1 2 1 NM NM 1 1 2 2 1 1 NM 8 1 NM NM 2 1 2 1 NM 1 1 1 2 2 1 1 NM NM NM NM NM NM 1 2 1 NM NM 1 1 2 2 1 1 NM 8 1 NM D1, D2 D1A, D2A D3 D4, D7 D5 D6 D8 D9 D10 D11, D15 D12, D13 D14 D16 D17 D18 : D25 D26 D27 Diode bridge DF01S Diode bridge HD01 Diode SMAJ58A Diode STTH302S Diode Zener BZX84C15 Diode BAT46J Diode STPS15L30CB Diode SMAJ40A Diode STPR120A Diode green LED Toshiba TLGE1100B Diode Zener BZX84C18 Diode BAT46J Diode BAS316 Diode BAT46J Diode STPS1H100A Diode BAS316 STPS1H100A Dip MiniDip SMA SMC SOT23 SOT323 DPACK - TO252 SMA SMA SMD SOT23 SOT323 SOT323 SOT323 SMA SOT323 SMA Diodes Diodes STMicroelectronics STMicroelectronics Std STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics Toshiba Std STMicroelectronics Std STMicroelectronics STMicroelectronics Std STMicroelectronics
Connectors 2 2 1 2 2 1 2 2 1 2 2 1 J1, J2 J3, J4 J5 Shielded RJ45 8-pole DC power jack THT RAPC722 DC power connector 2-pole THT THT pitch 5.08
Inductors
13/47
Bill of material Table 2.
3.3 V high power 3.3 V std power
AN2783
Components for the 4 isolated configurations possible with the PM8800 (continued)
5 V high power 5 V std power
Reference
Description
Pkg
Manufacturer
Qty 1 1 NM
Qty 1 NM 1
Qty 1 1 NM
Qty 1 NM 1 L1 L2 L3 Inductor 3.3 H ME3220-332ML Inductor 0.33 H LPS4012331L Inductor 0.33 H DO1813H331ML Coilcraft Coilcraft Coilcraft
MOSFETs 1 NM 1 NM 1 1 NM 1 1 NM 1 NM 1 1 NM 1 Q1 Q2 Q3 Q3 Mosfet STS10PF30L Mosfet STSJ60NH3LL Mosfet STD5N20L Mosfet STD22NM20M SO-8 PowerSO-8 DPACK - TO252 DPACK - TO252 STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics
Resistors 1 NM NM 2 1 1 1 NM 1 1 1 1 NM 3 2 1 1 1 1 NM NM 2 1 1 1 NM 1 1 1 1 NM 3 2 1 1 1 1 NM NM 2 1 1 1 NM 1 1 1 1 NM 3 2 1 1 1 1 NM NM 2 1 1 1 NM 1 1 1 1 NM 3 2 1 1 1 R1 R2:R7, R35 R8, R9 R11, R15 R10 R12 R13 R14, R16, R20, R41 R17 R18 R19 R21 R22, R34, R36 R23, R27, R38 R24, R25 R26 R28 R29 Resistor chip 0 Resistor chip Resistor chip 2.2 Resistor chip 15 k Resistor chip 330 k Resistor chip 33 k Resistor chip 15 Resistor chip Resistor chip 1 k Resistor chip 10 Resistor chip 3K3 Resistor chip 88K7 1% Resistor chip Resistor chip 10 k Resistor chip 0 Resistor chip 10 Resistor chip 1 k Resistor chip 1 k 805 805 2512 805 805 805 1206 1206 603 603 603 603 603 603 603 603 603 603 Std Std Std Std Std Std Std Std Std Std Std Std Std Std Std Std Std Std
14/47
AN2783 Table 2.
3.3 V high power 3.3 V std power
Bill of material Components for the 4 isolated configurations possible with the PM8800 (continued)
5 V high power 5 V std power
Reference
Description
Pkg
Manufacturer
Qty 1 1 1 1 NM 2 NM 1 1 1 NM NM NM 1 1
Qty 1 1 1 1 1 2 NM 1 1 1 NM NM NM NM 1
Qty 1 1 1 1 NM 2 NM 1 1 1 NM 1 NM 1 1
Qty 1 1 1 1 1 2 NM 1 1 1 NM 1 NM NM 1 R30 R31 R32 R33 R37 R39, R40 R20, R41 R42 R43 R44 R46 R47 R48 R49 R50 Resistor chip 0 Resistor chip 10 Resistor chip 21 k 1% Resistor chip 100 Resistor chip 15 k 1% Resistor chip 0R47 Resistor chip 0 Resistor chip 0 Resistor chip 10 k 1% Resistor chip 12K4 1% Resistor chip 0R47 Resistor chip 15 k 1% Resistor chip 10 k 1% Resistor chip 0 Resistor chip 0 1206 805 603 603 603 1206 1206 603 603 603 1206 603 603 603 603 Std Std Std Std Std Std Std Std Std Std Std Std Std Std Std
Transformers NM NM 1 NM 1 NM 13 ICs 1 1 1 1 1 1 1 1 1 1 1 1 U1 U2 U3 PM8800 Optocoupler PC3H7 TSA431AILT SOT23-5 HTSSOP16 STMicroelectronics Shar p STMicroelectronics 1 NM NM NM NM 1 13 NM NM NM 1 1 NM 13 NM 1 NM NM NM 1 13 T1 T1 T2 T2 T3 T4 TP1:TP13 Transformer EFD17 FA2706-BL Transformer EFD17 FA2707-BL Transformer EP13 PoE13P-33L Transformer EP13 PoE13P-50L Transformer H2019 / TLA6T127LF Transformer ETH1-230LD Test point 5013 Coilcraft Coilcraft Coilcraft Coilcraft Pulse/TDK Coilcraft Keystone
1. PM8800 demonstration kit printed circuit board has been manufactured with the following Cu layer thicknesses: Layer 1, 4: 35 m (1 oz.) (top / bottom side) Layer 2, 3: 35 m (1 oz.) (power plane)
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Power-up sequence
AN2783
6
Power-up sequence
It is recommended to apply power at the PoE input first, slowly increasing the voltage to verify the absence of abnormal input current levels. From 1.5 V to 11.5 V input, the signature phase, the PM8800 presents a 24.5 k nominal resistor as load. After that in the range 11.5 V to 23 V, the classification phase, the PM8800 draws about 1.5 mA plus the current fixed with the classification resistance, if mounted. After those two steps are verified, the voltage can be increased to 48 V typical. Two green LEDs indicate proper operation of the PoE and DC/DC section of the PM8800 demonstration kit. D15 is the nPGD LED and is on when the internal hot-swap MOSFET is closed, while D11 indicates the presence of the output voltage.
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AN2783
Input section
7
7.1
Input section
Diode bridges
Two diode bridges are required at the input because PD must be able to accept voltage from an Ethernet cable with undefined polarity and coming from either Tx and Rx or spare pairs. Diode bridges must be at least 0.5 A to 1 A, 100 V . They contribute to increasing the resistance presented by the PD to the PSE during the signature phase. For this reason the internal signature resistance is set to 24.5 k. Care must be taken to not exceed the standard accepted values between 23.75 k and 26.25 k. On the high-power board the diode bridges are replaced with discrete Schottky diodes, that due to the lower voltage drop, allow lower losses at high output power.
7.2
Input capacitors
The IEEE802.3af standard requires a capacitor whose values are between 50 nF to 120 nF during the signature phase and a minimum of 5 F during the operating phase. A 100 nF, 100 V ceramic capacitor is used, placed near the VIN pin of PM8800. In order to reduce the conducted emission, a C-L-C input filter has been designed with a 100 V aluminum capacitor at the input side, a 3.3 H inductor and three 100 V ceramic capacitors on the output side. The resonant frequency of the filter is: Equation 1
1 F r e q = --------------------------------------( 2 L Cc e r )
It has been selected to be about 5-10 times above the control loop bandwidth, to not impact the stability of the control loop. Equation 2
Ip r m s C c e r ----------------------------------------------( 8 Fs w Vr i p p l e )
7.3
Transient voltage suppression
The PD in some circumstances (ringing, overshoot transients, static electricity, ground differences, etc.) can see hundreds or thousands of volts at its RJ45 input connector. The energy associated with these voltages can be quite large. A transient voltage suppressor (TVS) is typically applied at the input of the PD, after the diode bridge, in parallel to the 100 nF input capacitor. The TVS must absorb this energy, but the PD interface must be designed to withstand an additional 20 V or 30 V above the operating range until the TVS limits the voltage. The TVS must be selected with a standoff voltage higher than the maximum voltage of 57 V defined in the PoE standard which means a clamping voltage that can easily reach 100 V.
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PoE section
AN2783
With the SMAJ58A the standoff is 58 V and the clamping voltage for a standard 10/1000 s transient is 93 V. PM8800 is able to withstand transient voltage up to 100 V without any damage.
8
8.1
PoE section
Signature
Signature is the first phase in the PoE standard and allows a PSE (power source equipment) to recognize the presence of a PD (powered device) that can accept power on the Ethernet cable. The PM8800 integrates a 24.5 k resistance to simplify a standard PoE PD interface design. Its value has been chosen to take into account the voltage drop across the diode bridge and its effect on the effective resistor value presented at the RJ45 connector input. This resistor is disconnected for input voltages higher than 11.5 V. The required signature capacitance is obtained with C1= 100 nF, 100 V.
8.2
Classification
Classification is the second phase in the PoE standard and allows the PSE to allocate the right amount of power for the PD connected on a single port. The IEEE802.3af standard defines 4 power classes. PM8800 has a dedicated pin for the classification resistor. The reference board has R35 left open, corresponding to CLASS 0. To select a different class please refer to the table below: Table 3. RCLASS resistor value
802.3af classification current (mA) CLASS 0 1 2 3 4 PD power(W) 0.44 -12.95 0.44 - 3.84 3.84 - 6.49 6.49 - 12.95 Reserved RCLASS() Open 158 82.5 52.3 36.5 min. 0 9 17 26 36 max 4 12 20 30 44
To provide a constant current during the classification phase, PM8800 has an internal voltage regulator that maintains 1.4 V typ. across the classification resistor. The value of R35 is calculated taking into account the power consumption of PM8800 during the classification phase, which is about 1.5 mA.
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AN2783
PoE section R35 is disconnected at the end of the classification phase, when the input voltage rises above 23 V.
8.3
UVLO and power-on
Power-on is the final state after successful detection and classification. The input voltage is increased and an internal switch is closed to connect the PD load. The inrush current is actively limited by the PM8800 itself. The PM8800 is fully compliant with UVLO thresholds and inrush current limits defined in the IEEE802.3af standard.
8.4
Inrush current limit
The inrush current in PM8800 has a three-step limit depending on the voltage across the hot-swap MOSFET. The first two steps are fixed at 140 mA and 250 mA respectively, the last step has a default value of 440 mA and it is programmable. The external resistor to select the desired inrush current is found with the following formula: Equation 3
R I R L [ k ] = ----1-------0--------12---0 II R L [ m A ]
Figure 8.
Inrush current limit vs. RIRL
90
RIRL [kOhm]
70 50 30 10 100 150 200 250 300 350 400 450 500
IIRL [mA]
The PM8800 useful programming range for the inrush current limitation is between140 and 440 mA. The practical resistor value ranges between 25 k and 82 k. Depending on the application, attention must be given to the choice of the inrush current limit to avoid that the voltage drop on the external Ethernet cable causes UVLO conditions during the charging phase of the bulk capacitor. It is recommended to select this voltage drop (can be estimated as max: 20 x I inrush) to be lower than the UVLO hysteresis (7 Vmin) in order to avoid hiccup turn-on. The inrush current is set to the default three-step values when the AUXI pin is pulled up over the 2 V internal threshold by an auxiliary voltage.
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PoE section
AN2783
Programming inrush current limit resistor R38 on the PM8800 reference board is left open, thus the limits are set to the default values.
8.5
DC current limit
The continuous current limitation is internally set at 440 mA, but it is possible to modify it by connecting a resistor between DCCL and VSS. This limitation is active after setting nPGD, but in case the selected value is lower than the default inrush current, it also applies during the inrush current phase. The formula to select the desired DC current is the following: Equation 4
11200 R D C [ k ] = ---------------------ID C [ m A ]
Figure 9.
DC current limit vs. RDC
900 800 700 600
IDC [mA]
500 400 300 200 100 0 10 20 30 40 50 60 70 80
R DC [kohm]
The PM8800 useful programming range for the DC current limitation is between 150 mA and 800 mA. The practical resistor value ranges between 15 k and 75 k. Please note that the DC current limit is not linked to the inrush current limit, both limits can be set independently of each other. Different current limits occur at different voltage drops between VSS and GND regardless of the PM8800 operative phase:
For a drop < 3 V, the DC limit occurs with a default value of 440 mA For a drop > 3 V but < 15 V, the 3rd step of inrush current occurs with a default value of 440 mA For a drop >15 V and < 30 V, the 2nd step of inrush current occurs with a default value of 250 mA For a drop > 30 V, the 1st step of inrush current occurs with a default value of 140 mA
We suggest putting the DC limit over the inrush current which allows avoiding an increase of current limiting during protection phases. Programming DC current limit resistor R37 on the PM8800 standard reference board is left open, leaving the default value as the limit, while a 15 k is mounted on the high-power version, putting the limit at 740 mA typ.
20/47
AN2783
PoE section
8.6
AUXI input
The PM8800 reference board accepts auxiliary power sources applied before the hot-swap MOSFET as low as 18 V (16 V seen at the pin VIN of device). To do so and change the UVLO levels, the AUXI pin must be pulled up above 2 V with a current greater than 70 A. The AUXI pin can be connected to the auxiliary voltage through a diode. In this case the current flowing into the pin is internally limited to about 300 A. Depending on the output current drawn, the real operative AUXI voltage can be higher than the above mentioned value, basically due to the DC current limitation which is maximum input power at minimum applied on AUXI = 16V x 800 mA =12.8 W. Another limitation on the operative AUXI voltage can be the power transformer, not designed to work with a wide input voltage range for the maximum output power.
8.7
AUXII input
PM8800 can also accept auxiliary power sources applied after the hot-swap MOSFET as slow as 12 V (9 V seen at the pins of device). In this case there is no current limitation and an external circuit is recommended in order to limit the inrush current. On the PM8800 reference board an active switch is implemented with a P-channel power MOSFET, capable of limiting the inrush current at startup and with very low ohmic drop during operation. AUXII prevalence over PoE can be programmed forcing a current higher than 100A in pin AUXII of PM8800. In this case the PD is always powered from AUXII power source because the interface circuits and the hot-swap MOSFET are forced in an off state. The pin can be connected to the auxiliary voltage through a diode. In this configuration the current flowing into the pin is internally limited to about 250 A. AUXII can be conveniently used in case of high-power PDs requiring input power higher than the 12.95 W specified in the IEEE802.3af standard. Please note that having the hot-swap MOSFET in an off state means having the IC substrate in high impedance with GND. It is strongly recommended to move the signature capacitor of 100 nF from the C1 position to C36. This capacitor is placed between VSS and GND, implementing a low-impedance circuit at high frequency across the hot-swap MOSFET, assuring a good HF connection of the IC substrate. The PM8800 reference board is preset for AUXII prevalence over PoE, having R23 set to 10 k.
Warning:
In case of AUXII low input voltage sources, the condition VIN < VCC must be avoided because of possible damage to the device.
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Power transformer and operating input voltage
AN2783
9
Power transformer and operating input voltage
The PM8800 demonstration kit can contain two different types of power transformers: Table 4. Characteristics of the power transformer for the PM8800 evaluation kit
Type Lprimary N Ipeak sat Rsec
PoE13P-33L / 50L FA2706-BL / 07-BL
127 H
70 H
6/4 6.8 / 4.85
1A 3.5 A
24 m/ 39 m 8 m/ 18.5 m
The standard EP13 transformer is designed to operate at full IEEE802.3af power when the input voltage is in the range 36-72 V. When working from auxiliary voltages lower than 36 V the output power must be reduced in order to not saturate the transformer. The custom transformer has been designed to work optimally over the full input range between 12 V to 60 V in order to exploit the AUXII connection option made available by the PM8800. FA2706/7-BL can be also used to draw more power than 10 W when restricting the input operational voltage range. For example about 20 W can be drawn with a minimum input voltage of about 30 V, the minimum operating voltage of the PoE standard range. Figure 10. Output power vs. VAUXII
Pou t vs VAUXII w it h FA270x-BL
25 20 Pout ( W ) 15 10 5 0 10 15 20 25 30 40 50 60 V AUXII ( V )
An auxiliary winding has been added in the FA2706/7-BL to directly drive a synchronous power MOSFET as a secondary rectifier, in order to reduce the power losses associated with a standard diode rectifier at high output currents. When working at very low input voltage, as in the case of AUXII, the diode D6 can be added, (actually not mounted on the reference board) to directly supply the VCC pin of PM8800.
Warning:
In this condition please do not increase the AUXII voltage above 15 V as permanent damage can occur to the device.
22/47
AN2783
Power converter
10
Power converter
The PM8800 reference board implements a flyback converter operating in DCM (discontinuous mode) at low output power and in CCM (continuous mode) for medium to high output power. The output secondary rectifier can be a classic diode for low to medium output power or a synchronous rectifier for high output current. Flyback configuration is the standard choice for a low-power isolated converter. It is the simplest isolated converter, using the lowest number of power components. CCM has been selected in order to reduce the stress on the power components, especially on the secondary side. CCM is assured only at medium to full output power, while in low output power the converter works in DCM which allows reducing the size of the power transformer. It is out of the scope of this document to show the whole flyback converter theory, which can be found in every basic power supply handbook. In this application note we focus only on the aspects directly related to the use of the PM8800 in a flyback converter.
10.1
Flyback continuous conduction mode
The flyback converter is in DCM when the energy stored during the ON phase has been completely transferred to the secondary side during the OFF phase. This means that a small period of time still remains during which no current is flowing on either side of the power transformer. When this period of time does not exist, i.e. when the energy stored has not been completely transferred during the ON phase, the flyback is said to work in CCM. Compared to CCM, DCM presents higher peak and rms current values on the primary switch and on the output rectifier. This implies higher output ripple and require bigger input and output filters. CCM presents an RHP zero, which slightly complicates the control loop compensation. A flyback converter designed to work in CCM is also stable in DCM. The transfer function of a flyback in CCM is: Equation 5
(Vin Vds ) Ton = (Vout + Vd ) N (Tsw Ton )
The above equation can be written as: Equation 6
(------------------------------ = -------------------------D -Vout + Vd) (Vin Vds) N (1 D)
23/47
Power converter The maximum duty cycle can be obtained as: Equation 7
Tonm a x -------------------- = ----------------------N-------------------t-------V------------------------------- ( V o u - + --- d ) Tsw ( V i nm i n V d s ) + N ( V o u t + V d )
AN2783
10.2
Main switch current and current sensing
The current shape in the primary power switch is different when the flyback converter is working in DCM or CCM. In DCM the shape is triangular with the current starting from zero, while in CCM the shape is trapezoidal. For CCM operations the peak current can be computed as: Equation 8
I V i nm x Dm a x T s w I o -- t -I p e a k = I p a v e + ------L = -----------------------u------------------- + --------------a------------------------------------2Lp 2 N ( 1 Dm a x )
which can be expressed as: Equation 9
V i nm x Dm a x T s w Pout I p e a k = --------------------------------------------------------- + --------------a------------------------------------- Dm a x ( V i n V d s ) 2Lp
The RMS current can be: Equation 10
Iprms = I I 2 -D m a x I p e a k I p e a k ------L + ------L-- 2 3
2
The above formula can be used to calculate the right current sense resistor, taking into account that the first level of OCP is for PM8800 at 500 mV: Equation 11
5---0 ---- V R c s = --------0----m--------1.3 I p e a k
The associated power dissipation on the sense resistor is: Equation 12
Pcs = Rcs Iprms
2
10.3
Main switch power dissipation
The power dissipation on the main power MOSFET is the sum of two terms:
24/47
AN2783 Equation 13
P c o n d = R o n I p r m s Dm a x
2
Power converter
oss Vds Fs P s w i t c h i n g = C-----------------------------------------w + V d s m a x I p e a k T m F s w -----2
2
where Equation 14
V d s m a x = 1.2 [ ( V i n m a x + V s p i k e ) + N ( V o u t + V d ) ]
Vspike is due to the leakage inductance of the power transformer and can be assumed to be 40 V max, as the snubber network on the primary side is built with a TVS with breakdown voltage of 40 V. Tm is the time to charge the Miller capacitor of the power MOSFET and can be estimated as: Equation 15
Qgd - Rg T m = ------------------------------Vcc Vgsth
Note that if the major contribution to the MOSFET losses comes from the second term of the switching power losses, the right choice is for a low gate charge power MOSFET.
10.4
Rectifier diode dissipation
The secondary output current is: Equation 16
I o u tm x [ ( V o u t + V d ) ( T s w T o n ) ] I L --I s p e a k = I s a v e + ------S--- = -----------------a--- + -------------------------------------------------------------------------2 2 1 Dm a x (Lp) / N I L 2 -( 1 D m a x ) I s p e a k I s p e a k I S L + ------S--3
2
Isrms =
The reverse voltage across the rectification diode is: Equation 17
V i nm x V r d i o d e = --------------a-- + V o u t -N
The power dissipated in the secondary diode, neglecting the reverse leakage losses, can be estimated as: Equation 18
Pd i o d e = I s r m s V d ( 1 Dm a x )
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Power converter
AN2783
10.5
PM8800 internal power dissipation
A calculation must be done to verify that the PM8800 maximum junction temperature has not been exceeded. Major contributions to internal power dissipation are: star tup circuit power MOSFET gate driver hot-swap MOSFET
internal circuitry It is strongly recommended to use an additional winding to generate an auxiliary VCC voltage of 9 V minimum, which switches off the internal startup circuit after the power-up of the conver ter. As mentioned before, the converter power MOSFET must be chosen as a good compromise between low Ron and low total charge. The internal power dissipation associated to the gate drive is: Equation 19
Pd r i v e = V c c Q g F r e q
The hot-swap MOSFET dissipates internally: Equation 20
Ph o t s w a p = R o n I i n
2
Internal power dissipation is due to circuits that draw current directly from VIN, like the hotswap controller or other logic circuits powered from VCC: Equation 21
P d e v i c e = V i n I i n + V c c I log i c
Typical operative values are Iin = 5 mA and Ilogic = 3 mA. The total power dissipated by PM8800 is: Equation 22
Pt o t = Pd r i v e + Ph o t s w a p + Pd e v i c e
The following relationship must be satisfied: Equation 23
Ta m b + Pt o t R t hj a < Tj m a x
where a typical value of Rth for PM8800 mounted on the ref board is 85 C/W and Tjmax is 150 C.
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AN2783
Layout guidelines
11
Layout guidelines
We suggest the following guidelines for the layout of the PM8800:
Place the component group including input ceramic capacitors, input side of transformer, power MOSFET and sense resistors close to each other in order to keep the interconnections as short as possible. Place the component group including secondary rectifier diode, output side of transformer, output ceramic capacitors close to each other in order to keep the interconnections as short as possible. Place the PM8800 in such a way as to have a short path to the gate of the power MOSFET. Use a 20-30 mils wide path for this signal. Ground: there are basically 4 different grounds on the board (VSS, GND, RTN and chassis ground). The exposed pad of PM8800 must be connected to VSS. Design a fill area with at least 6 vias to the VSS plane. Try where possible to increase the number of VSS power planes connected, at least below the PM8800 position, to improve the heat dissipation of PM8800. GND must be divided into power gnd (to connect input caps, Rsense, PM8800 pin 9, AUXII circuitry, isolation cap) and signal gnd (to connect the other components around the PM8800, the circuitry powered by VCC voltage, and the IC pin 16). The signal gnd must be connected to power gnd in one point only, close to the PM8800 pin 9. Keep the power path on RTN (output side of transformer, secondary diode, output connector) separated from the feedback network gnd, which is connected only at the connector side.
Design the power MOSFET area with at least 9-12 vias of connection to the internal copper area. Try where possible to increase the number of power planes connected, at least below the MOSFET position, to improve the heat dissipation. Design the secondary rectifier diode with at least 9-12 vias of connection to the internal copper area. Try where possible to increase the number of power planes connected, at least below the diode position, to improve the heat dissipation. Chassis: design copper areas on both side of the PCB. Do not place other grounds or signals under the RJ45 and the data transformer area. Place any termination network on the bottom side.
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Layout guidelines More in detail: Place the TVS close to the input diode bridges, if possible on the same side 1. 2. 3. 4. 5. 6. 7. 8. 9.
AN2783
Place the PM8800 and all the related components close to each other, use both sides Place all the feedback components close to each other, use both sides Place the sense resistors close to the power MOSFET, if possible on the same side Place the input ceramic capacitors close to the input side of power transformer, if possible on the same side Place the primary snubber network close to the power transformer, on the bottom side Place the rectifier diode close to the output side of the transformer, if possible on the same side Place the secondary snubber network close to the rectifier diode, bottom side Place the output ceramic capacitors close to the rectifier diode and the power transformer, on the copper areas, top side Place the last ceramic capacitors close to the output terminal of the power connector, bottom side
10. Place the 100 nF input capacitor close to the VSS and GND pins 11. Place the decoupling capacitors for VCC close to the relevant PM8800 pin 12. Place the components for RT and SS pins in a quiet area, separated as much as possible from other signals 13. Use paths of at least 20 mils for signals connected to the IC pins 5,10,11 14. Connect the PM8800 pins 8,9,16 directly to the copper areas 15. Use a wide path or copper area for VIN, AUXI and AUXII networks
28/47
AN2783
Test results
12
12.1
Test results
Efficiency measurements
Figure 11. 5 V out - standard board with diode rectification
90%
85%
80% Efficiency
75%
70%
5Vou t DC-DC
65%
5Vout Overall
60% 0 .0 0 0 .5 0 1 .0 0 Io u t [A] 1 .5 0 2 .0 0 2 .5 0
Figure 12. 5 V out - high-power board with synchronous rectification
90%
85%
80% Efficiency
75%
70%
65%
5Vou t HP DC-DC 5Vou t HP overall
60% 0 .0 0 .5 1 .0 1 .5 2 .0 2 .5 3 .0 3 .5 4 .0 4 .5 Io u t [A]
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Test results Figure 13. 3.3 V out - standard board with diode rectification
90%
AN2783
85%
80%
Efficiency
75%
70%
3 . 3 Vo u t DC-DC
65%
3 . 3 Vo u t overall
60% 0 .0 0 .5 1 .0 1 .5 2 .0 2 .5 3 .0 3 .5
I o u t [A]
Figure 14. 3.3 V out - high-power board with synchronous rectification
9 0% 8 5% 8 0% Efficiency 7 5% 7 0%
3 . 3 Vo u t HP DC-DC
6 5% 6 0% 0 .0 0 .5 1 .0 1 .5 2 .0 2 . 5 3 .0 3 . 5 4 .0 4 . 5 5 . 0 5 .5 6 .0 6 .5 I o u t [A]
3 . 3 Vo u t HP overall
In the following pages are shown tests done on the 5 V high-power version and 3.3 V standard version of the reference board. Similar results and behaviors could be obtained with the 3.3 V high-power version and 5 V standard versions.
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AN2783
Test results
12.2
5 V high-power board measurements
Figure 16. Startup of the PM8800 demonstration kit with 5 V 4 A
Figure 15. Startup of the PM8800 demonstration kit with 5 V 1 A
Ch1= output voltage, Ch2 = VSS voltage with respect to GND, Ch3 = VCC voltage, Ch4 = input current Figure 17. Details of the inrush phase Figure 18. Details of the soft-start phase
Ch1= output voltage, Ch2 = VSS voltage with respect to GND, Ch3 = VCC voltage (left) and soft-start (right), Ch4 = input current.
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Test results
AN2783
Figure 19. VDS and VGS of the primary MOSFET for 5 V 1 A
Figure 20. VDS and VGS of the primary MOSFET for 5 V 4 A
Ch2 = primary side power MOSFET gate voltage, Ch3 = primary side power MOSFET drain voltage. Figure 21. Details of the synchronous rectifier MOSFET voltage with 48 V and 4 A out
Ch1 = secondary side power MOSFET drain-source voltage, Ch3 = primary side power MOSFET drain voltage
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AN2783
Test results
Figure 22. Output voltage ripple at 4 A output Figure 23. Output voltage ripple at 4 A output current current (1 sec persistence)
Figure 24. Dynamic load 1 A to 4 A: output voltage (up) and output current (down)
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Test results
AN2783
Figure 25. PM8800A response to a 6 A overload condition
Figure 26. PM8800A recovering from a 6 A overload condition
Ch1 = output voltage, Ch2 = soft-start voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = input current. Figure 27. PM8800A response to a short on the load Figure 28. PM8800A recovering from a short on the load
Ch1 = output voltage, Ch2 = soft-start voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = input current.
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AN2783 Figure 29. Internal short on the secondary winding
Test results
Ch1 = output voltage, Ch2 = soft-start voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = input current Figure 30. Switch between 48 V PoE and 24 V Figure 31. back to 48 V removing the 24 V AUXII with 5 V at 2 A AUXII voltage with 5 V at 2 A
Ch1 = output voltage, Ch2 = internal primary voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = AUXII input current
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Test results
AN2783
Figure 32. Switch between 48 V PoE and 12 V Figure 33. Back to 48 V removing the 12 V AUXII with 5 V at 2 A AUXII voltage with 5 V at 2 A
Ch1 = output voltage, Ch2 = internal primary voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = AUXII input current
12.3
3.3 V standard-power board measurements
Figure 35. Startup of the PM8800 demonstration kit with 3.3 V, 3 A
Figure 34. Startup of the PM8800 demonstration kit with 3.3 V, 1 A
Ch1= output voltage, Ch2 = VSS voltage with respect to GND, Ch3 = VCC voltage, Ch4 = input current
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AN2783
Test results
Figure 36. Details of the inrush phase
Figure 37. Details of the soft-start phase
Ch1= output voltage, Ch2 = VSS voltage with respect to GND, Ch3 = VCC voltage (left) and soft-start (right), Ch4 = input current Figure 38. VDS and VGS of the primary MOSFET for 3.3 V 1 A Figure 39. VDS and VGS of the primary MOSFET for 3.3 V 3 A
Ch2 = primary side power MOSFET gate voltage, Ch3 = primary side power MOSFET drain voltage
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Test results
AN2783 Figure 40. Details of the synchronous rectifier MOSFET voltage with 48 V and 3 A output current
Ch1 = secondary side power MOSFET drain-source voltage, Ch3 = primary side power MOSFET drain voltage Figure 41. Output voltage ripple at 3 A output Figure 42. Output voltage ripple at 3 A output current current (1 sec persistence)
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AN2783
Test results Figure 43. Dynamic load 1 to 3 A: output voltage (up) and output current (down)
Figure 44. PM8800A response to a 5 A overload condition
Figure 45. PM8800A recovering from a 5 A overload condition
Ch1 = output voltage, Ch2 = soft-start voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = input current
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Test results
AN2783
Figure 46. PM8800A response to a short on the load
Figure 47. PM8800A recovering from a short on the load
Ch1 = output voltage, Ch2 = soft-start voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = input current Figure 48. Internal short on the secondary winding
Ch1 = output voltage, Ch2 = soft-start voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = input current
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AN2783
Test results
Figure 49. Switch between 48 V PoE and 24 V Figure 50. Back to 48 V removing the 24 V AUXII with 3.3 V at 2 A AUXII voltage with 3.3 V at 2 A
Ch1 = output voltage, Ch2 = internal primary voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = AUXII input current Figure 51. Switch between 48 V PoE and 12 V Figure 52. Back to 48 V removing the 12 V AUXII with 3.3 V at 2 A AUXII voltage with 3.3 V at 2 A
Ch1 = output voltage, Ch2 = internal primary voltage, Ch3 = voltage across the hot-swap MOSFET, Ch4 = AUXII input current
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Test results
AN2783
12.4
IEEE 802.3af compatibility test
Additional tests of compatibility to the IEEE802.3af standard have been done with the PDA100 PD tester from Sifos Technologies. Results obtained with the 5 V, 2 A standard board are summarized inTable 5, 6, and 7. All tests have been successfully completed. Table 5. Compatibility test at -45 degC
Alt-A MDI Det. resistance Det. capacitance Class. current Class result Average power Max current Min current Av. current Turn-on voltage Turn-off voltage 25.18 k 0.109 F 1.4 mA 0 12.52 W 266.2 mA 260.3 mA 261.0 mA 40.0 V 33.9 V Alt-A MDI-X 25.16 k 0.092 F 1.4 mA 0 12.52 W 261.6 mA 260.3 mA 260.9 mA 40.0 V 33.9 V Alt-B MDI 25.25 k 0.109 F 1.4 mA 0 12.38 W 258.8 mA 257.4 mA 258.0 mA 40.0 V 33.1 V Alt-B MDI-X 25.25 k 0.103 F 1.4 mA 0 12.38 W 258.6 mA 257.3 mA 258.0 mA 40.0 V 33.1 V
Table 6.
Compatibility test at room temperature
Alt-A MDI Alt-A MDI-X 24.99 k 0.104 F 1.3 mA 0 12.53 W 262.0 mA 260.5 mA 261.2 mA 40.0 V 34.1 V Alt-B MDI 24.95 k 0.104 F 1.3 mA 0 12.34 W 257.7 mA 256.8 mA 257.2 mA 40.0 V 33.1 V Alt-B MDI-X 25.09 k 0.109 F 1.3 mA 0 12.34 W 257.6 mA 256.8 mA 257.1 mA 40.0 V 33.0 V
Det. resistance Det. capacitance Class. current Class result Average power Max current Min current Average current Turn-on voltage Turn-off voltage
24.90 k 0.103 F 1.4 mA 0 12.53 W 266.2 mA 260.7 mA 261.1 mA 40.0 V 34.2 V
Table 7.
Compatibility test at +85 degC
Alt-A MDI Alt-A MDI-X 25.49 k 0.112 F 1.3 mA 0 12.59 W Alt-B MDI 25.54 k 0.109 F 1.3 mA 0 12.36 W Alt-B MDI-X 25.57 k 0.103 F 1.3 mA 0 12.37 W
Det. resistance Det. capacitance Class. current Class result Average power
25.47 k 0.114 F 1.3 mA 0 12.59 W
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AN2783 Table 7. Compatibility test at +85 degC (continued)
Alt-A MDI Max current Min current Average current Turn-on voltage Turn-off voltage 267.2 mA 261.8 mA 262.3 mA 39.8 V 34.1 V Alt-A MDI-X 263.0 mA 261.8 mA 262.4 mA 39.7 V 34.1 V Alt-B MDI 258.6 mA 257.4 mA 257.7 mA 39.7 V 32.9 V
Test results
Alt-B MDI-X 258.6 mA 257.2 mA 257.8 mA 39.7 V 32.9 V
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10
10
9
R1 J2 Ch ass is 0 0 805
R J45 Data and Power Jack
J1
Ch a ss is
OUTPUT
INPUT
T P1 8 7 T4 R3 0 6 0 1 206 5 Ch ass is 11 12 3 2 13 T P2 1 14 4 10 D3 C1 0 .1 u 080 5 100 V
D1 8 D2 4 9
ST PS1H100 ST PS1H100
SMA
D2 0
D2 2
SMA
Schematic of high-power board
ST PS1H100
SMA
ST PS1H100
SMA
SMAJ58A
D1 9 D2 5
D2 1
D2 3
ST PS1H100
SMA
SMA
ST PS1H100
SMA
ST PS1H100
SMA
ST PS1H100
15
16
E T H1 - 2 30L D
DC Power Jack
3 2 1 S O8 S MC 4 Q1 8 7 6 5 D4
ST S10PF30L
T P3
AUX II
ST TH302S
R1 0 33 0K 0805
1 2 3
D5
3
B ZX84 C 1 5 S O T 23
C2 7 0. 1 u
J4
R5 0
R1 1 15 K 080 5 R1 2 3 30 K 0 805 C4 1 0. 1u 08 05 10 0V
1
0
T P4 GND
DC Power Jack
ST TH302S
15 12 06 D7 L1 1 2 3. 3uH ME32 20-3 32 ML C1 3 D9 C1 4 C1 5 C1 7 T1 TP7 T P6 R1 3
SMC
C1 1 4 70p 08 05
T P5
AUXI_IRL
1 2 3
J3
9
R J45 Data Jack
ST PS1H100A
S MA 5 6 G ND S O D3 23
ST SJ60NH3LL
Power SO8 11 12
4
2 D1 4 C2 5 10 1 R1 9 3 .3 k D1 5 C4 0 Gree n LED C2 6 100 p NM R2 1 0. 1u C3 4 0. 1u 0. 1u 8 8 .7 K 1% U1 RT 1 RT SS AUXII VIN RC L ASS AUXI_ IRL DC CL E x Pad VSS 17 17 GND 9 G ND GD 10 GD R3 3 1 00 C3 3 470 p R3 8 10 k R3 1 VCC 11 VC C 10 0 80 5 1 3 n PG D 12 n PG D 2 TP 11 CS 13 CS COMP 14 VF B 15 AGND AG ND 2 3 4 5 6 7 8 16 D1 6 AUXII VIN RC LASS A UXI_ IRL DC CL V SS SS A GND T P 10 GND R4 8 NM C2 8 1u 1 6V 0 60 3
7 D1 2 8 COILC RAF T F A27 06 -BL 3 11 B ZX84 C 1 8 S O T2 3 D1 3 3 B ZX84C 18 S OT 2 3
G re e n LE D
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Ch ass is 1 2 3 4 5 6 7 8 T P 14 L3 1 0.33uH Q2 D2 6 C1 8 C1 9 C2 0 C2 1 DO1 81 3H-3 31 ML C2 3 C2 4 0 .1 u 1 0u 6 .3 V 1 206 10 u 6. 3V 12 06 10u 6. 3 V 120 6 10 u 6. 3V 12 06 D1 1 330 u 6. 3 V 8x10. 5 10u 6. 3V 120 6 2 3 2 1 R1 7 1k C3 9 1 2 O UT
Appendix A
Ch a ss is
1 2 3 4 5 6 7 8
R1 5 15K 22u 100 V 8x1 0.2 2. 2u 1 81 2 1 00 V 2. 2u 1812 100V 2. 2u 1812 100V
DC OUTPU T
8 7 6 5 J5
08 05 D1 0 BAS21 S OT 23
SMAJ 58A
3 4
10 9
T P9
R2 3 10 k R1 8
BAT 46J
RT N
TP8
T P1 3
SEE BOM
Sync Input
R2 4 0
R2 5 0
Schematic of high-power board
BAT 46J
S OD32 3
U2
4 3 R2 8 1k 1 2
R2 6 10
R2 7 10k
Sharp PC3H7
C3 0 1u 16 V 060 3
ST D22NM20N
DPac k
Q3
AG N D C3 2 0. 1u
R2 9 1k
R3 2 21 k 1%
PM8800
HT SS O1 6
R3 6 NM R3 7 15k 1%
R3 5 0 805 NM 1%
R3 9 0 .47 o hm 1 206
R4 0 0 . 4 7 ohm 12 06 T P1 2
R4 2 0 C3 7 3
C3 5 22n
R4 3
U3
G ND A GND
4 .7 n
TS431
SO T 23- 5 5 C2 9
4
1 0k 1%
SEE BOM
R4 7 NM 1%
R4 4 1 2. 4k 1%
Figure 53. Schematic of the 3.3/5 Vout high power with synchronous rectification
NOTE for Resistors Where not indicated the body is 0603 and tolerance 5%
NOTE The AGND is a dedicated plane of signal ground that will be connected to the GND power ground plane close to pin 9 of PM8800
GND
2. 2n 18 12 2 KV
AN2783
AM01334v1
NOTE for Capacitors Where not indicated the body is 0603 and the voltage is 50V
AN2783
RJ45 Data and Power Jac Chassi s RJ45 Data Jac k 10 16 1 2 3 6 7 J2 Chassi s 8 H2019 / TL A-6T127LF 0 0805 R1 9 15 14 11 10 9 1 2 3 4 5 6 7 8
k
Appendix B
Chassis T3 1312 5 4
10
1 2 3 4 5 6 7 8
9
J1
Chassis
OUTPU T
INPUT
TP1 1 R3 0 + 3 D2 DF01S N M 2 SMAJ58 A Chassis 4 C1 0.1u 0805 100V D3 0 1206
1
+
3
4
D1 DF01S NM 2
TP2
STS10PF30L 3 2 1 SO8 Q1 STTH302 S SMC 8 7 6 5 D4
DC Power Jac k
TP3
AUX II
R10 4 330K 0805 R12 33K 0805 C41 0.1u 0805 100V
1 2 3
3
D5
J4
R11 15K 0805
1
BZX84C1 5 SOT23 R5 0
C27 0.1u
0
TP4 GND R13 15 1206 D7 1 3 10 9 4 1 D10 STPS1H100 A SMA GND R23 10k R18 10 R19 3.3k D15 C40 Green LED C26 100p N M R48 NM 88.7K 1% 0.1u U1 RT 1 RT AGND VFB COMP CS nPGD VCC GD GND R33 100 C33 470p R38 10k R39 R40 0.47 ohm 0.47 ohm 1206 1206 TP12 10 0805 1 R31 3 2 TP11 Q3 STD5N20L DPac k 14 15 SS AUXII 2 3 16 AGND AGND SS AUXII VIN RCLAS S AUXI_IRL DCC L TP10 0.1u R21 C34 GND C28 0.1u C25 1u 16V 0603 D14 SOD323 BAT46J 2 COILCRAFT POE13P SEE BOM -XXL 8 7 L1 1 3 D8 TP6 T2 2 3.3uH ME3220 -332ML C14 2.2u 1812 100V 2.2u 1812 100V D9 SMAJ58 A C15 TP7 SMC STTH302 S C11
DC Power Jac k
TP5
AUXI_IRL
1 2 3
470p 0805 TP1 4 4 STPS15L30CB DPac k C20 10u 6.3V 1206 C21 10u 6.3V 1206 1 OU T R17 1k C23 10u 6.3V 1206 C24 330u Green LED 6.3V 8x10.5 D11 C39 0.1u 1 2 J5
J3 C13 22u 100V 8x10.2 R49 0R
R15 15K
L2 2 0.33uH LPS4012 -331L
DC OUTPU T
0805
RTN
TP9
TP8
TP1 3
Sync Input
R24 0 U2 4 3 R28 1k AGND C32 0.1u 1 2 Sharp PC3H 7 C30 1u 16V 0603 R29 1k R32 21k 1% R26 10
R25 0
BAT46 J
SOD32 3
D16
Schematic of standard-power board
R27 10k
4 VI N CS 13 5 12 RCLAS S nPGD 6 11 AUXI_IRL VCC 7 DCCL Ex Pad GD 10 VS S 8 9 VS S GND 17 PM8800 HTSSO16
R35 0805 NM 1%
R37 15k 1%
R42 0 C37 3 GND AGND U3 TS431AILT SOT23 -5 C29 4 5 4.7n
C35 1n R43 10k 1%
Figure 54. Schematic of the 3.3/5 Vout standard power with diode rectification
SEE BOM
R47 NM 1%
R44 12.4k 1%
NOTE for Resistors Where not indicated the body is 0603 and tolerance 5 %
NOTE The AGND is a dedicated plane of si gnal ground that will be connected to th e GND power ground plane close to pin 9 of PM880 0
GND
2.2n 1812 2KV
Schematic of standard-power board
AM01335v1
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NOTE for Capacitors Where not in dicated the bod y is 0603 and the volta ge is 50 V
Revision history
AN2783
Revision history
Table 8.
Date 13-Jul-2008 04-Sep-2008
Document revision history
Revision 1 2 Initial release Modified: Figure 2 and 53 Changes
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AN2783
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