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What happens to the M24xxx I²C EEPROM if the I²C bus communication is stopped?
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Last Updated: 04/09/2006
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128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM
16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit serial I²C bus EEPROM
512 Kbit and 256 Kbit serial I²C bus EEPROM with three Chip Enable lines
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AN1471 Application note
What happens to the M24xxx I²C EEPROM if the I²C bus communication is stopped?
This Application note describes what can be attempted to set an M24xxx memory back to a known state if it has been suddenly stopped before completion of the current I²C instruction. The method presented here will work regardless of whether the device was stopped during an incoming or an outgoing Byte transfer. It is used to resynchronize the memory device whenever an undefined state has been detected on the I²C bus.
1
Resynchronizing the M24xxx's internal logic
If the Bus Master (the microcontroller or processor) or other components on the I²C bus have failed, with clock and data lines being improperly driven, the internal state of the M24xxx might reach an unknown state. The M24xxx internal logic must be resynchronized. The analysis of this situation can be structured under the following sub-headings:
The interrupted transmission was an Incoming data Byte The interrupted transmission was an Outgoing data Byte (during a READ cycle)
1.1
The interrupted transmission was an Incoming data Byte
The issue of a STOP condition is sufficient to abort the transmission. However, if the last transmitted instruction was a WRITE, the STOP condition is also able to start the internal Write cycle (if the STOP condition occurs after the 9th clock cycle of each data Byte). It is therefore risky to send a single STOP condition. It is recommended, instead, to issue a START condition first, followed by a STOP condition. The START condition aborts the transmission, and leaves the M24xxx waiting for a Device Select Code; the STOP condition then sets the M24xxx in stand-by mode.
Caution:
resynchronization does not modify the internal address counter. In order to define the internal address counter value, the next instruction must be Byte Random Read, Sequential Random Read or Write (the current Read or Sequential Read instruction does not modify the internal address counter).
August 2006
Rev 3
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Resynchronizing the M24xxx's internal logic
AN1471 - Application note
1.2
The interrupted transmission was an Outgoing data Byte (during a READ cycle)
A tricky configuration might be reached if, after loosing the Bus communication control, the M24xxx memory is stopped when outputting a "0" on SDA. In such a case, even if the Bus Master transmits a START condition, the M24xxx memory cannot decode it as the "SDA bus" is forced to "0". A good way to work around this state is to have the Bus Master sending several clock cycles until the M24xxx outputs a "1": once the "1" state has been output, a START condition transmitted by the Bus Master will be correctly decoded by the M24xxx memory. The same result can be reached using a blind sequence, with two possible outcomes: a) worst case: when it lost the Bus communication control, the M24xxx memory device was starting to clock out eight 0s (the data Byte was 00h), as shown in Figure 1. As the ninth clock pulse makes the M24xxx output a NoAck state ("SDAout from memory device" is "1"), the falling edge of "SDAout from Bus Master" correctly drives the "SDAbus" and this event is decoded as a START condition by the M24xxx memory. standard case: when it lost the Bus communication control, the M24xxx memory device was starting to clock out a Byte composed of "0s" and "1s"; the START condition is decoded sooner, that is with the first bit of data "SDAout from Memory Device" ="1". In such a case, the M24xxx memory decodes N successive START conditions (one START condition for each "SDAout from Memory Device" ="1") which restart the M24xxx memory N times, before decoding the final STOP condition (see Figure 1).
b)
Caution:
resynchronization does not modify the internal address counter. In order to define the internal address counter value, the next instruction must be Byte Random Read, Sequential Random Read or Write (the current Read or Sequential Read instruction does not modify the internal address counter). Nine attempts at a START condition and then a STOP condition
1 2 3 4 5 6 7 8 9
Figure 1.
SCL from Bus Master SDAout from Bus Master SDAout from Memory Device
START Condition
0
0
0
0
0
0
0
0
NoACK
SDA Bus
AI02406b
1. The STOP condition following the START condition sets the M24xxx in Standby mode. It can be also envisaged to have a new instruction directly after the START condition.
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STOP Condition
AN1471 - Application note
Revision history
It is recommended that the Bus Master sends to the M24xxx two overlapping trains of pulses on SCL and SDA as shown in Figure 1. This is not a standard sequence from the I²C protocol, but a specially designed sequence for resynchronizing the device to a known state. The main part of the sequence consists of nine rising edges of SCL, interleaved with nine attempts by the Bus Master to force a falling edge on SDA, while SCL is High. In this way, the Bus Master makes nine attempts at generating a START condition. It is certain to succeed on the ninth attempt, if not before. The START condition can be followed by a STOP condition that will put the device in its known standby state.
2
Revision history
Table 1.
Date 07-Nov-2001 27-Sep-2002 25-Aug-2004 28-Aug-2006
Document revision history
Version 1.0 1.1 2.0 3 First Issue Minor revision Indication of improvements that might be possible outside the worst cases Application note revised to limit the topic to the case where the I²C bus communication is lost. Changes
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AN1471 - Application note
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Document Number: 8335
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