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ST7 - 8-bit Microcontrollers
Understanding and minimising ADC conversion errors
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Last Updated: 28/02/2008
Pages: 42
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AN1636 APPLICATION NOTE
UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS
By Microcontroller Division Applications
1 INTRODUCTION
Th e purpose of this document is to explain the different ADC errors and the techniques that application developers can use to minimise them. The ADC (Analog to Digital Converter) is an important peripheral that connects the analog world to the digital world of microcontrollers. In this application note the ADC embedded in the ST7 microcontroller is used as an example, howe ver the same principles to apply to other ADCs. The accuracy of analog to digital conversion has an impact on overall system quality and efficiency. To be able to improve accuracy you need to understand the errors associated with the ADC and the parameters affecting them. The ADC itself, cannot ensure the accuracy of results, It depends on your overall system design. For this reason, you need to do some careful preparation before starting your developm ent. Lots of parameters affect the ADC accuracy depending on the application. Some of these factors are: PCB layout, voltage source, I/O switching and analog source impedance.
AN1636/0603
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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 WHAT IS AN ADC? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 ADC BLOCK DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 ANALOG INPUT PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 ANALOG MULTIPLEXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 SAMPLE AND HOLD CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 CONTROL BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 ANALOG SUPPLY AND REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 ADC TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 REFERENCE VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 RESOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 QUANTIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 MONOTONICITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 BIPOLAR AND UNIPOLAR ADC INPUT . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 HARDW ARE AVERAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 SAMPLING THEOREM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 SOURCES OF ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 POWER SUPPLY NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 POWER SUPPLY REGULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 ANALOG INPUT SIGNAL NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 EFFECT OF ANALOG SOURCE RESISTANCE . . . . . . . . . . . . . . . . . . . 19 4.5 EFFECT OF SOURCE CAPACITANCE . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 EFFECT OF INJECTION CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 I/O PIN CROSS-TALK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8 EMI-INDUCED NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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5 DIFFERENT TYPES OF A/D CONVERTER ERRORS . . . . . . . . . . . . . . . . . . 27 5.1 OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 DIFFERENTIAL LINEARITY ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 INTEGRAL LINEARITY ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 TOTAL UNADJUSTED ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 PCB LAYOUT RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 HOW POWER SAVING MODES AFFECT THE ADC . . . . . . . . . . . . . . . . . . . 39 8 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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1 WHAT IS AN ADC?
An analog to digital converter is a peripheral which converts analog signals in a defined range to the digital outputs. In the real world, signals are mostly available in analog form. To use a microcontroller in this type of system, an ADC is required, so that the signals can be converted to the digital values. Th e application software can then process the digital outputs and take decisions depending on the application or system requirements. The limitation imposed by the finite number of digital outputs decides how close the output is to the analog input. The more bits there are in the output, the closer the digital result will be to the analog signal. In other words, the resolution of the ADC is defined by the number of bits in the digital result (8 bits, 10 bits etc) and the input voltage range.
Successive Approximation Method Differen t techniques are available for converting analog signals to digital outputs. The Successive approximation method is the most popular technique. It is also known as Successive approximation Register (SAR) technique. This technique uses binary search method. It consists of a high speed comparator, DAC (digital to analog converter), and control logic. Refer to Figure 1. Figure 1. Successive Approximation Block Diagram VIN From Sample and Hold + Comparator VAREF Control Logic
D AC
n bit register
Digital Output
The SAR starts by forcing the MSB (Most Significant bit) high (for example in an 8 bit ADC it becomes 1000 0000), the DAC converts it to VAREF/2. The analog comparator compares the input voltage with VAREF/2. If the input voltage is greater than the voltage corresponding to the MSB, the bit is left set, otherwise it is reset.
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VAREF is the reference voltage used by ADC for conversions. The details are mentioned in Section 2.5 After this comparison is done, the next significant bit is set (=VAREF /4) and a comparison is done again with the input voltage. The procedure is followed till all the bit positions are compared. At the end of all the bit comparisons we get the corresponding digital output for the analog input. The successive approximation steps are shown in Table 1. As you can see, the digital output obtained from the ADC is B2h when the analog input is 3.5V. Table 1. 8-bit ADC successive approximation steps
S t ep s Digital code 1 2 3 4 5 6 7 8 1000 0000 1100 0000 1010 0000 1011 0000 1011 1000 1011 0100 1011 0010 1011 0011 Vin = 3.5v, VAREF= 5V DAC output 2.5v 3. 76v 3. 13v 3.45 3. 6 3.52 3.49 3. 509 C ompa rator output 1 0 1 1 0 0 1 0 digital output (for steps) 1000 0000 1000 0000 1010 0000 1011 0000 1011 0000 1011 0000 1011 0010 1011 0010 Final output = B2h
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2 ADC BLOCK DESCRIPTION
Figure 2. ADC Block diagram
fCPU
D IV 4 DIV 2 0 1
f ADC
( e)
VAREF
EO C S PEED AD ON 0 CH3 CH2 CH1 CH0
VSSA (f) 4
ADCCS R
AIN0
AIN1
A NA L O G MU X
AINx
Sample and Hold circuit ( c)
Successive Approximation Block (d)
( a)
(b)
ADCDRH
D9
D8
D7
D6
D5
D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
The ADC can be divided into the following blocks. a. Analog input pins b. Analog multiplexer c. Sample and Hold circuit d. Successive approximation block e. Control block f. Analog supply/ reference 2.1 ANALOG INPUT PINS Several analog input pins are available to connect different analog signals. These are internally multiplexed to use same sample and hold circuit and SAR logic.
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Figure 3. Electrical diagram of typical ADC application
VD D VT 0.6V RAIN V A IN CAIN VT 0.6V IL 1A AINx RADC 10-Bit A/D Conversion CADC
Configuring the analog pin Choo se any I/O port that has analog input capability (AIN alternate function) and configure it as floating input. You can do this by writing `0' in the DDR and OR register bits of the corresponding port. At reset, most of the ST7 IOs are configured by default as floating input. Th e pin should NOT be configured as floating input with pull-up. This configuration reduces the ADC accuracy. The reason being the potential divider formed between the pull-up resistance and RADC. Also some current flows from VDD to the analog source. This current is drawn fro m the VDD supply. Also there is a potential divider formed between VDD, R PU and R AIN, where RAIN is the series impedance of the voltage source. Figure 4. Analog input with pull-up NOT RECOMMENDED
RPU should not be enabled. Current from VDD VDD
\/\/\/\/\/\
R PU RA D C
\/\/\/\/\/
VIN
RAIN
\/\/\/\/\/\/
CA D C
VSSA (Analog Ground)
Configuring the analog input as floating input with pull-up ( instead of floating input ) will cause more current to be drawn from the V DD supply.There is also an affect on the accuracy of the ADC and the digital output converted by ADC may not be accurate.
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Analog Pin Input Impedance RADC and CADC (hold capacitor) define the input impedance of the analog pins. RADC is also ca lled as Rss (Resistance of sampling switch and internal trace/resistance). Please refer to the Sample and Hold circuit explanation in Section 2.3. If the hold capacitor is fully discharged, the minimum input impedance is R ADC. As the hold capa cito r starts to charge, the current flowing into the pin will reduce. If the hold capacitor is char ge d to a level equal to the external voltage there will be only minimal charging current flowing into the analog input. Figure 5. Analog input pin Impedance
\/\/\/\/\/\/ Input imp edance Zi = RADC + CADC
R ADC C ADC VSSA (Analog Ground)
The minimum input impedance of the analog pin is thus R ADC. In the datasheet the maximum value of RADC is specified instead of a typical value, so that the user can calculate the affect of external resistance on sampling. This is explained in Section 4.4. 2.2 ANALOG MULTIPLEXER The ADC can have several analog input pins. These pins are connected internally to the Ana lo g to Digital converter using the analog multiplexer. You can select each pin simply by writing in the appropriate control register. This allows a single Sample and Hold circuit and Analog to Digital Converter block to be used to convert several analog input sources. This allows you to switch the analog channels and convert them one by one through software control.
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Figure 6. Analog multiplexer AIN0 AIN1 AIN2 To Sample and Hold Circuit Analog Input Channels AIN7 Channel selection bits = 010 selects AIN2
CH[2:0] = 010 2.3 SAMPLE AND HOLD CIRCUIT
The sample and hold circuit samples the input signal and charges the internal hold capacitor CADC to the voltage equal to VIN through RADC. The analog pin is then disconnected and the volta ge across the capacitor is then converted to digital code using successive approximation. Figure 7. Sample and Hold circuit Electrically operated switch VIN From Analog Multiplexer \/\/\/\/\/\/ R ADC C ADC VSSA (Analog Ground) T h e sample and hold circuit consists of an electrically operated analog switch, internal charging resistance and hold capacitor. As soon as the ADC conversion starts, the electrically operated switch is closed, connecting the hold capacitor to the analog input through the internal ADC resistance RADC. This causes a charging current to flow into the analog input and the capacitor starts to charge. The time the switch remains closed is decided by the fADC. It is called sampling time. The sampling time is generally indicated in the datasheet as a multiple of fADC clock periods. Time period tAD = 1/fADC
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Figure 8. Sample and Hold timing and electrical diagram
Sampling Time
Hold Time Conversion time
tAD = 1/fADC Vc = Voltage developed across capacitor. Electrically operated Switch = Closed VIN \/\/\/\/\/\/ RADC C ADC VSSA Hold and Conversion Electrically operated Switch = Open VIN \/\/\/\ /\/\/ Leak age Current R ADC C ADC time Capacitor charged=VIN Sampling time Vc Vc = VI N
S a mp lin g
Charging + leakage current
SAR
VSSA Note : Please refer to product datasheet for Sample and Hold timing for ADC. SAR = Successive Approximation Register block. After the sampling time, the input capacitor has the same voltage as the input, the analog sw i tc h is then disconnected from the input and successive approximation conversion is started, to convert the voltage stored in the hold capacitor. This time is known as Hold time. It is also expressed in multiples of tAD (1/fADC). The total conversion time of the ADC is the addition of sampling time and hold time. The sample and hold circuit is also known as track and hold.
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2.4 CONTROL BLOCK This block consists of logic which controls the sample and hold circuit, starts the SAR and then generates the conversion of the `conversion complete' signal for the microcontroller. 2.5 ANALOG SUPPLY AND REFERENCE De pending on microcontroller and packaging, the analog supply pins are generally available on the package. VDDA - analog supply ( or, VAREF - reference voltage) VSSA- analog ground. If these pins are not available the VDDA (analog supply) is shorted to VDD and VSSA is shorted to VSS internally. Separate analog power supply pins are available to the user to improve the ADC performance. It is recommended to put the filtering capacitor between VDDA and VSSA so that power supply noise ( or ripples) on VDDA are filtered and do not affect the ADC accuracy. The VAREF pins are available instead of VDDA when the analog supply voltage can be different from the VDD. You may choose to keep VAREF shorted to VDD if a dual supply is to be avoided. Figure 9. Analog Supply block
1 to 10F
ST7 DIGITAL NOISE FILTERING
10pF (if needed) 0.1F
ST72XXX VSS
ST72xx
VDD /\/\/\/\/\/\
VD D
VDD
POWER SUPPLY SOURCE
10pF (if needed) 0.1F
EXTERNAL NOISE FILTERING
VDDA /\/\/\/\/\/\
VAREF
VSSA
VSSA
R E C O M ME N D E D
NO T RECOMMENDED
As these pins provide power supply to the analog block, you should not connect a resistor in series with VAREF. This will cause the voltage to drop due to the current flowing through the resistor and hence will affect the accuracy of the ADC. Do not leave the V DDA/VAREF, VSS pins unconnected. If your application does not use the AD C, you must connect these pins as follows: VDDA must be connected to V DD, and VSSA
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must be connected to the VSS of the microcontroller. VSSA cannot have any voltage other than VSS. Make sure that V AREF is not greater than VDD. There is a protection diode from VAREF to VDD. Similarly VSSA should not be less than or greater than VSS. There are protection diodes connected back-to-back between V SSA and V SS. Figure 10. Multisupply Configuration
VDD
VAREF
VAREF
VSS
BACK TO BACK DIODE BETWEEN GROUNDS
VSSA
VSSA
3 ADC TERMINOLOGY
There are some terms associated with the ADC which we should understand before we move further. 3.1 REFERENCE VOLTAGE The ADC requires a reference voltage to which the analog input is compared to produce the digital output. The digital output is the ratio of the analog input with respect to this reference volta ge. digital value =((Analog input voltage)/(reference voltage high- reference voltage low)) * (2 n-1) where n = number of bits of ADC digital output. The reference voltage is the maximum input voltage that can be converted by the ADC. VAREF is the reference voltage for the ADC. If VAREF is not available VDDA is used as reference. For example: for 10-bit ADC, VIN=1V, VAREF=5V, Digital value = (1V/5V ) *1023 = 204d = 0CCh 3.2 RESOLUTION The ADC resolution is defined as the smallest incremental voltage that can be recognized and hence it causes a change in the digital output. It is usually expressed as the number of bits output by the ADC.
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Hence an ADC which converts the analog signal to a 10-bit digital value, has a resolution of 10 bits. The smallest incremental voltage that can be recognized is expressed in terms of LSB. 1LSB = (VAREF - VSSA)/2n where LSB = Least significant bit. n = number of bits output by the ADC. VAREF = Reference voltage VSSA = Analog ground An ADC which has `n' bit digital output, provides 2n digital values. It includes both 0 and 2 n-1. With a 5V reference voltage, the resolution is 5 (volts) /210 = 5 (volts)/1024 = 4.88 mV. Th is means that for a change in 4.88mV analog input the ADC converted digital value will change by 1LSB. In reality there are 2n-1 steps. So the actual resolution is 1LSB = (VAREF - VSSA)/(2n -1). As in practice there is very little difference between the two calculated values because `n' is quite a large number, both definitions are used. Figure 11. Resolution representation Digital O utput 3FFh
N +1 N Resolution 00h n (n+1) V AREF VAREF 3.3 QUANTIZATION In theory, the continuous analog signal can be broken into an infinite number of digital steps, but the quantization of an analog signal by the ADC can be done only in the finite number of steps which can be produced by the ADC. Anal og VAREFInput
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The quantization error is the error introduced because of the process of quantization. Ideally any analog input voltage can be maximum of 1/2 LSB away from its nearest digital code. So the quantization error is 0.5LSB for the ADC.
Figure 12. Quantization of analog signal Step width 1LSB Digital outpu t (Decimal steps) 1 Center of step = 0 quantization error VSSA 1 2 VI N Ideal transfer curve
Quantization 0.5LSB Error 0 - 0.5LSB Vi n
3.4 MONOTONICITY Mon oto nicity is defined as a property of the ADC transfer function, which ensures that converted digital values will never decrease if the analog input does not decrease and conversion results will never increase if the analog input does not increase. This property is inherent to the desig n of the ADC, subject to the accuracy specified in the datasheet in each case.
3.5 BIPOLAR AND UNIPOLAR ADC INPUT ADCs that can accept both positive and negative analog signals are known as bipolar.
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ADCs that can accept only positive input voltage are known as unipolar. ADCs embedded in microcon trollers are unipolar, as the input cannot decrease below the analog ground. ST7 microcontrollers have unipolar input ADCs and have an input range from 0V to V AREF. In an 8-bit ADC, for example, A unipolar ADC with an input range of 0V to 5V will output the digital code 00h for 0V and FFh for 5V. A bipolar ADC with an input range of -5V to +5V will output the digital code 00h for -5V, 80h for 0V and FFh for +5V. Figure 13. Bipolar and Unipolar ADC transfer curves Digital output FFh Digital Output FFh
80h Analog Input 00h Bipolar ADC transfer curve 00h Unipolar ADC transfer curve
Analog Input
3.6 HARDWARE AVERAGING To improve ADC accuracy, you can perform a number of ADC conversions and use the aver a ge of these conversions to obtain more accurate digital output. In hardware averaging ADCs, this technique is embedded in the hardware and the averaging is done by the hardware itself. The final digital output received from ADC is actually the average of the conversions. Th is hardware averaging technique is implemented in some ST7 microcontrollers. The conversion time is thus increased as several conversions are performed. 3.7 SAMPLING THEOREM The sampling theorem states that to convert the analog signal with frequency `f', the ADC sampling frequency must be at least twice the analog signal frequency. So the sampling frequency must be at least `2*f'.
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Sampling the signal at twice the analog signal frequency will not result in a loss of information. If sampling frequency is less, then the information will be lost. This is a standard theorem that applies to ADCs in general. For example: an ADC with a conversion time of 10s can be used to sample an analog signal with a time period of 20s, i.e. 50kHz. (1/20s).
4 SOURCES OF ERROR
4.1 POWER SUPPLY NOISE The analog power supply is used as the reference voltage for conversion. As the ADC output is the ratio between the analog signal voltage and the supply voltage, any noise on the analog reference will cause a change in the converted digital value. For example: with a 5V supply (analog reference) and 1V signal, the converted result is (1/5)*1023 = 204d = CCh But with 40mV ripple peak-to-peak in the power supply, the converted value is (1/5.04)*1023 = 202d = CAh (when V AREF was at its peak). The SMPS (Switch mode power supply) normally has internal fast switching power transistors. This introduces high frequency noise in the output. The switching noise is in the range of 151M h z. You can filter this noise by putting low value capacitors (10pf - 22pf) on the power supply rail. Low value capacitors have low reactance whereas high value capacitors have high reactance. Linear regulators have better output in terms of noise. The mains must be stepped down, rectified and filtered and then fed to linear regulators. It is highly recommended to have the filter capacitors at the rectifier output. Please refer to the datasheet of the linear regulator in each case . Generally 0.01uF is recommended. If you are using a switching power supply, it is recommended to have a linear regulator to supply the analog section. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1uF and optionally, if needed 10pF capacitors as close as possible to the ST7 power supply pins and a 1 to 10uF capacitor close to the power source.
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Figure 14. Power supply filtering
1 to 10F
ST7 DIGITAL NOISE FILTERING
10pF (if needed) 0.1F
ST72XXX VSS
VDD
VDD
POWER SUPPLY SOURCE
10pF (if needed) 0.1F
EXTERNAL NOISE FILTERING
VDD A
VSSA
The capacitors allow the AC signals to pass through them. The small value capacitors filter high frequency noise and the high value capacitors filter low frequency noise. Ceramic capacitors are generally available in small values (1pf to 0.1 f) and small voltages 16V to 50V. It is recommended to place the ceramic capacitors close to the main supply pins (V DD & VSS and analog supply pins (VDDA & VSSA). These filter the noise induced in the PCB tracks. Small capacitors can react fast to current surges and discharge quickly for fast current requirements. Tantalum capacitors can also be used along with ceramic capacitors. High value capacitors (10f to 100f) which are generally electrolytic, you can use them to filter low frequency noise. It is recommended to put them near the power source. You can also filter high frequency noise using a ferrite inductance in series with the power supply. Ferrites cause low DC loss (negligible) unless the current is high. This is because the series resistance of the wire is very low. But for high frequency, the impedance offered is high. In most ST7 microcontrollers the VDD & VSS pins are placed close to each other. Similarly VAREF & V SSA pins are placed closed to each other. This allows you to put a capacitor very close to the microcontroller with very short leads. For multiple VDD & VSS pins, use separate decoupling capacitors. 4.2 POWER SUPPLY REGULATION The power supply should have good line and load regulation. As the ADC uses VAREF as the analog reference and the digital value is the ratio of analog input signal and VAREF. So VAREF must remain stable at different loads. Whe never the load is increased by switching-on a part of the circuit, the increase in current must not cause the voltage to decrease. If the voltage remains stable over a wide range of current the power supply has good load regulation.
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If the voltage decreases, the decrease in VAREF changes the ratio of the analog signal to VAREF. dig ital output = (VIN/VAREF) * (2n-1) A change in VAREF will make a change in the digital output. For example: for the L7805 voltage regulator, (Please refer to the L7805 datasheet for details). Line regulation is 20mV typical for I(load) between 1mA to 100mA. Similarly, Line regulation is 18mV typical for rectified voltage between 7V to 20V.
4.3 ANALOG INPUT SIGNAL NOISE The analog signal to be converted may have some noise superimposed on it. There may be a high frequency noise signal. It is recommended to connect a 10nf capacitor to the analog input signa l. You can also add a low pass filter but this will affect FAIN, so you should use this only if the input signal frequency is low. FAIN is the frequency of the analog input signal. For other details refer to Section 4.5.
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Figure 15. Noise in analog input signal
10mv Vp-p ~2 LSB
Expected /ideal Signal at Analog input
Actual Signal at Analog input
VAIN 10nf
AI Nx
AD C
Recommen ded configuration with slow input signal 4.4 EFFECT OF ANALOG SOURCE RESISTANCE The impedance of the analog signal source or series resistance (RAIN) between source and pin will cause a voltage drop across it because of current flowing into the pin. The RADC and CADC form an RC network. The charging of the capacitor is controlled by RADC. W h en there is R AIN in series, the effective value of charging of C ADC will be governed by RADC+RAIN, So the charging time constant will become (RADC+R AIN)*CADC. The sampling time for ADC should be greater than 10 times the RC time constant. Please refer to the explanation in Section 4.5. With external input resistance, the sampling time required by the ADC will also increase. The ADC has a fixed sampling time depending on fADC. With the addition of source resistance, the time required to fully charge the hold capacitor will increase. If the sampling time is less than the time required to fully charge the CADC through RADC+RAIN, the digital value converted by the ADC will be less than the actual value. Sampling time > 10*(RADC+RAIN)*CADC
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Figure 16. Effect of source impedance on internal sampling VAIN RAIN \/\/\/\/\/\/ AIN x \/\/\/\/\/\/ R ADC C ADC Vc
VSSA (Analog Ground) Vc = Voltage across hold capacitor C ADC
Vc
Vc
VIN
ti m e Correct time to charge CADC to VIN Time constant = 10*RADC*CADC
time Increased time to charge CADC to VIN Time constant = 10*(RAIN+RADC)*CADC
AINx = analog input pin CADC = the hold capacitor of the ADC Refer to datasheet for values for R ADC and CADC
4.5 EFFECT OF SOURCE CAPACITANCE You have to take the capacitance and resistance at the source into account when converting analog signals. The source resistance and capacitance form an RC network and the ADC conversion results may not be accurate unless the external capacitor is fully charged to the level of the input voltage. The external capacitance at source is denoted by CAIN.
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Figure 17. ADC input with RAIN, CAIN
ST72x Cp = Parasitic capacitance CAIN = Source capacitance
RAIN V A IN CAIN AINx
Cp
The external capacitance will not allow the voltage of the analog input to be exactly the same as VIN if it is not fully charged by the analog source. If the analog input signal varies, then the analog signal frequency (F AIN) should be such that the time period of this analog signal is at least 10 * RAIN * CAIN. Figure 18. Recommended RAIN, CAIN values
1000
Cain 10 nF
100
Cain 22 nF Cain 47 nF
Max. R AIN (Kohm)
10
1
0.1 0.01 0.1 1 10
f AI N(K Hz )
TAIN = time period of analog signal = 1/FAIN TAIN >= 10 * RAIN * CAIN. FAIN = 1/ TAIN <= 1/ (10 * RAIN * CAIN ) For example: For RAIN = 10K, CAIN = 10nf TAIN = 10 RAIN * CAIN = 10 * 10K* 10n = 1000s = 1ms FAIN = 1/TAIN = 1/1ms = 1KHz maximum.
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Figure 19. Effect of external R and C.
Input Signal
Signal at analog input (=across Cain)
External capacitor not charged to VIN
The voltage across the capacitor follows the following equation: Vc = VIN (1 - e-t/RC) Vc = Voltage across capacitor VIN = Voltage from voltage source e = Exponential constant = 2.71 (approx.) t= Time, after which voltage across the capacitor is to be calculated. R = Resistance used to charge the capacitor C= Capacitance value. R*C = time constant of RC network Table 2. Voltage across the capacitor
t/RC 1 2 3 4 8 10 Vc/VIN (1- (2.71)-1) (1- (2.71)-2) (1- (2.71)-3) (1- (2.71)-4) (1- (2.71)-8) (1- (2.71)-10) Vc 0.63*VIN 0.86*VIN 0.94*VIN 0.98*VIN 0.9996*VIN 0.9999Vin
It should be noted that when the ratio of t/RC increases, the voltage developed across the capacitor becomes nearly equal to V IN. The conversion result will be correct only when the capacitor is fully charged. Therefore, t >= 10*R*C.
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The parasitic capacitance formed at the analog input because of track paths etc. appears in parallel with external capacitance. So it must be added to C AIN. However when the parasitic capacitance value is much less than CAIN, it can be ignored. When CAIN is small (for example CAIN < 100*CADC ), it may not be able to hold the VIN voltage effe ctive ly. So when ADC conversion is started, CADC will appear across the CAIN through RADC causing C AIN to effectively discharge. So we need to consider the sampling time required with external resistance and capacitance. Figure 20. RAIN Vs fADC
For example: With RAIN=10K, CAIN (or Cparasitic) = 10pf, CADC=6pf Time for charging external capacitor = RAIN*CAIN= 10k* 10pf = 100ns 10*RAIN*CAIN = 1us. Time for charging hold capacitor CADC = (RAIN+RADC)* CADC RC = 12K*6pf =72ns 10RC = 720ns = 0.72us Total time = 1us + 0.72s = 1.72s. (approx.) So, for ADCs with fADC=2Mhz, sampling time = 4*tAD= 2s. With total time of 1.72s obtained with RAIN and Cparasitic, the sampling time of 2s is already at its upper limit. If the resistance is higher, fADC must be decreased to increase the sampling time. So fADC less than 2MHz can be used. It can be noted that for fADC = 1MHz, RADC can be up to 20 kOhm.
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At lower fADC, we can start the ADC conversion as the sampling time is long enough to charge both CADC and CAIN (or Cparasitic). 4.6 EFFECT OF INJECTION CURRENT ST microcontrollers have robust tolerance of additional leakage current introduced on analog inpu t signals as an effect of negative injection current. Negative injection current on any analog pin (or closely placed digital input pin) may introduce leakage current into the ADC input. The worst case is the adjacent analog channel. Negative injection current is introduced when VIN
For example: For an injection of 0.8mA on the analog input pin ST specifies a maximum leakage current of 1.6A (please refer to the respective product datasheet) as Voltage = Current * Resistance. The voltage drop due to this leakage current across R AIN is: V (RAIN)= RAIN * I Leak If source series resistance RAIN is 10K, the leakage current will introduce 1.6A*10kohm = 16mV for 10-bit ADC, 1LSB = 5V/1023 = 4.8mV. A drop of 16mV will correspond to approximately a drop of 4LSB. This means that all the digital converted values will contain an error of 4LSB. This means that after the ADC converts the input signal, the digital output will always be 4LSB less than it should be.
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Figure 21. Effect of injection current Vain
RAIN \/\/\/\/ \/\/
AIN 0 Leak age current
AIN1
A DC
VIN < VSS injection current VSSA Microcontroller
This demonstrates that the source impedance should be as small as possible to obtain maximum accuracy. With no negative injection current, no loss of accuracy is expected. Positive injection current is introduced when VIN > VDD. Therefore current flows into the I/O pin. Positive injection current within the limit does not cause any loss of accuracy.
Minimizing Injection current Check the application to verify if any digital or analog input voltages can be less than VSS or VSSA. In this case negative injection current will flow from the pins. Negative injection current will have greater affect on the accuracy, when a digital input is close to the analog input being converted. It is recommended to connect a Schottky diode from VSSA to the IO which can have the negative injection current.
4.7 I/O PIN CROSS-TALK Switching the I/Os may induce some noise in the analog input of the microcontroller. This is beca use of capacitive coupling between the I/Os. The cross-talk may be introduced by PCB tracks running close to each other or crossing over each other. Within the microcontroller there can be non-negligible effect on I/Os because of switching etc. Internally switching digital signals and I/Os introduces high frequency noise. If high sink I/Os are switched, this may induce some voltage dips in the power supply because of the current surges. A digital track crossing over an analog input track on the PCB may affect the analog signal.
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Figure 22. Cross-talk between I/Os
Analog-in
Analog-in
Analo g-in
Digital I/O Digital and analog signal passing close to each other
Digital I/O Digital and analog signal tracks crossing e ach other on different side of the PCB
Digital I/O Recommended Grounding between signals
Shielding the analog signal by placing ground tracks across it helps reduce noise produced by cross talk etc.
4.8 EMI-INDUCED NOISE Electromagnetic emissions from neighboring circuits may introduce high frequency noise into an analog signal because the PCB tracks may act like an antenna. You can reduce the emission noise by proper shielding and layout techniques. The possible so ur ce s of emissions must be physically separated from the receptors. You can separate them electrically by proper grounding and shielding. You can minimize the reception noise by using filtering techniques so that high frequency noise is filtered. Figure 23. EMI sources I/O coupled Noise ADC
Electromagnetic Noise Analog Source
Induce d noise from PCB tracks
Inter nal Noise
Microcontrolle r
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Shie lding Placing ground tracks alongside sensitive analog signals provides shielding on the PCB. The other side of the two-layer PCB should also have a ground plane. This prevents interference and I/O cross-talk affecting the signal. Signals coming from distant locations (like sensors etc) should be connected to the PCB using shie ld e d cable. Care should be taken to minimize the length of the paths of these types of signa l on the PCB. The shield should not be used to carry the ground reference from the sensor or analog source to the microcontroller. A separate wire should be used as ground. The shield should be grounded at only one place near the receiver such as the analog ground of the microcontroller. Grou nding the shield at both the ends (source and receiver) may cause ground loops to be formed and making the current flow from the shield. Figure 24. Shielding Not Recommended Sensor AD C Sensor AD C Recommended
Gr ound Currents Do not ground the shield at both ends Grounding the shield at the receiver end only
If the current is flowing through the shield, it will act like an antenna and the purpose of shielding will be lost. The shielding concept also applies to grounding the chassis of the application if it is metallic. This also helps to remove EMI and EMC interference. In this case the mains `Earth Ground' is used to shield the chassis. Similarly DC ground can also be used for shielding in case `Earth Ground' is not available.
5 DIFFERENT TYPES OF A/D CONVERTER ERRORS
Differen t error types are specified for A/D Converters. These errors are normally expressed as multiples of LSB for easy reference. The resolution in terms of voltage depends on the referen ce voltage. You can calculate the error in terms of voltage by multiplying the (number of LSB) with (voltage corresponding to 1LSB ).
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5.1 OFFSET ERROR This is defined as the deviation between the first actual transition and the first ideal transition. The first transition is when the digital output of ADC changes from 0 to 1. In an ideal case we should get a digital output of 1, when the analog input is between 0.5 LSB to 1.5LSB. The first transitio n in an ideal case will be at 0.5 LSB. Offset error is represented as E O. Example 1: In a 10-bit ADC, ideally 2.44mV (0.5 LSB = 0.5 * 4.88mV) input should generate a corresponding digital output of 1. But in practice the ADC may still show the reading as 0. If we get a digital output of 1 from an analog input of 10mV, then: Offse t error = Actual transition - Ideal transition EO = 10mV - 2.44mV = 7.56 mV EO = 7.56mV / 4.88 mV = 1.54 LSB When an analog input voltage of greater than 0.5LSB generates the first transition, then the offset error will be positive. Figure 25. Positive offset error representation
Digital outpu t (Decimal steps)
EO EO = Offset error (positive) Ideal transfer curve Actual transfer curve
1
0.5LS B
VI N
When the analog input voltage V IN = VSSA and the ADC generates a non-zero digital output then the offset error will be negative. This will mean that theoretically (or by Extrapolation) a neg ative voltage will generate the first transition. As specified in the datasheet, any voltage less than VSSA will cause the digital output to be 0.
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Figure 26. Negative offset error representation
Digital O utput EO EO = Offset error (negative) Ideal transfer curve
1
Actual transfer curve VI N
0.5LS B
5.2 GAIN ERROR Gain Error is defined as the deviation between the last actual transition and the last ideal transition. Gain error is represented as EG. Th e last actual transition means the transition from 3FE to 3FF for a 10-bit ADC. In an ideal case we should get a transition from 3FE to 3FF from a 10-bit ADC, when the analog input is equal to V AREF-0.5LSB. So for VAREF= 5V, last ideal transition shall be at 4997.12 mV. If ADC provides the 3FFh reading for VIN < VAREF-0.5 LSB, then we have a negative gain error.
Example For a 10-bit ADC and VAREF =5v If VIN = 4990 mV generates transition from 3FE to 3FF then, Gain error E G = Last actual transition - ideal transition EG = 4990mV - 4997.12 mV EG = - 7.12 mV EG = (-7.12mV / 4.88mV) LSB = -1.45 LSB
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Figure 27. Negative Gain error representation EG 1023 Digital outpu t (Decimal steps) EG = Gain error (negative) Ideal transfer curve Actual transfer curve
1022.5 LS B
VI N
If we do not get full scale reading ( 3FF for a 10-bit ADC ) for VIN equal to VAREF the gain error will be positive. This means theoretically (or by extrapolation), a voltage greater than VAREF will cause the last transitio n. Figure 28. Positive Gain error representation EG 1023 Digital outpu t (Decimal steps) EG = Gain error (positive) Ideal transfer curve Actual transfer curve
1022.5 LSB
VI N
5.3 DIFFERENTIAL LINEARITY ERROR Differe ntial Linearity Error (DLE) is defined as the maximum deviation between actual steps and the ideal steps. Here `ideal' is not for the ideal transfer curve but for the resolution of the ADC. DLE is represented as ED.
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DLE = Actual step width - 1LSB Ideally analog input voltage change of 1LSB should cause a change in the digital code. If an analog input voltage greater than 1LSB is required for a change in digital code, then the ADC has the differential linearity error. DLE thus corresponds to additional maximum voltage that is required to change one digital code to the next digital code. DLE is also known as DNL, Differential Non-Linearity error.
Example: For a range of analog input we should get the same digital output. Ideally the step width should be 1LSB. Suppose we get same digital output for a range of analog input voltage 1V to 1.010V then the step width will be 1.010V-1V = 10mV. DLE is thus the voltage difference between the hig he r (1.010V) and lower analog voltage (1V) subtracted by the voltage corresponding to 1LSB. Figure 29. Differential Error representation ED (Negative) Positive ED Digital outpu t (Decimal steps) Ideal Transfer curve 1L SB id eal
1LSB Actual transfer curve ED = Differential linearity error
1 VSSA
VI N
Note: In this example the actual curve is shown to have an offset error from ideal curve.
With a 10-bit ADC and V AREF = 5V, an analog input of 1V can provide results varying from CB h to CDh. Similarly for 1.010V, i.e. 206d = CEh, the results may vary from CDh to CFh. So, total voltage range corresponding to the step CDh is 1.010 V - 1V = 10mV ED= 10mV - 4.88 mV ED= 5.12 mV
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ED= (5.12mV/4.88mV) LSB ED= 1.04 LSB Here we assume that any voltage greater than 1.010 V will not result in the digital code equal to CDh. When the step width is less than 1LSB, DLE will be negative. 5.4 INTEGRAL LINEARITY ERROR Integral Linearity Error is maximum deviation between any actual transition and the endpoint correlation line. ILE is represented as E L. The endpoint correlation line can be defined as the line on the A/D transfer curve that connects the first actual transition and last actual transition. ILE is the deviation from this line for each transition. The endpoint correlation line thus corresponds to the actual transfer curve and has no relation to the ideal transfer curve. ILE is also known as INL, Integral Non linearity Error. ILE is the integral of DLE over the full range. Figure 30. Integral error representation
1023 Digital outpu t (Decimal steps) Actual transfer curve EL
Endpoint correlation Line EL = Integral linearity error
1 VSSA Example:
VI N
If we get the first transition from 0 to 1 at 10mV ( offset error ) and we get the last transition (3FE to 3FF) at 4.990V (gain error) then the line on transfer curve connecting the actual digital code 1 and the actual digital code 3FF will be the endpoint correlation line.
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5.5 TOTAL UNADJUSTED ERROR TUE is defined as the maximum deviation between the actual and the ideal transfer curves. It is a parameter which specifies the total errors that can occur causing maximum deviation between the ideal digital output and actual digital output. It is the maximum deviation recorded between ideal expected value and actual value obtained from the ADC for any input voltage. TUE is represented as E T. TUE is not the sum of EO, EG, EL, ED. The offset error affects the digital result at lower voltages whereas the gain error affects the digital output for higher voltages.
Example: With a 10-bit ADC and VAREF=5V and 1V input, the ideal result is CCh. But if on conversion we get the result CEh, this deviation may be because of offset, DLE and INL errors occurring simultaneously. TUE = absolute (actual value - ideal case value). = CEh - CCh = 2h
Figure 31. Total unadjusted error
Et Digital outpu t (Decimal steps) Et = Total Unadjusted error Ideal transfer curve Actual transfer curve
1 VSSA
VI N
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Using error parameters 1. The TUE is NOT the sum of all the errors EO, EG, EL, ED. It is the maximum error which can occur between ideal and expected digital values. It can be the effect of either a single error or two errors occuring simultaneously. 2. As ILE is the integral of DLE, it can be considered as indicative of maximum error. Do not add both DLE and ILE together to calculate the maximum error which can occur at any digital step. 3. Integral Linearity Error is the maximum deviation between any actual transition and the end point correlation line. So it represents the linearity of the ADC. 4. ILE and DLE are dependent on the ADC design. It is difficult to calibrate them. 5. The ILE and DLE can be minimized by doing multiple conversions and then averaging. 6. Offset and Gain errors can be easily cancelled / compensated using software techniques. 7. The maximum values for errors specified in datasheet are the worst error values measured in the laboratory test environment for full voltage range. 8. As already mentioned, all the ADCs provide the digital converted output in ratio with the reference voltage. To convert analog voltage accurately, the ADC needs to have an accurate VAREF otherwise the digital output received may not be the correct value. Example: In the widely used 7805 voltage regulator, the datasheet (L78M05C) specifies Vo min.= 4.8V and Vomax = 5.2v. This variation is 0.2V from required 5V. Hence a variation of 200mv. With an analog input of 1V and with VAREF=5V, the expected digital output should be (1/5)*1023 = 204d = CCh But if V AREF = 4.8v, the digital output = (1/4.8)*1023 = D5h So the power supply variation has caused a change of D5-CC = 9. In this case to measure the true input voltage, all the relevant parameters must be verified and crosschecked. For example, if a precision voltage regulator such as the L78M05AB is used, it provides Io=350mA and Vomin=4.9V, Vo max = 5.1V.
6 PCB LAYOUT RECOMMENDATIONS
For best ADC conversion accuracy, you should follow these PCB layout guidelines. 1. Separate the analog and digital layouts
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It is recommended to separate the analog and digital circuitry on the PCB. They should be placed in different parts of the PCB. This also avoids tracks crossing each other. The tracks carrying digital signals may introduce high frequency noise in analog signals because of coupling . The digital signals produce high frequency noise because of fast switching. Co upling of the capacitive nature is formed because of the metal connections (tracks) separated by the dielectric provided by the PCB base (glass, ceramic or plastic). It is recommended to use different planes for analog and digital ground. If there is a lot of analog circuitry then an analog ground plane is recommended. Analog ground must be placed below the analog circuitry.
Figure 32. Separating the analog and digital layouts Power Supply
Dig ital Circu itry Digital Gr ound (Noisy and noise Generating)
Micro Controller
Analog circuitry
(affected by noise) Analog Gr ound
2. Separate power supplies for analog and digital circuits It is desirable to have separate analog and digital power supplies in cases where there is a lot of analog and digital circuits external to the microcontroller. Depending on the microcontroller packa ge, different analog and digital power supply and ground pins are available. Internally VAREF and VDD pins are not connected except for protection through Schottky diodes. These pins can be powered from separate power supplies. In low pin-count packages, separate analog and digital supply and ground pins may not be available. In this case they are internally shorted. So VDDA and VDD are internally connected in packages which have fewer pins. As mentioned earlier, if you use a switching type power supply for the digital circuitry, you should use a separate linear supply for the analog circuit. Also, if you expect a lot of noise on the DC power supply due to I/O switching etc, a separate supply for the analog section is preferable.
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Important: Separate Analog and Digital supplies are recommended only if the microcontroller has VAREF pins for the ADC reference voltage (instead of VDDA). If the microcontroller does not have VAREF pins, then the difference between VDDA and VDD should not be more than the difference specified in the datasheet (check the Absolute maximum ratings). Generally the difference between VDDA and VDD is specified as 50mV, hence separate supplies are not recomm ended. Figure 33. Separating the analog and digital supplies Linear Regulator
SMPS
AC mains
VAREF VSSA Anal og Circuit VSS
VDD
Microcontroller
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3. Connect analog and digital power supplies in a star network It is recommended to connect the analog and digital grounds in star network. This means that you must connect the analog and digital grounds only at one point. This avoids noise being intr o du ce d in the analog power supply section, because of digital signal switching and also avoid s current surges affecting the analog section.
Figure 34. Star connection for analog and digital supplies
Digital Circuit Analog Circuit
Analog Ground
Analog Current Power Supply
Digital Current
Digital Gr ound
4. Using separate PCB layers for supply and ground Two-Lay er PCBs For two layer PCBs it is recommended to provide a maximum area for the ground. The power supply (VDD, VDDA) should run through thick tracks. The ground area between two layers can be shorted together via multiple connections in the overlap region if they are same ground signals. The unused area of the PCB can be filled with the ground area. The other convention is to fill the unused area of PCB on one layer with positive supply (V DD) and unused area on other plane for Ground. The advantage is reduced inductance for power and ground signals. Maximum ground area on PCB provides a good shielding effect and reduces the electromagnetic induction susceptibility of the circuit.
Multilayer PCBs Whe re ve r possible, try to use multilayered PCBs and use separate layers on the PCB for po w er and ground. The VDD, VSS pins of the various ICs can be directly connected to the
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po w e r planes thus reducing the tracks needed to connect the supply and ground. Longer tracks will have a high inductive effect. The analog ground can be connected at one point to this ground plane, this should be near to the power supply. A full ground plane provides a good shielding effect and reduces the Electromagnetic induction susceptibility of the circuit. Figure 35. Multlayer PCB configurations
1. Top layer and bottom layer for SMD components 2. Second layer as power plane 3. Third layer ground layer
1. Top layer and bottom layer 1. Top layer and bottom layer for components and ground plane for SMD components ( Analog and digital ) 2. Second layer as digital 2. Second and third layer for tracks ground plane. 3. Third layer as analog ground Digital and analog ground connected at one point near power supply
There will be tracks passing vertically through the ground and supply planes. S MD: Surface mounted devices
The disadvantage of multilayer PCBs is the higher cost of manufacturing and the fact that they are more difficult to debug.
Single-layer PCBs Single-layer PCBs are used to save cost. They can be used only in simple applications when th e number of connections is very limited. It is recommended to fill the unused area with ground. Jumpers can be used to connect different parts of the PCB.
5. Component placement and routing Place the components and route the signal traces on the PCB to shield the analog inputs. Analog signal paths should run over the analog ground plane. Components like resistors and capacitors must be placed with their leads very short. Surface mounted devices (SMD), resistors and capacitors can be used. SMD capacitors can be placed close to the microcontroller for decoupling. The tracks for the power should be wide, as the series resistance of these tracks will cause the volta ge drop if the tracks are narrow. Narrow power tracks will have non-negligible finite resistance. High load current will cause some voltage drop across these tracks.
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Qua rtz crystals must be surrounded by ground tracks/plane. The other side of the two layer PCB below the crystal should preferably be covered by the ground plane. Most crystals have a metallic body that should be grounded. The crystal should be placed close to the microcontroller. Surface mounted crystals are available and can be used. 6. Software considerations Do not toggle digital outputs on the same I/O port as the A/D input being converted. This will introduce switching noise into the analog inputs. Toggling high sink I/Os may introduce high frequency noise in the power supply, this may affect the conversion results.
7 HOW POWER SAVING MODES AFFECT THE ADC
Wait mode ADC can be used when the microcontroller is in Wait mode. You can take advantage of the reduced internal noise in the microcontroller to improve ADC conversion results.
Halt mode Ente ring Halt mode will disable the ADC, irrespective of whether the ADON bit is set or not. This is because executing the HALT instruction shuts down the ADC. Exiting from Halt mode requires some stabilization time before ADC conversion should be started. This conversion time is very small. Please refer to the datasheets. Table 3. Summary Table
ST7 Modes Run Slow Wait Slow -W ait Oscillator On On On On Oscillator/C PU/Peripheral Status M CCS RM CCS RCP U OIE Bit SMS Bit On On Off Off X X X X Reset S et R es et S et Effect on ADC Use the ADC as mentioned in dat as heet . Take care that fADC does not fall below fADC min. If ADC has exit-from Wait capability, this mode is recommended. If ADC has exit-from Wait capability, this mode is recommended.
AD C On On On On
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ST7 Modes
Oscillator/C PU/Peripheral Status OscilM CCS RM CCS RCP U lator OIE Bit SMS Bit On Off S et X
AD C Of f
Effect on ADC Exit from Halt mode requires stabilization time before conversion starts. Exit from Halt mode requires stabilization time before conversion starts.
Active-Halt
Halt
Of f
Off
Reset
X
Of f
Note : Reset=0, Set=1 Rules and Recommendations for using the ADC in Power Saving Mode Different power saving modes for ST7 can be selected depending on power saving requiremen ts of the application, the following rules and recommendations should be applied when using the ADC. 1. When switching to Slow mode from Run mode care should be taken that the fADC should not fall below the fADC minimum specified. Otherwise the conversion results are not guaranteed. Sim ilarly when application switches to Slow-wait mode after recovering from Wait mode, fADC shall be in specified range. 2. Similarly, when switching back from Slow mode to Run mode (or Slow-Wait to Wait mode), if ADC conversion is intended, the fADC should not increase above the fADC max specified in th e data sheet. Conversion results are not guaranteed outside the operating frequency range of ADC. 3. For ADCs with Wait mode wake up capability, it is recommended to use Wait mode for ADC conversion. This will improve results because the CPU is off in Wait mode, and this reduces the noise generated by digital switching. 4. If the ADC does not have an interrupt capability for waking up from Wait mode, then any oth er interrupt (for example a Timer interrupt) can be used to take advantage of the reduced in tern al noise in Wait mode. Before entering Wait mode, ADC conversion can be started, and the results can be read after exit from Wait mode. 5. If ADC is off/disabled, leakage current can flow into the ADC if the analog channels are connected to the analog input pins. This is because of finite impedance of IO pins. 6. If the ADC is not used in the application, and you want to save power consumption, then you must disable the ADC through software. 7. When entering a power saving mode, disable the ADC if you do not need it to perform conversion while the microcontroller is in power saving mode. If the ADC is not disabled before
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entering power saving mode (except Halt or Active-Halt), the internal analog circuit will consume some current.
8 RELATED DOCUMENTATION
You can refer to the following application notes for additional useful information: AN435: Designing with microcontrollers in noisy environment AN898: EMC General Information AN901: EMC Guidelines for microcontroller - based applications AN1015: Software techniques for improving microcontroller EMC performance
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