STV82x8
Digital Audio Decoder/Processor for BTSC Television/Video Recorders
PRELIMINARY DATA
Key Features
Fully Automatic Multi-Standard Demodulation M/N standards FM mono BTSC (US MTS) stereo and SAP standards
Multi-Channel Capability 3 I²S digital inputs, S/PDIF (in/out) 5.1 analog outputs Dolby Pro Logic Dolby Pro Logic II 2 I²S digital outputs (TQFP100 only) 2 asynchronous I²S digital inputs (TQFP100 only)
Virtual or true multi-channel capabilities and easy digital links make them ideal for digital audio low cost consumer applications. Starting from enhanced stereo up to independent control of 5 loudspeakers and a subwoofer (5.1 channels), the STV82x8 family offers standard and advanced features plus sound enhancements, spatial and virtual effects to enhance television viewer comfort and entertainment.
Typical Applications
Analog and digital TV with virtual surround sound Analog and digital TV with multi-channel surround sound DVD and HDD recorders "Palm size" portable TV
Sound Processing ST royalty-free processing: ST WideSurround, ST OmniSurround, ST Dynamic Bass, ST Bass Enhancer, SRS WOWTM , SRS TruSurround XTTM which is Virtual Dolby Surround and Virtual Dolby Digital compliant Independent Volume / Balance for Loudspeakers and Headphone Loudspeakers: Smart Volume Control (SVC), 5-band equalizer and loudness Headphone: Smart Volume Control (SVC), basstreble, loudness, ST Dynamic Bass and SRS TruBassTM 3 different bip tones
8 2x V8 ST
S
8 TV
2x
8
TQFP80 Package
TQFP100 Package
Analog Audio Matrix 4 stereo inputs or 5 stereo inputs (TQFP100 only) 3 stereo outputs Pass-thru mode
Audio Delay for Audio Video Synchronization Embedded stereo delay up to 120 ms for lip-sync function Independent delay on headphone and loudspeaker channels Exter nal additional audio delay support (TQFP100 only)
2004 SRS Labs, Inc. All rights reserved, SRS and the SRS logo are registered trademarks of SRS Labs, Inc.
The STV82x8 family, based on audio digital signal processors (DSP), performs high quality and advanced dedicated digital audio processing.These devices provide all of the necessary resources for automatic detection and demodulation of analog audio transmissions for USA, Taiwanese, Brazilian etc. terrestrial analog TV broadcasts.
"Dolby", "Pro Logic", and the double-D symbol are trademarks of Dolby Laboratories.
Rev. 1 February 2005 1/157
CLK_SEL
XTALIN
XTALOUT
2/157
I²S Inputs/Output O_PCM_CLK S/PDIF in S/PDIF out
Audio DAC
0.9 VRMS
DATA_0 DATA_1 DATA_2 LR_CLK
I²S Interface
S_C L K
IRQ Volume Balance Mute matrix
Audio DAC
0.9 VRMS
Automatic
Headphone Detection
Detection & Smar t Control
Loudspeakers Digital Audio Processing Delay, Equalizer, Loudness Dolby Pro Logic Dolby Pro Logic II, ST WideSurround, ST Dynamic Bass, ST OmniSurround, ST Bass Enhancer Smar t Volume Control, Bass Management, Bip tones SRS WOWTM or TruSurroundTM
LS_L LS_R Loudspeakers LS_C LS_SUB
Sound IF BTSC Digital Decoder
H eadphone Digital Audio Processing Volume, Balance, Loudness Smar t Volume Control ST Dynamic Bass, Bass/Treble SRS TruBassTM
Audio DAC
Audio Matrix
SIF
AGC
A/D
Back-end Processing and Pre-scaler
Audio DAC
0.9 VRMS
Mono Input MONO_IN Audio A/D
HP_LSS_L HP_LSS_R Headphone / Surround
2VRMS
SC1_IN_L SC1_IN_R
Figure 1: STV82x8 Block Diagram (TQFP80)
SC2_IN_L SC2_IN_R
SC1_OUT_L SC1_OUT_R
SC3_IN_L SC3_IN_R
Input Analog Audio Matrix
SC4_IN_L SC4_IN_R I²C Interface Clock Generator
Output Analog Audio Matrix
2VRMS
SC2_OUT_L SC2_OUT_R
2VRMS
SCART Inputs SDA
SC3_OUT_L SC3_OUT_R SCART O u tp u ts
S CL I²C
STV82x8
STV82x8
A_DATA I²S Inputs/Outputs I²S Outputs P CM _ CL K O_SCLK O_LR_CLK O_DATA_1 O_DATA_0 S/PDIF in S/PDIF out
Audio DAC
0.9 VRMS
S CL K
DATA_0 DATA_1 DATA_2 LR_CLK
A_LR_CLK
A_S _ CLK
D_DATA
Loudspeakers Digital Audio Processing Delay, Equalizer, Loudness Dolby Pro Logic Dolby Pro Logic II, ST WideSurround, ST Dynamic Bass, ST OmniSurround, ST Bass Enhancer Smar t Volume Control, Bass Management, Bip tones SRS WOWTM or TruSurround XTTM
I²S interface
IRQ Volume Balance Mute matrix
Audio DAC
0.9 VRMS
Automatic
Headphone Detection
Detection & Smar t Control
LS_L LS_R Loudspeakers LS_C LS_SUB
Audio Matrix
Sound IF SIF1 BTSC Digital Decoder
Headph one Digital Audio Processing Delay,Bass/Treble, Loudness, Smar t Volume Control, ST Dynamic Bass, Bip tones SRS TrubassTM,
Audio DAC
SIF2
AGC
A/D
Back-end Processing and Pre-scaler
Audio DAC
0.9 VRMS
Mono Input MONO_IN Audio A/D
HP_LSS_L HP_LSS_R Headphone / Surround
2VRMS
SC1_IN_L SC1_IN_R
Figure 2: STV82x8 Block Diagram (TQFP100)
SC2_IN_L SC2_IN_R
SC1_OUT_L SC1_OUT_R
SC3_IN_L SC3_IN_R
Input Analog Audio Matrix
SC4_IN_L SC4_IN_R I²C Interface Clock Generator
Output Analog Audio Matrix
2VRMS
SC2_OUT_L SC2_OUT_R
SC5_IN_L SC5_IN_R
2VRMS
SCART Inputs SCL I ²C CLK_SEL XTALIN XTALOUT SDA
SC3_OUT_L SC3_OUT_R SCART Output s
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STV82x8
Table of Contents
Chapter 1
1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
STV82x8 Overview . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 13
1.1.1 Core Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....13 1.1.2 Software Information . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...14 1.1.3 Electrical Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..14
1.2
Typical Applications . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 15
Chapter 2 Chapter 3
3.1 3.2
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Digital Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sound IF Signal . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 19 Demodulation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 19
Chapter 4
4.1 4.2 4.3 4.4 4.5 4.6
Dedicated Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Back-end Processing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 21 Audio Processing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 22 ST WideSurround . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 24 ST OmniSurround . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 25 Dolby Pro Logic II Decoder . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 25 Bass Management . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 25
4.6.1 Bass Management Configuration 0 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .26 4.6.2 Bass Management Configuration 1 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .26 4.6.3 Bass Management Configuration 2 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .27 4.6.4 Bass Management Configuration 3 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .28 4.6.5 Bass Management Configuration 4 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .29
4.7
SRS WOW and TruSurround XT . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 29
4.7.1 SRS TruSurround . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...29 4.7.2 SRS WOW . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....30
4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15
Smart Volume Control (SVC) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 30 ST Dynamic Bass/ST Bass Enhancer . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 31 5-Band Audio Equalizer . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 31 Bass/Treble Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 31 Automatic Loudness Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 32 Volume/Balance Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 32 Soft Mute Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 33 Beeper . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 33
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STV82x8 Chapter 5 Chapter 6
6.1
Analog Audio Matrix (Input / Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 I²S Interface (In / Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
I²S Inputs . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 36
6.1.1 I²S Inputs in TQFP 80 Package . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..36 6.1.2 I²S Inputs in TQFP 100 Package . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....37
6.2
I²S Outputs . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 37
6.2.1 I²S Outputs in TQFP 80 Package . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....37 6.2.2 I²S Outputs in TQFP 100 Package . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..38
Chapter 7 Chapter 8
8.1
S/PDIF Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Power Supply Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Standby Mode (Loop-through mode) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 41
Chapter 9
9.1 9.2 9.3
Additional Controls and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Headphone Detection . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 42 IRQ Generation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 42 I²C Bus Expander . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 42
Chapter 10 Chapter 11
11.1 11.2
STV82x8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 I²C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
I²C Address and Protocol . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 44 Start-up and Configuration Change Procedure . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 45
Chapter 12
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10
Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
I²C Register Map . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 47 Software Registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 49 STV82x8 General Control Registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 53 Clocking 1 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 56 Demodulator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 58 Demodulator Channel 1 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 61 I2S and Analog Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 69 Clocking 2 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 72 DSP Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 73 Automatic Standard Recognition . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 78
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STV82x8
12.11 12.12 12.13 12.14 12.15 12.16 12.17 12.18 12.19 12.20 Demodulator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 81 Audio PreProcessing & Selection . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 84 Matrixing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 89 Audio Processing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 96 Mute . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 123 Beeper . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 124 SPDIF Output Configuration . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 126 Headphone Configuration . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 126 DAC Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 127 AutoStandard Coefficients Settings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 129
Chapter 13
13.1 13.2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
TQFP 80-pin Package . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 131 TQFP 100-pin Package . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 134
Chapter 14 Chapter 15 Chapter 16
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.12 16.13 16.14
Application Diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Input/Output Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Absolute Maximum Ratings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 145 Thermal Data . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 145 Power Supply Data . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 145 Crystal Oscillator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 146 Analog Sound IF Signal . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 146 SIF to I²S Output Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 146 SCART to SCART Analog Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 147 SCART and MONO IN to I²S Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 148 I2S to LS/HP/SUB/C Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 148 I²S to SCART Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 148 MUTE Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 149 Digital I/Os Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 149 I²C Bus Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 150
I²S Bus Interface . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 151
Chapter 17
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Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
STV82x8
17.1 17.2 TQFP80 Package . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 153 TQFP100 Package . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 154
Chapter 18
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
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General Description
STV82x8
1
General Description
This chip performs BTSC stereo and SAP analog TV stereo sound identification and demodulation (no specific I²C programming is required). It offers various audio processing functions such as equalization, loudness, beeper, volume, balance, and surround effects. It provides a cost-effective solution for analog and digital TV designs. The STV82x8 is an audio processor which integrates SRS WOWTM, SRS TruSurround XTTM, Dolby Pro Logic, Dolby Pro Logic II, Virtual Dolby Surround (VDS) and Virtual Dolby Digital (VDD) capabilities. Advanced ST royalty-free algorithms such as ST OmniSurround, ST WideSurround, ST Dynamic Bass, ST Bass Enhancer are also available in this audio sound processor. ST OmniSurround is a certified Dolby algorithm for the Virtual Dolby Digital (VDD) and the Virtual Dolby Surround (VDS). When using VDD or VDS, either an external Dolby Digital or an internal Pro Logic (or Pro Logic II) decoder must be used respectively. The STV82x8 is perfectly suited to current and future digital TV platforms, based on audio/video digital chips (STD2000 - DTV100 platform) which include an internal digital decoder (MPEG, Dolby Digital...). In the case where a Dolby Digital decoder is embedded in the audio/video digital chip, Virtual Dolby Digital certification could be obtained.
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STV82x8
General Description
Table 1: STV82x8 Version List (TQFP 80)
STV8248 S T V 8 2 1 8 S T V 8 2 3 8 S T V 8 2 4 8 D S X STV8258 S T V 8 2 5 8 D S T V 8 2 5 8 D S X STV8268 S T V 8 2 6 8 D S X STV8278 S T V 8 2 7 8 D S X STV8288 S T V 8 2 8 8 D S X
S T V 8 2 4 8 D
S T V 8 2 6 8 D
S T V 8 2 7 8 D
S T V 8 2 8 8 D
Multi-Channel Capabilities I²S data input number Analog loudspeakers output number
1 2.1 1 2.1 1 2.1 1 2.1 3 2.1 3 2.1 1 5.1 1 5.1 3 5.1 3 5.1 3 5.1 3 5.1
Embedded SRS and Dolby algorithms Dolby Pro Logic (DPLI) or Dolby Pro Logic II (DPLII) SRS WOWTM (WOW) or SRS TruSurround XTTM (XT) General Capabilities S/PDIF Pass-thru BTSC & SAP / Mono FM Demodulation ST OmniSurround1, ST WideSurround ST Voice, ST Dynamic Bass, ST Bass Enhancer Dolby Pro Logic (DPLI) or Dolby Pro Logic II (DPLII) 5.1 output Dolby Digital Bypass 5.1 output2 Vir tual Dolby Surround Vir tual Dolby Digital capability2
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X WOW DPLI DPLI DPLI DPLI DPLI DPLI DPLI DPLI DPLII DPLII
XT
XT
XT
XT
XT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DPLI
DPLI
DPLI
DPLI
DPLII
DPLII
X X X
X X X
X X X
X X X
1. When using Virtual Dolby Digital or Virtual Dolby Surround with ST OmniSurround or SRS TruSurround XTTM a Dolby Digital or a Pro Logic (or Pro Logic II) decoder is mandatory respectively 2. Dolby Digital Bypass capability or Virtual Dolby Digital are obtained with the use of an external Dolby Digital decoder (for example STD2000).
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General Description
Figure 3: Package Ordering Information
STV82x8
Order Code: STV82x8 (Tray) STV82x8/T (Tape & Reel) For Example: STV8258DSX/T will be delivered in Tape & Reel conditioning
FP TQ
80
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STV82x8
General Description
Table 2: STV82x8 Version List (TQFP 100)
STV8248 S T V 8 2 1 8 F S T V 8 2 3 8 F S T V 8 2 4 8 F D S X STV8258 S T V 8 2 5 8 F D S T V 8 2 5 8 F D S X STV8268 S T V 8 2 6 8 F D S X STV8278 S T V 8 2 7 8 F D S X STV8288 S T V 8 2 8 8 F D S X
S T V 8 2 4 8 F D
S T V 8 2 6 8 F D
S T V 8 2 7 8 F D
S T V 8 2 8 8 F D
Multi-Channel Capabilities I²S data input number Analog loudspeakers output number
1 2.1 1 2.1 1 2.1 1 2.1 3 2.1 3 2.1 1 5.1 1 5.1 3 5.1 3 5.1 3 5.1 3 5.1
Embedded SRS and Dolby algorithms Dolby Pro Logic (DPLI) or Dolby Pro Logic II (DPLII) SRS WOWTM (WOW) or SRS TruSurround XTTM (XT) General Capabilities S/PDIF Pass-thru Second SIF input I²S Output (always available) BTSC & SAP / Mono FM Demodulation ST OmniSurround1, ST WideSurround ST Voice, ST Dynamic Bass, ST Bass Enhancer Dolby Pro Logic (DPLI) or Dolby Pro Logic II (DPLII) 5.1 output Dolby Digital Bypass 5.1 output2 Vir tual Dolby Surround Vir tual Dolby Digital capability2
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X WOW DPLI DPLI DPLI DPLI DPLI DPLI DPLI DPLI DPLII DPLII
XT
XT
XT
XT
XT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DPLI
DPLI
DPLI
DPLI
DPLII
DPLII
X X X
X X X
X X X
X X X
1. When using Virtual Dolby Digital or Virtual Dolby Surround with ST OmniSurround or SRS TruSurround XTTM a Dolby Digital or a Pro Logic (or Pro Logic II) decoder is mandatory respectively 2. Dolby Digital Bypass capability or Virtual Dolby Digital are obtained with the use of an external Dolby Digital decoder (for example STD2000).
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General Description
Figure 4: Package Ordering Information
STV82x8
Order Code: STV82x8F (Tray) STV82x8F/T (Tape & Reel) For Example: STV8258FDSX/T will be delivered in Tape & Reel conditioning
TQ
00 P1 F
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STV82x8
General Description
1.1
1.1.1
STV82x8 Overview
Core Features
Single audio source processing: -- IF source and/or analog stereo input (SCART) -- one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three I²S)
SIF input signal with Automatic Gain Control (AGC) BTSC and SAP demodulator, FM Mono Audio processor working at 48 kHz with specific features: -- For loudspeakers (L, R, LS, RS, SubW, C): Dolby Pro Logic II decoder with bass management SRS WOWTM or TruSurround XTTM including Virtual Dolby Surround and Virtual Dolby Digital ST WideSurround ST OmniSurround ST Dynamic Bass / ST Bass Enhancer 5-band equalizer or bass / treble controls Loudness Smar t Volume Control Volume/balance/soft-mute Three different types of bips Video processing delay compensation -- For headphones: SRS TruBassTM ST Dynamic Bass Smar t Volume Control Bass / treble controls Loudness Volume/balance/soft-mute Three different types of bips Video processing delay compensation
Shared outputs for headphone and certain loudspeakers (surround channels); Analog matrix with: -- Five external inputs: Four SCART inputs (2 VRMS capable) One analog mono input (0.5 VRMS) -- One internal input from a digital matrix via a DAC -- Three external outputs (2 VRMS capable) -- One internal output for the digital matrix (using an internal ADC)
Digital matrix with: -- Three input modes (demodulator/SCART, SCART only and I²S) -- Three stereo outputs (loudspeakers, headphone and SCART)
High-end audio DAC S/PDIF output for connection with an external amplifier/decoder Internal multiplexer for the S/PDIF output (to share the internal S/PDIF output and the S/PDIF output generated by the external decoder of the digital broadcast)
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General Description
STV82x8
Specific stand-by mode (loop-through) Control by I²C bus (two I²C addresses) System PLL and clock generation using either a single crystal oscillator or a differential clock input
1.1.2
Software Information
The different software combinations are listed in Table 3.
Table 3: Input/Output Software Configurations
Output (Number of Channels)
Input (Number of Channels) 2 (+1) 1 (Mono) ST WideSurround or SRS WOWTM ST WideSurround or ST OmniSurround or SRS TruSurround XTTM or SRS WOWTM or Dolby Pro Logic II ST WideSurround or ST OmniSurround or SRS TruSurround XTTM or SRS WOWTM or Dolby Pro Logic I or II ST OmniSurround or SRS TruSurround XTTM ST OmniSurround or SRS TruSurround XTTM 4 (+1) 5.1
2 (LO & RO)
Dolby Pro Logic II
Dolby Pro Logic II
2 (LT & RT)
Dolby Pro Logic I or II
Dolby Pro Logic II
4 (+1) 5.1
No processing Downmix No processing
Note: Note:
In addition to the above sound processing, it is always possible to add ST Voice and also ST Dynamic Bass or ST Bass Enhancer algorithms. The SRS TruSurround and ST OmniSurround are approved by Dolby Labs as Virtual Dolby Surround (VDS) and Virtual Dolby Digital (VDD). The SRS TruSurround XTTM system is composed of:
SRS TruSurroundTM SRS WOWTM SRS Dialog ClarityTM SRS TruBassTM SRS 3D mono / stereo
The SRS WOWTM system also includes:
1.1.3
Electrical Features
Multi Power Supplies: 1.8 V, 3.3 V and 8 V. Power Consumption:
lower than 800mW in functional mode (full features) 200 mW in loop-through mode corresponding to the switch-off of all digital blocks
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STV82x8
General Description
1.2
Typical Applications
The STV82x8 is specified to enable flexible, analog and digital TV chassis design (refer to Figure 5, Figure 6, Figure 7 and Figure 8). The main considerations are:
all necessary connections between devices can be provided through the TV set, pseudo stand-by mode used to copy to VCR or the DVD sources when the TV set is OFF, pin compatibility with previous STV82x7 (TQFP80 package) TV design.
The STV82x8 can be used to process dual audio sources (one analog and one digital in parallel). Note: Headphone and loudspeakers can be used simultaneously for dual-language purpose. In this case, certain restrictions occur (see Section 4.2: Audio Processing). For more connections, the SCART-to-SCART path can be used. The use of these full analog paths implies that the sound is not digitally processed.
Figure 5: STV8238 Typical Application (Enhanced Stereo)
Tuner
I²S In and Out (TQFP100) S/PDIF I²S In or Out (TQFP80) Output & Pass-thru
R
STV8238
or Demodulation - BTSC stereo & SAP Sound Processing - Volume, Balance, 5-Band Equalizer - ST OmniSurround - SRS WOWTM
SubW
L
4 x SCART (TQFP100) Left Right
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General Description
Figure 6: STV8248 Typical Application (Analog Virtual Sound)
STV82x8
I²S In and Out (TQFP100) I²S In or Out (TQFP80) Tuner
S/PDIF Output & Pass-thru
R
STV8248
or Demodulation - BTSC stereo & SAP Sound Processing - Volume, Balance, 5-Band Equalizer - SRS TruSurround XTTM - ST OmniSurround - Virtual Dolby Surround1 SubW
L
4 x SCART (TQFP100) Left Right
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic decoder is mandatory.
Figure 7: STV8258 Typical Application (Digital: Virtual Sound)
Multi-Channel Digital Decoder (Dolby Digital)
R S/PDIF Output & Pass-thru SubW
I²S
Tuner
STV8258
Demodulation - BTSC stereo & SAP Audio Processing - Volume, Balance, 5-Band Equalizer - SRS TruSurround XTTM - ST OmniSurround - Virtual Dolby Surround1 - Virtual Dolby Digital2
or
L
4 x SCART (TQFP100) Left Right
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic decoder is mandatory. 2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, an external Dolby Digital decoder is mandatory.
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STV82x8
General Description
Figure 8: STV8288 Typical Application (Digital TV: Multi-Channel and Virtual Sound)
Multi-Channel Digital Decoder (Dolby Digital)
I²S
Tuner
S/PDIF Output & Pass-thru
R
SubW
RS C LS L
STV8288
Demodulation - BTSC stereo & SAP Audio Processing - Volume, Balance, 5-Band Equalizer - Dolby Pro Logic II - ST OmniSurround - 5.1 Analog Outputs - SRS TruSurround XTTM - Virtual Dolby Surround1 - Virtual Dolby Digital2
or
4 x SCART (TQFP100)
Left Right Shared with surround LS/RS
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic decoder is mandatory. 2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, an external Dolby Digital decoder is mandatory.
Figure 9: STV8218 Typical Application (DVD & HDD Recorders)
A/V Codec (Digital Recorder)
Tuner
I²S
or
STV8218
Demodulation - BTSC stereo & SAP - Volume, Balance, 5-Band Equalizer - ST OmniSurround
4 x SCART (TQFP100) Left Right
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System Clock
STV82x8
2
System Clock
The System Clock integrates 2 independent frequency synthesizers. The first frequency synthesizer is used by the demodulator at a frequency of 24.576 MHz. The second frequency synthesizer is used by the DSP core and can be adjusted between 100 and 150 MHz depending on the application. The default values are designed for a standard 27-MHz reference frequency provided by a stable single crystal oscillator or an external differential clock signal (for example, from the STV35x0) depending on the CLK_SEL pin configuration (CLK_SEL = 1 means a single crystal oscillator, 0 means an external differential clock). The 27-MHz value is the recommended frequency for minimizing potential RF interference in the application. The sinusoidal clock frequency, and any harmonic products, remain outside the TV picture and sound IFs (PIF/SIF) and Band-I RF.
Note:
A change in the reference frequency is compatible with other default I²C programming values, including those of the built-in Automatic Standard Recognition System.
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STV82x8
Digital Demodulator
3
Digital Demodulator
The Digital Demodulator (see Figure 10) consists of a channel demodulator and a stereo/SAP decoder. All channel parameters are programmed automatically by the built-in Automatic Standard Recognition System (Autostandard) in order to find the STEREO or the SAP modes. Channel parameters can also be programmed manually via the I²C interface for very specific standards not included among the known standards.
Figure 10: Demodulator Block Diagram
DSP Processing
DEMOD_STAT(0Dh) STEREO_SAP_STATUS(4Ch) ACOEFF1(1Dh) CARFQ1 (12-14h) FIR1C (15-1Ch) BCOEFF1(1Eh) SAP_CONF(47h) AUTOSTD DETECTION
SIF
AGC Amp
A/D
DCO1+ Mixer
Channel Filter FIR1
FM Demodulator
Stereo/SAP Demodulator
(L+R)* or mono* (L-R)dbx or SAPdbx
Deemphasis, DBX decoding and dematrixing
AGC Control *: Pre-emphasis signal dbx: DBX -encoded signal
3.1
Sound IF Signal
The Analog Sound Carrier IF is connected to the STV82x8 via the SIF pin. Before Analog-to-Digital Conversion (ADC), an Automatic Gain Control (AGC) is performed to adjust the incoming IF signal to the full scale of the ADC. A preliminary video rejection is recommended to optimize conversion and demodulation performances. The AGC system provides a gain value allowing for a wide range of SIF input levels. The TQFP100 package provides a second SIF input.
3.2
Demodulation
The demodulation system operates by default in Automatic mode. In this mode, the STV82x8 is able to identify and demodulate the BTSC TV sound standard including stereo and SAP modes without any external control via the I²C interface. The built-in Automatic Standard Recognition System (Autostandard) automatically programs the appropriate bits in the I²C registers which are forced to Read-only mode for users. STEREO and SAP modes can be removed (or added) from the List of modes to be recognized by programming registers AUTOSTD_CTRL. The identified standard is displayed in register AUTOSTD_STATUS and any change to standard is flagged to the host system via pin IRQ. This flag
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Digital Demodulator
STV82x8
must be reset by re-programming the LSB of register IRQ_STATUS while checking the detected standard status by reading registers AUTOSTD_STATUS. ITo recover out-of standard FM deviations or the Sound Carrier Frequency Offset, additional I²C controls are provided without interfering with the Automatic Standard Recognition System (Autostandard).
Table 4: BTSC Standard Aural Carrier (4.5 MHz) Peak Deviation
25 kHz (1) 0Fh L-R 2nd Channel 0.05 -15 kHz 0.05 -15 kHz DBX Compression DBX Compression 2Fh 5Fh AM DSB SC FM 10 kHz 5 kHz 50 kHz(1) 15 kHz
Source
Modulation
Frequency Range
Audio Preprocessing
Sub-Carrier
Modulation Type
Sub-Carrier Deviation
Monophonic Pilot Stereophonic SAP
L+R
0.05 -15 kHz
75 s Preemphasis
(1) L+R and L-R must not exceed 50 kHz Sound Carrier Frequency Offset Recovery:IF Carrier frequency can be adjusted with register CAROFFSET1 within a large range (up to 120 kHz ) while the Automatic Standard Recognition System remains active. The frequency offset estimation is written in registers DEMOD_DC_LEVEL and can be used to implement the Automatic Frequency Control (AFC) via an external I²2C control. Manual Mode: If required, the Automatic Standard Recognition System system can be disabled (Manual mode) and the user can control all registers including those only controlled by the Automatic Standard Recognition System function when active. Manual mode is selected in register AUTOSTD_CTRL by setting to 0 bits SAP_CHECK, STEREO_CHECK and MONO_CHECK.
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STV82x8
Dedicated Digital Signal Processor (DSP)
4
Dedicated Digital Signal Processor (DSP)
A dedicated Digital Signal Processor (DSP) takes charge of all audio processing features and the low frequency signal processing features of the demodulator. The internal 24-bit architecture will ensure a high quality signal treatment and an excellent dynamic.
4.1
Back-end Processing
The "back-end" processing corresponds to the low frequency signal processing (32 kHz or higher frequencies) of the demodulator and other inputs (I²S, ADC). Figure 11 shows a flowchart of the back-end processing tasks. However, the figure shows that the processing is only a SINGLE SOURCE PROCESSING flow (no processing is possible with "Demod + SCART" and I²S inputs simultaneously) and that the selection of a headphone output restricts the loudspeakers configuration to 2.1 instead of 5.1.
Figure 11: Back-end Audio Processing
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Dedicated Digital Signal Processor (DSP)
The main features depend on the path:
STV82x8
FM Channel -- DC Removal -- Prescaling -- De-emphasis (50 or 75 us) -- Stereo Dematrix
Input SCART Channel -- DC Removal -- Prescaling
Input I²S Channel -- I²S Prescaling Digital Audio Matrix -- Audio Channel Multiplexer between the different sources (IF, I²S, SCART) towards all outputs (S/PDIF, LS, HP or SCART).
Autostandard management -- device configuration depending on the standard to be detected -- freeze the device when a standard is detected -- once a standard detected, check that there is no change in the detection status -- set the correct action depending on any change in the detection status (mono backup or mute setup and new standard detection)
SCART -- Downmixing: LT / RT or L0 / R0 (see AC-3 specification) -- Soft Mute
4.2
Audio Processing
The following software is provided for main loudspeakers (L, R, C, LS, RS, SubW):
Downmix Dolby Pro Logic II Decoder (LT, RT L, R, C, Ls, Rs, SubW) with Bass Management ST WideSurround, ST OmniSurround, SRS WOWTM or SRS TruSurround XT (certified
Virtual Dolby Surround and Virtual Dolby Digital)
ST Dynamic Bass and ST Bass Enhancer Smar t Volume Control (SVC) 5-band Equalizer or Bass-Treble Loudness Volume with independent channels (Smooth Volume Control) Master Volume Control Mute/soft-mute Balance Beeper Pink Noise Generator (used to position the loudspeakers) Programmable Delay for each loudspeaker Adjustable Delay for "lip sync" up to 120 ms (to compensate for audio/video latency)
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STV82x8
Dedicated Digital Signal Processor (DSP)
The following software is provided for the headphone or auxiliary output:
Downmix SRS TruBassTM ST Dynamic Bass Smar t Volume Control (SVC) Bass/Treble Loudness Independent Volume for each channel (Smooth Volume Control) Soft Mute Balance Beeper Adjustable Delay for "lip sync" feature up to 120 ms (to compensate for audio/video latency)
The following software is provided for SCART or S/PDIF outputs:
Downmix Soft Mute
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Dedicated Digital Signal Processor (DSP)
STV82x8
Figure 12: Audio Processing for Loudspeakers, Headphone, SCART and S/PDIF outputs
4.3
ST WideSurround
STV82x8 offers three preset ST WideSurround Sound effects on the Loudspeakers path:
Music, a concert hall effect Movie, for films on TV Simulated Stereo, which generates a pseudo-stereo effect from mono source
"ST WideSurround Sound" is an extension of the conventional stereo concept which improves the spatial characteristics of the sound. This could be done simply by adding more speakers and coding more channels into the source signal as is done in the cinema, but this approach is too costly for
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STV82x8
Dedicated Digital Signal Processor (DSP)
normal home use. The ST WideSurround system exploits a method of phase shifting to achieve a similar result using only two speakers. It restores spatiality by adding artificial phase differences. The Surround/Pseudo-stereo mode is automatically selected by the Automatic Standard Recognition System (Autostandard) depending on the detected stereo or mono source. By default, "Movie" is selected for Surround mode. This value may be changed to "Music" by the WIDESRND_MODE bit in the WIDESRND_CONTROL register. Additional user controls are provided to better adapt the spatial effect to the source. The ST WideSurround Gain (WIDESRND_LEVEL) and ST WideSurround Frequency (WIDESRND_FREQ) registers can be used to enhance Music Predominancy in Music mode and Theater effect and Voice Predominancy in Movie mode.
4.4
ST OmniSurround
STV82x8 offers a spatial virtualizer to output any multi-channel input in stereo on the Loudspeakers path. "ST OmniSurround" will recreate a multi-channel spatial sound environment using only the Left and Right front speakers. It can be adapted to any input configuration (OMNISRND_INPUT_MODE). ST Voice will allow you to enhance the voice content of your program to increase the intellegibility and the presence of the sound.
4.5
Dolby Pro Logic II Decoder
Dolby Pro Logic II is a matrix decoder that decodes the five channels of surround sound that have been encoded onto the stereo sound tracks of Dolby Surround program material such as DVD movies and TV shows. It is even possible to decode standard stereo signals like music or non encoded movies. Furthermore, it is an active process designed to enhance sound localization through the use of very high-separation decoding techniques. The Dolby Pro Logic II decoder is also able to emulate the former Dolby Pro Logic decoder in a specific mode.
4.6
Bass Management
This processing will generate the subwoofer signal and adjust all loudspeakers channels gain and bandwidth. Speakers capable of reproducing the entire frequency range will be referred to as "full range speakers", then signals sent to full range speaker will be full bandwidth (no filtering). Speakers that have limited bass handling capabilities will be referred to as "satellite speakers", then signals sent to satellite speaker will be high-pass filtered to remove bass information below 100 Hz. In the STV82x8, five output configuration modes have been implemented according to "Dolby Digital Consumer Decoder" specifications. They are described below.
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Dedicated Digital Signal Processor (DSP) 4.6.1 Bass Management Configuration 0
STV82x8
In some cases, the bass management filters are available in the decoder itself, so there is no need to reproduce these filters. The output configuration shown in Figure 13 offers this possibility.
Figure 13: Bass Management Configuration 0 (with Pro Logic switch indicating its reset state) L L
R
R
C
C
Ls
Ls
Rs -15 dB LFE -5 dB +
Rs
SubW
4.6.2
Bass Management Configuration 1
Configuration 1, shown in Figure 14, assumes that all five speakers are not full range and that all of the bass information will be redirected to and reproduced by a single subwoofer. This configuration is intended for use with 5 satellite speakers. To prevent signal overload, the five main channels are attenuated by 15 dB, while the LFE channel is attenuated by 5dB to maintain the proper mixing ratio.
Figure 14: Bass Management Configuration 1 (with Pro Logic switch indicating its reset state) L
L
R
R
C
C
Ls
Ls
Rs -15 dB LFE -5 dB +
Rs
SubW
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STV82x8 4.6.3 Bass Management Configuration 2
Dedicated Digital Signal Processor (DSP)
Configuration 2 assumes that the left and right speakers, are full range while the center and surround speakers are smaller speakers. Also, all bass data is redirected to the left and right speakers. This configuration include output level adjustment that allows 12 dB attenuation for the 3 smaller speakers (C, Ls, Rs). When the level adjustment will be disabled the decoder boosts by 12 dB the full range speakers (Left, Right).
Figure 15: Bass Management Configuration 2 (all switches indicate their reset state)
Level Adjustment OFF Switch L -12 dB + -1.5 dB C -12 dB C R +12 dB -1.5 dB Ls -12 dB + Rs -15 dB LFE -5 dB + SubW -12 dB Rs Subwoofer ON Switch Ls L
+12 dB
R
-12 dB
+
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Dedicated Digital Signal Processor (DSP) 4.6.4 Bass Management Configuration 3
STV82x8
The third configuration, shown in Figure 16, assumes that all speakers except the center are full range, then all bass information will be directed to and reproduced by the front left and front right and both surround speakers. In order to provide more flexibility to this configuration, a switch will offer an option which will produce a subwoofer channel by the LFE channel. When the Subwoofer Switch is OFF, the input channels will be attenuated by 8 dB. Configuration 3 is required in certain high-end products.
Figure 16: Bass Management Configuration 3 (all switches indicate their reset state) Level Adjustment OFF Switch + L
L
-8dB -4dB
+
+8dB +4dB +8dB +4dB
C
C
-8dB -4dB -4.5dB
R
-8dB -4dB
+
+
+8dB +4dB + +8dB +4dB + +8dB +4dB
R
Ls
Ls
-8dB -4dB -8dB -4dB
Rs
Rs
LFE
-8dB -4dB Subwoofer ON Switch Subwoofer ON Switch +10dB SubW
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STV82x8 4.6.5 Bass Management Configuration 4
Dedicated Digital Signal Processor (DSP)
This configuration implements the Simplified Dolby configuration. The center, left surround and right surround channels are summed and then filtered by the LPF. The composite bass information is either summed back into the left and right channels or summed with the LFE channel and sent to the subwoofer output, see Figure 17.
Figure 17: Implementation of the Bass Management Configuration 4 (Simplified Configuration)
L
+
L
C
C
R
+
R
Ls
Ls
Rs -4.5dB Subwoofer ON Switch -10.5dB -5dB +
Rs
+
LFE
SubW
4.7
SRS WOW and TruSurround XT
The SRS TruSurround XTTM is a processing system that can accept from 1 to 6 channels on input and that will generate a 2-channel output signal. This processing system includes the latest SRS algorithms:
SRS WOWTM SRS TruSurround (Multi-channel signal virtualizer)
4.7.1
SRS TruSurround
The SRS TruSurround is a processing that can accept from 2 to 5 channels on input and that will generate a 2-channel output signal. SRS TruSurround uses Head-Related Transfer Function (HRTF) -based frequency tailoring of (L/R) difference signals to extend the sound image out past the physical boundaries of the speaker placements to surround channel information. These rear channel HRTF curves have much greater peak to valley differences at center frequencies. These were chosen to cause rear channel difference signals to virtualize farther behind the listener and directed to a different virtual position as compared to front channel signals. Information that is equal (L+R) in the rear surround channels
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Dedicated Digital Signal Processor (DSP)
STV82x8
is processed by an identical HRTF curve but mixed in at a much lower amount. This HRTF processing of equal (L/R) signals was again used to virtualize information to the rear of the listener. The SRS TruSurround is certified by Dolby Laboratories to be a Virtual Dolby Digital and Virtual Dolby Surround.
4.7.2
SRS WOW
The SRS WOWTM is an a sound processing system including:
SRS 3D Mono/StereoTM SRS Dialog ClarityTM SRS TruBassTM
4.7.2.1 SRS 3D Mono/Stereo This system is used to create a pseudo-stereo signal for mono inputs or a three-dimensional spatial signal for stereo inputs. 4.7.2.2 SRS Dialog Clarity This system is used to enhance dialog perception. 4.7.2.3 SRS TruBass The SRS TruBassTM audio enhancement technology provides deep, rich bass to small speaker systems without the need for a subwoofer or additional extra physical components. For systems with a subwoofer, TruBassTM complements and enhances bass performance. Psycho-acoustically, when the human ear is presented with a low frequency sound signal that is missing the fundamental harmonic, it will fill in the fundamental frequency based on the higher harmonics that are present. By accentuating the second and higher frequency harmonics of the bass portion of a signal, TruBassTM gives the perception of greatly improved bass response. SRS TruBassTM is implemented on loudspeakers path, headphone path or on both in parallel.
4.8
Smart Volume Control (SVC)
The Smart Volume Control regulates the audio signal level before audio processing. This regulation is necessary in order for the signal level to be independent from the source (terrestrial channels, I2S or SCART), its modulation (FM) and annoying volume changes (advertising, etc.). The Smart Volume Control works as an audio compressor/expander; i.e. when the input signal exceeds the threshold level, a very rapid attenuation (-2 dB/ms) is applied to rescale the signal down to the threshold value. When the input signal is below the threshold level, the previous attenuation is reduced slowly in order to retrieve the original input level (0dB gain). If the input signal is too low, an addition gain of 6 dB can be provided. To personalize the action of the SVC, five parameters are available: 1. Threshold: Maximum quasi-peak level that can be expected on output 2. Peak measurement mode: Select the channel on which the peak measurement must be performed (Left, Right, Center...) 3. Release time: Gain slope applied to the amplification phase 4. Expander switch: To allow a +6dB amplification of small signals in order to reduce the output dynamic range 5. Make up gain: Allows compensation of the signal amplitude limitation thanks to a 0 to 24 dB adjustable gain.
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STV82x8
Dedicated Digital Signal Processor (DSP)
The SVC is implemented on the loudspeakers path, headphone path or on both in parallel (independent settings). Also, the SVC can be applied in six-channel mode (L, R, LS, RS, C and SubW).
4.9
ST Dynamic Bass/ST Bass Enhancer
STV82x8 offers dynamic bass boost processing on the Loudspeakers path: ST Dynamic Bass is a bass boost process that can dramatically increase the bass content of any program without any output level saturation. 3 cutoff frequencies (BASS_FREQ) can be chosen, 100 Hz, 150 Hz and 200 Hz to adapt the effect to your loudspeakers. The amount of bass (BASS_LEVEL) can also be fine tuned in order to adapt the effect loudness.
4.10
5-Band Audio Equalizer
The loudspeakers audio spectrum is split into 5 frequency bands and the gain of each of band can be adjusted within a range from -12 dB to +12 dB in steps of 0.25 dB. The Audio Equalizer may be used to pre-define frequency band enhancement features dedicated to various kinds of music or to attenuate frequency resonances of loudspeakers or the listening environment. The Equalizer is enabled by the LS_EQ_ON bit in the EQ_BT_CTRL register. The gain value for Band X is programmed in register LS_EQ_BANDX. The 5-Band Audio Equalizer is exclusive with Bass-Treble control. Bit LS_EQ_BT_SW in register EQ_BT_CTRL is used to select either the 5-Band Audio Equalizer or the Bass-Treble control for the Loudspeakers path. Depending on the LS Equalizer or LS Bass-Treble value, the volume level can be clamped to the LS output to prevent any possible signal clipping from occuring using the ANTICLIP_LS_VOL_CLAMP bit in the VOLUME_MODES (D7h) register.
Figure 18: Equalizer f1 = 100 Hz, f2 = 316 Hz, f3 = 1 kHz, f4 = 3.16 kHz and f5 = 10 kHz
4.11
Bass/Treble Control
The gain of bass and treble frequency bands for Headphone can be also tuned within a range from -12 dB to +12 dB in steps of 0.25 dB. It may be used to pre-define frequency band enhancement features dedicated to various kinds of music. The Headphone Bass/Treble feature is enabled by setting the HP_BT_ON bit in the EQ_BT_CTRL register. The Bass and Treble gain values are adjusted in registers HP_BASS_GAIN and HP_TREBLE_GAIN, respectively. Depending on the HP Bass-Treble value, the volume level can be clamped to the HP output to prevent any possible signal clipping from occuring using the ANTICLIP_HP_VOL_CLAMP bit in the VOLUME_MODES (D7h) register.
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Dedicated Digital Signal Processor (DSP)
STV82x8
4.12
Automatic Loudness Control
As the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the Loudness Control corrects this effect by sensing the volume level and then boosting bass and treble frequencies proportionally to middle frequencies at lower volume. While maintaining the amplitude of the 1 kHz components at an approximately constant value, the gain values of lower and higher frequencies are automatically progressively amplified up to +18 dB when the audio volume level decreases.The maximum treble amplification can be adjusted from 0 dB (first order loudness) to +18 dB (second order loudness) in steps of 0.125 dB. As the volume is proportional to the external audio amplification power, the loudness amplification threshold is programmable in order to tune the absolute level. The Loudspeakers Loudness function is enabled by setting the LS_LOUD_ON bit in register LS_LOUDNESS. The Loudspeakers Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The Headphone Loudness function is enabled by setting the HP_LOUD_ON bit in register HP_LOUDNESS. The Headphone Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The loudness cut-off frequency is 100 Hz.
4.13
Volume/Balance Control
The STV82x8 provides a Volume/Balance Control for all output channels configuration (except for S/PDIF) with different volume level per channel (L, R, C, LS, RS, SubW, SCART). Its wide range (from +11.875 to -116 dB, in a dB linear scale with a 0.125 dB step) largely covers typical home applications (approx. 60 dB) while maintaining a good S/N ratio.
Figure 19: Volume Control
Output Gain
+11.875 dB
-116 dB Mute 00h I²C Control 3FFh
An extra Master Volume Control can apply an extra gain/attenuation on L, R, C, LS, RS and SubW channels. The Volume/Balance Control can operate in one of two different modes:
In Differential mode (default value), the volume control is a common volume value for both the Left and Right Loudspeakers or Headphone channels (see Figure 19) and complimentary balance control is used (see Figure 20).
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STV82x8
Dedicated Digital Signal Processor (DSP)
In Independent mode, the volume for the Left and Right channels for Loudspeakers or Headphone is controlled independently.
Figure 20: Differential Balance
Output Gain
100%
R ig ht C ha nn el C ft Le el nn ha
Mute 200h 000h I²C Control (10 bits) 1FFh
4.14
Soft Mute Control
The Digital Soft Mute is applied smoothly (20 ms for 120 dB range) to avoid any switch noise on output. It is available on all output channels pairs:
S/PDIF channel (Left/Right) SCART channels (Left/Right) Loudspeakers channels (Left/Right) Center Subwoofer Headphone/Surround channels (Left/Right)
Another soft mute (analog) is also available on each DAC output.
4.15
Beeper
The beeper is used to generate a tone on the Loudspeakers or/and Headphone outputs. The beeper sound (square wave) is added to the audio signal which is attenuated by 20 dB. The beep sound amplitude includes a smooth attack and decay to avoid any parasitic noise when starting and stopping. It can be used for various applications such as beep sounds for remote control, alarm clock or other features. The Beeper operates in one of two modes:
Pulse mode (beep applications): A tone with a programmable short duration (0.1, 0.25, 0.5 and 1.0 s) is generated. Afterwards, the beeper is automatically disabled and the output is switched back to the audio signal, see Figure 21. Continuous mode (alarm application): A tone with a programmable long duration is generated. Its start and stop controls must be programmed by I²C, see Figure 22.
The Beeper function is enabled by setting the BEEPER_ON bit in register BEEPER_ON. Beeper parameters are controlled in register BEEPER_MODE. The beeper tone level and frequency are programmed in register BEEPER_FREQ_VOL. The level (or volume) ranges between 0 dB and -93 dB in steps of 3 dB and the tone frequency ranges between 62.2 Hz and 8 kHz in steps of 1 octave.
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Dedicated Digital Signal Processor (DSP)
STV82x8
A beep generator is shared only by the Loudspeakers or Headphone outputs. Therefore, in the event of simultaneous beeps when in Pulse mode, only the first beep will define the effective duration that will be the same for both outputs.
Figure 21: Pulse Mode
BEEP_ON = 1
BEEP_ON = 0
0.1, 0.25, 0.5 and 1.0 s T predefined
62.5 Hz < f < 8 kHz
Figure 22: Continuous Mode
BEEP_ON = 1 T defined by I²C write
BEEP_ON = 0
62.5 Hz < F < 8 kHz
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STV82x8
Analog Audio Matrix (Input / Output)
5
Analog Audio Matrix (Input / Output)
The analog part of the audio matrix can be divided into two parts: the SCART input matrix and the SCART output matrix.
Figure 23: SCART Input Matrix
S1in S2in S3in S4in S5in* MONO_in Select
Audio ADC 2
Digital Matrix
*TQFP100 package only
The SCART input matrix is an input for the digital matrix (after the ADC) which select which source will be sent to the DSP.
Figure 24: SCART1/2/3 Output Matrix
S1in S2in S3in S4in S5in* Stereo DAC MONO_in
2 Soft mute S1out
Select or Mute
*TQFP100 only
The SCART output matrix selects the sound to output, which can be directly a SCART input or the output of the DSP. A mute function is provided to switch off the outputs. A soft-mute function is provided to avoid all spurious sounds when switching from one position to another position. The SCART 2 and 3 output matrices have the same functions as the SCART 1 output matrix. The particularity of the matrix is to accept input signal of 2 VRMS and to have the capability to output such level. In this case, the power supply must be 8 V. The Mono audio input is able to accept signals with a 0.5 VRMS amplitude.
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I²S Interface (In / Out)
STV82x8
6
6.1
6.1.1
I²S Interface (In / Out)
I²S Inputs
I²S Inputs in TQFP 80 Package
The STV82x8 can interface with a digital sound decoder. In this case, the digital data can be input at a speed of 0.384 Mbytes/s (3.072 MHz for a 48 kHz sampling frequency with 32 bits of data). A Sample Rate Conversion (SRC) is necessary if input frequency is not 48 kHz (STV82x8 slave) in order to obtain a fixed frequency output from this block (48 kHz).
Note:
The SRC function is only available in single I²S input mode. The interface with one I²S connection (I2S_DATA0) enables the input of stereo or stereo-coded Dolby Pro Logic. One interface with three I²S connections connected to the DSP enables the processing of a multichannel signal (maximum of 6 channels).
Figure 25: TQFP 80 I²S Input Block Diagram
I2S_DATA0 fS Input = 32 to 48 kHz I2S_DATA1 fS Input = 48 kHz only I2S_DATA2 fS Input = 48 kHz only I2S_SCLK fS Input * 64 I2S_LR_CLK fS Input = 32 to 48 kHz
Audio Processing
48 kHz DSP
Processing
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STV82x8 6.1.2 I²S Inputs in TQFP 100 Package
I²S Interface (In / Out)
An additional (auxiliary) asynchronous input is available in the TQFP100 package. An I2SD_DATA input for external delay is also available, but it must be in phase with the I²S output clocks.
Figure 26: TQFP100 I²S Input Block Diagram
I2S_DATA0 fS Input = 32 to 48 kHz I2S_DATA1 fS Input = 48 kHz only I2S_DATA2 fS Input = 48 kHz only I2S_SCLK fS Input * 64 I2S_LR_CLK fS Input = 32 to 48 kHz I2SA_DATA fS Input = 32 to 48 kHz I2SA_SCLK fS Input * 64 I2SA_LR_CLK fS Input = 32 to 48 kHz I2SD_DATA fS Input = 48 kHz in phase with I2SO_LR_CLK and I2SO_SCLK Audio Processing
48 kHz DSP
Processing
6.2
6.2.1
I²S Outputs
I²S Outputs in TQFP 80 Package
A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a converted input audio signal to an external device. In this case, the I2S_DATA0 signal and all clock signals are set as outputs by setting bit D5 in register RESET to 1 (and bit D6 for the clocking). The STV82x8 drives the serial bus (I2S_SCLK, I2S_LR_CLK, and I²2S_DATA0) in master mode in 64.fs format with a sampling frequency (fs) of 48 kHz. The I2S_PCM_CLK signal can be used as a master clock for the slave interface, if required. Both standard and non-standard modes are available.
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I²S Interface (In / Out)
.
Figure 27: TQFP 80 I²S Output Block Diagram
STV82x8
I2S_DATA0 fS Output = 48 kHz I2S_SCLK fS Output * 64 I2S_LR_CLK fS Output = 48 kHz I2S_PCM_CLK
Audio Processing
48 kHz DSP
Processing
6.2.2
I²S Outputs in TQFP 100 Package
Two digital stereo outputs (I²S compatible) are available for routing the demodulated signal or a converted input audio signal to an external device or perform an external delay. In this case, the I2SO_DATA0 and I2SO_DATA1 signals are available with all I²S inputs active. The STV82x8 drives the serial bus (I2SO_SCLK,I2SO_LR_CLK, I2SO_DATA0, and I2SO_DATA1) in master mode in 64.fs format with a sampling frequency (fs) of 48 kHz. The I2S_PCM_CLK signal can be used as a master clock if required for the slave interface. Both standard and non-standard modes are available. .
Figure 28: TQFP100 I²S Output Block Diagram
I2SO_DATA0 fS Output = 48 kHz I2SO_DATA1 fS Output = 48 kHz
Audio Processing
I2SO_SCLK fS Output * 64 I2SO_LR_CLK fS Output = 48 kHz I2S_PCM_CLK
48 kHz DSP
Processing
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STV82x8
Note:
I²S Interface (In / Out)
The Input and Output modes for I²S are exclusive in the TQFP80 package.
Figure 29: I²S Data Format: Lch = LOW, Rch = HIGH (I²S Input or Output mode)
1/fs Lch
I2S_LR_CLK
Rch
I2S_SCLK (= 64fs)
I2S_DATAx (standard mode)
1
2
3
22
23
24
1
2
3
22
23
24
1
2
MSB I2S_DATAx (non-standard mode) 1 2 3 22 23 24
LSB 1 2
MSB 3 22 23 24
LSB 1 2 3
MSB
LSB
MSB
LSB
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S/PDIF Input/Output
STV82x8
7
S/PDIF Input/Output
An S/PDIF output is available for connection with an external decoder/amplifier. An internal multiplexer allows selection of either the internal signal or the external signal connected on the S/ PDIF input (for example, the signal provided by the external MPEG audio / Dolby Digital decoder). The outputted internal signal can be selected from:
L/R C/Sub HP or Surround SCART
A Mute facility is also provided on the S/PDIF output.
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STV82x8
Power Supply Management
8
Power Supply Management
A mixed supply voltage environment requires the following voltages:
3.3V capable inputs/outputs for digital pins; 1.8V digital core; 8V capable inputs/outputs for analog audio interfaces (capability to output 2 VRMS for SCART requirements); 3.3V for stereo ADC and DAC (analog part); 1.8V for stereo ADC and DAC (digital part); 1.8V for IF ADC and AGC.
These voltages will be delivered by the application with an accuracy of 5%. For more information, refer to Section 16.3: Power Supply Data. Other specific DC voltages or features are provided:
Voltage Reference and Biasing Generation (AGC, ADCs, DACs), Bandgap reference.
8.1
Standby Mode (Loop-through mode)
The STV82x8 provides a Loop-through mode configuration that bypasses IC functions via a SCART I/O pin (Full Analog Path only). In this case, only a minimum power of 200 mW is required. In Standby mode, the digital and analog power supplies are switched off, except for pins VCC_H, VCC33_LS, VCC33_SC, and VCC_NISO which are used to maintain the SCART path with the last configuration programmed by analog matrixing (register SCART1_2_OUTPUT_CTRL and SCART3_OUTPUT_CTRL). When switching back to normal Full Power mode, all I²C registers are reset except for those used in Standby mode to maintain the original configuration. In Standby mode, the I²C bus does not operate. However, the bus can still be used by other ICs since the I²C I/O pins (SDA and SCL) of the STV82x8 are forced into a high-impedance configuration.
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Additional Controls and Flags
STV82x8
9
Additional Controls and Flags
This logic contains:
the headphone detection, the IRQ generation, signal to be output to the MCU, the I²C bus expander output pin.
9.1
Headphone Detection
For headphone, the HP_DET input can be used to automatically mute the Loudspeakers and Subwoofer outputs when the HP_LS_MUTE bit is set in register HEADPHONE_CONFIG (active low). When a headphone is detected (the HP_DET pin is set to 0) and the Mute function is enabled. Each change on the HP_DET pin generates an IRQ request to the microprocessor on the IRQ pin.
9.2
IRQ Generation
Four IRQs are generated by the STV82x8. On each IRQ generation, the IRQ pin is set to 1. The pending IRQ status must be read at the I²S address 81h and the acknowledge is done by writing 0 to this register. The four availables IRQs are: IRQ0: The identified TV sound standard is displayed in register AUTOSTD_STATUS. Each change in the detected standard is flagged to the host system via hardware pin IRQ. The flag must be reset by re-programming the IRQ bit in register AUTOSTD_CTRL and then checking the detected standard status by reading registers AUTOSTD_DEM_STATUS and AUTOSTD_TIME. IRQ1: This IRQ is enabled only in digital input mode. In case of I²S synchronisation loss, this IRQ is set to 1. IRQ2: This IRQ is set to 1 when the device detects any change on the HP Detection pin (Headphone connection or deconnection). IRQ3: On the STV82x8, same pins are used for both Headphone and Surround loudspeaker signal output. A change in the Headphone configuration (HP active or not active) will lead to a signal switch on those hardware pins. In order to ensure a smooth audio transition, the output is soft muted before the signal is switched. The IRQ3 is then set to 1 to advise the master processor that the signal has been switched and to request a HP/Srnd Ouput Un-Mute.
9.3
I²C Bus Expander
Pin BUS_EXP can be used to control external switchable IF SAW filters or audio switches. This pin can be directly programmed by register RESET.
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STV82x8
STV82x8 Reset
10
STV82x8 Reset
All STV82x8 features are controlled via the I²C bus. The STV82x8 can be "reset" in 2 ways: 1. By Software via the I²C bus: This clears all synchronous logic, except for the I²C bus registers. 2. By Hardware via the RESET pin: In addition to clearing all synchronous logic, the RESET input (active on the low level) resets all the I²C bus registers to the default values listed below.
Table 5: RESET Default Values Function
Demodulation Auto-standard Scanned Standards Audio Outputs Automatic Mute Mode Loudspeaker Source Loudspeaker Volume Loudspeaker L/R Balance Subwoofer Headphone Source Headphone Automatic Detection Headphone Volume Headphone L/R Balance SCART1 Output SCART2 Output SCART3 Output I²S Output (TQFP 100) ON Demodulated Sound -40 dB, Differential Mode, Muted L/R = 100% -40 dB / OFF Demodulated Sound ON -40 dB, Differential Mode, Muted L/R = 100% Demodulated Sound SCART1 Source SCART2 Source Mute OFF M/N BTSC
Default Mode
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I²C Interface
STV82x8
11
11.1
I²C Interface
I²C Address and Protocol
The STV82x8 I²C interface works in Slave mode and is fully compliant with I²C standards in Fast mode (maximum frequency of 400 kHz). Two pairs of I²C chip addresses are used to connect two STV82x8 chips to the same I²C serial bus. The device address pairs are defined by the polarity of the ADR_SEL pin and are listed in the following table:
Table 6: I²C Read/Write Addresses ADR
LOW (connected to GND1) HIGH (connected to VDD1)
Write Address (W)
80h 84h
Read Address (R)
81h 85h
Protocol Description
Write Protocol
Star t WA Sub-address A Data A .... A Data A Stop
Read Protocol
Star t WA Sub-address A Stop Star t R A Data A .... A Data N
W = Write address, R = Read address, A = Acknowledge, N = No acknowledge. Sub-address is the register address pointer; this value auto-increments for both write and read.
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STV82x8
I²C Interface
11.2
Start-up and Configuration Change Procedure
Figure 30: Flowchart
Power ON
Hardware Reset (by pin 43)
NOTE: This HW reset after Power ON is mandatory to prevent incorrect device configuration.
Clock PLLs progammation
(for oscillator values other than 27 MHz)
(Registers FS1 and FS2)
Load Patch File
(By I²C transfer)
HW_RESET bit = 1 (bit 2 in HOST_CMD register)
(DSP RUN)
INIT_MEM bit ? (bit 0 in DSP_STATUS register)
=0
(DSP inititialization)
=1
Device Configuration Set-up
(Analog or Digital)
HOST_RUN bit = 1 (bit 0 in DSP_RUN register)
(Start DSP processing)
INIT_MEM bit = 0
(Change configuration)
HOST_NO_INIT bit = 1 (bit 1 in DSP_RUN register)
(OPTIONAL)
(Registers 85h to FFh are not reset)
HOST_RUN bit = 0
(Stop DSP processing)
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Register List
STV82x8
12
Note:
Register List
The unused bits (defined as `Reserved') in the I²C registers must be kept to zero. The system clock registers (from address 08h to 0Bh and from address 5Ah to 5Dh) do not need to be modified if a standard 27 MHz crystal oscillator is used. The default values of the demodulator registers (from address 0Ch to 55h) are for optimum performances and any change is not recommended, except for:
CAROFFSET1 (22h) to compensate IF carrier frequency with an out-of-standard offset. Soundlevel Prescaling PRESCALE_DEMOD_MONO (94h), PRESCALE_DEMOD_STEREO (95h), PRESCALE_DEMOD_SAP (96h), PRESCALE_SCART (97h), PRESCALE_I2S0 (98H), PRESCALE_I2S1 (99H), PRESCALE_I2S2 (9AH) to equalize demodulated or external audio signal before audio processing. Peak detector registers PEAK_DETECTOR (9Bh), PEAK_L (9Ch), PEAK_R (9Dh), PEAK_L_R (9Eh) can be used to measure internal sound level.
Sound source selection for each audio output channel to be done using AUDIO_MATRIX1 (A2h), AUDIO_MATRIX2 (A3h) and AUDIO_MATRIX3 (A4h). Register AUTOSTD_CTRL (8Ah) is used to select the list of mono, stereo and SAP signals to be recognized automatically. Note: () used in reset value column means that the bit or the byte is read-only. (S) symbol indicates that the field value is represented in signed binary format.
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STV82x8
Register List
12.1
I²C Register Map
By default, all I²C registers controlled by Automatic Standard Recognition System (Autostandard) are forced to Read-only mode for the user. These registers and bits are shaded in Table 1.
Table 7: List of I²C Registers (Sheet 1 of 2) Name Ad. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IC General Control
CUT_ID RESET 00h 01h (0000 0001) 0000 0000 0 BUS_EXP 0
I2S_CO_EN I2 S _ D O _ E N
CUT_NUMBER[5:0] EN_STBY CLOCK_ DOWN 0 LOCK_ MODE 0 SOFT_ LRST1 SOFT_RST
I2S_CTRL I2S_STAT I2S_SYNC_OFFSET
04h 05h 06h
0000 0001 (0000 0000) (0000 0000)
I2S_PLL 0
SYNC_ SIGN 0
I2S_SRC 0
LOCK_TH[1:0] 0 0
SYNC_CST[1:0] LR_OFF LOCK_ FLAG
I2S_SFO[7:0]
Clocking 1
SYS_CONFIG FS1_DIV FS1_MD FS1_PE_H FS1_PE_L 07h 08h 09h 0Ah 0Bh 0000 1010 0001 0011 0001 0001 0011 0110 0000 0000 SYNC_PLL EN_PROG 0 OPEN_PLL 0 0 0 PE_H1[7:0] PE_L1[7:0] INPUT_FREQ[3:0] NDIV1[1:0] 0 MD1[4:0] BIT[1:0] SDIV1[2:0]
Demodulator
DEMOD_CTRL DEMOD_STAT AGC_CTRL AGC_GAIN DC_ERR_IF 0Ch 0Dh 0Eh 0Fh 10h 0000 0001 (0000 0000) 0001 0001 (0000 0000) (0000 0000) 0 0 0 0 0 0 0 0 0
IF_SELECT
0 0
0 0 AGC_REF[2:0] 0
DEMOD_MODE[2:0] FM1_CAR FM1_SQ
AGC_CST[1:0] SIG_OVER SIG_ UNDER
AGC_ERR[4:0] DC_ERR[7:0]
Demodulator Channel 1
CARFQ1H CARFQ1M CARFQ1L FIR1C0 FIR1C1 FIR1C2 FIR1C3 FIR1C4 FIR1C5 FIR1C6 FIR1C7 ACOEFF1 BCOEFF1 CRF1 CETH1 SQTH1 CAROFFSET1 CHANNEL_GAIN 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 0010 1110 1110 0000 0000 0000 0000 0001 0000 0000 1111 1110 1111 1100 0000 0000 0000 1011 0001 1001 0010 0100 0010 0010 0000 1001 (0000 0000) 0010 0000 0011 1100 0000 0000 0000 0010 0 0 0 CARFQ1[23:16] CARFQ1[15:8] CARFQ1[7:0] FIR1C0[7:0] (S) FIR1C1[7:0] (S) FIR1C2[7:0] (S) FIR1C3[7:0] (S) FIR1C4[7:0] (S) FIR1C5[7:0] (S) FIR1C6[7:0]6 (S) FIR1C7[7:0] (S) ACOEFF1[7:0] BCOEFF1[7:0] CRF1[7:0] (S) CETH1[7:0] SQTH1[7:0] CAROFFSET1[7:0] (S) 0 0 0 CH_GAIN[1:0]
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Register List
Table 7: List of I²C Registers (Sheet 2 of 2) Name
BTSC Stereo and SAP
STEREO_CONF STEREO_FSM_CONF STEREO_LEVEL_H STEREO_LEVEL_L SAP_CONF SAP_LEVEL_H SAP_LEVEL_L STE_CAR_LEVEL STE_PLL_STATUS STEREO_SAP_STATUS PLL_P_GAIN PLL_I_GAIN SAP_SQ_TH 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 00111000 00001110 0010 0 0 00010000 0 0 0000 0010 0 0 00010000 (0 0 0000) (0 0 0000) (0 0 0000) 01101100 0 0 011 00110000 0 0 0 0 0 0 OVER 0 0 0 0 LOCK_TH_STE[7:4] 0 BYPASS FSM_OFF STE_LEV_H[7:0] STE_LEV_L[7:0] 0 0 0 0 LOOP_GAIN[1:0] GAIN_INI[2:0]
STV82x8
Ad.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FREQ_PIL
RESET STE_DEM
SAP_SEL
SAP_LEV_H[7:0] SAP_LEV_L[7:0] STE_CAR_LEV[7:0] LOOP_GAIN[3:0] LOCK_DET STE_DET 0 OVER 0 LOCK_DET SQ_DET STE_DET SAP_DET
PLL_P_GAIN[7:0] 0 SAP_SQ_TH[7:0] PLL_I_GAIN[3:0]
Analog and I2S Out Control
I2S_ADC_CTRL SCART1_2_OUTPUT_CTRL SCART3_OUTPUT_CTRL I2SO_DATA_CTRL 56h 57h 58h 59h 0000 1000 1010 1000 0000 1011 0000 0000 I2S_DATA0_CTRL
SC2_MUTE
0
ADC_ POWER_UP SC1_MUTE
ADC_INPUT_SEL[2:0] SC1_OUTPUT_SEL[2:0] SC3_OUTPUT_SEL[2:0] I2SO_DATA0_CTRL
SC2_OUTPUT_SEL[2:0] 0 0 I2SO_DATA1_CTRL 0
0 0
SC3_MUTE
0
Clocking 2
FS2_DIV FS2_MD FS2_PE_H FS2_PE_L 5Ah 5Bh 5Ch 5Dh 0001 0001 0001 0001 0101 1100 0010 1001 0 0 0 NDIV2[1:0] 0 PE_H2[7:0] PE_L2[7:0] 0 MD2[4:0] SDIV2[2:0]
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STV82x8
Register List
12.2
Software Registers
Table 8: List of I²C Registers (Sheet 1 of 5) Name Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DSP Control
HOST_CMD 80h 0000 0000 IT_IN_DSP 0 0 IRQ5 (HP/Srnd unmute ready) 0 0 IRQ3 (I2S SRC input freq change) PATCH_WR HW_RESET ITE_ENABL EMUL_SW E IRQ2 (I2S sync found) IRQ1 (I2S sync lost) IRQ0 (AutoStanda rd)
IRQ_STATUS
81h
0000 0000
IRQ7
IRQ6
IRQ4 (HP detected)
FW_VERSION ONCHIP_ALGO DSP_STATUS DSP_RUN I2S_IN_CONFIG I2S_IN_SHIFT_RIGHT I2S_IN_MASK
82h 83h 84h 85h 86h 87h 88h
(0000 0001) (0000 0000) 0000 0000 0000 0000 1000 1110 0000 1000 0001 1111 0 0 0 LOCK_ MODE_EN 0 0 0 0 TEST_MOD E_INPUT RESET_I2S 0 0
SOFT_VERSION[7:0] PROLOGIC MULTI_I2S_ _TYPE IN 0 0 TRUBASS 0 TRUSURR OUND 0 PROLOGIC 0 MULTICHA NNEL_OUT INIT_MEM
TEST_MODE 0 0 0
INPUT_CONFIG
REGISTER HOST_RUN S_RESET DATA_CFG I2S_MODE
LRCLK_STA LRCLK_PO SCLK_POL RT LARITY ARITY
SHIFT_RIGHT_RANGE WORD_MASK
I2S_IN_STATUS
89h
1000 0(000)
ENABLE_IR ENABLE_IR ENABLE_IR AUTO_SRC Q_SRC_FR Q_SYNC_F Q_SYNC_L _SYNC EQ_CHANG OUND OST E
0
I2S_INPUT_FREQ
Automatic Standard Detection
AUTOSTD_CTRL AUTOSTD_TIME AUTOSTD_STATUS AUTOSTD_DEM_STATU S DMA_FORCE_OFF I2S_IN_DELAY_CONFIG 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 0000 0000 0000 1010 (0000 0000) (0000 0000) 0000 0000 0000 0111 MONO_SA SIHGLESH FORCE_SQ FORCE_SQ AUTO_MUT SAP_CHEC STEREO_C MONO_CH P_MATRIX_ OT _SAP _MONO E K HECK ECK CTRL 0 0 0 0 0 0 0 OVERFLO W 0 0 0 0 LCK_DET 0 SYNC 0 ST_DET ADC STEREO_TIME SAP_OK SAP_SQ I2S2 STEREO_ OK SAP_DET I2S1 FM_TIME MONO_OK FM1_CAR I2S0 DATA_CFG AUTOSTD_ ON FM1_SQ DEMOD I2S_MODE
LRCLK_STA LRCLK_PO SCLK_POL RT LARITY ARITY
Demodulator
BTSC_FINE_PRESCALE _ST BTSC_FINE_PRESCALE _SAP BTSC_CONTROL 90h 91h 0000 0000 0000 0000 FINE_PRES CAL_SELE CT_SAP 0 BTSC_FINE_PRESCALE_ST[7:0] (S) BTSC_FINE_PRESCALE_SAP[7:0] (S)
92h
0010 0000
DBX_DEMATRIX
DBX_ON
DEEMPHASIS_CH1
DEEMPHASIS_CH0
DCREMOVAL
93h
0011 0111
0
DEEMPHAS DBX_FILTE IS_FILTER_ R_SELECT SELECT
0
DC_DEMO DC_DEMO DC_SCART D_POST_O D_PRE_ON _ON N
Audio Preprocessing & Selection
PRESCALE_DEMOD_M ONO PRESCALE_DEMOD_ST EREO PRESCALE_DEMOD_SA P PRESCALE_SCART 94h 0000 0000 PRESCALE _DEMOD_S ELECT_SA P 0 0 0 PRESCALE_DEMOD_MONO[6:0] (S)
95h 96h 97h
0000 0000 0000 0000 0000 0000
PRESCALE_DEMOD_STEREO[6:0] (S) PRESCALE_DEMOD_SAP[6:0] (S) PRESCALE_SCART[6:0] (S)
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Register List
Table 8: List of I²C Registers (Sheet 2 of 5) Name
PRESCALE_I2S0 PRESCALE_I2S1 PRESCALE_I2S2 PEAK_DETECTOR PEAK_L PEAK_R PEAK_L_R
STV82x8
Addr.
98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh
Reset
0000 0000 0000 0000 0000 0000 0000 0000 0(000 0000) 0(000 0000) 0(000 0000)
Bit 7
0 0 0 0 OVERLOAD _L OVERLOAD _R OVERLOAD _L_R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_I2S0[6:0] (S) PRESCALE_I2S1[6:0] (S) PRESCALE_I2S2[6:0] (S) PEAK_L_R_RANGE[2:0] PEAK_DET_INPUT[2:0] PEAK_L[6:0] PEAK_R[6:0] PEAK_L_R[6:0 PEAK_DET ECTOR_ON
Matrixing
DOWNMIX_MODE DOWNMIX_DUAL_MOD E DOWNMIX_CONFIG AUDIO_MATRIX1 AUDIO_MATRIX2 AUDIO_MATRIX3 CHANNEL_MATRIX_LS 9Fh A0h A1h A2h A3h A4h A5h 0111 1111 0000 0000 0000 0001 0001 0010 0000 0010 0001 0000 0000 0010 LTRT_OUT_ MODE 0 0 0 0 0 0 0 0 0 0 0 MIX_OUT_MODE[2:0] 0 DUAL_ON LFE_IN MIX_IN_MODE[2:0] LTRT_DUAL_SELECT [1:0] LR_UPMIX LS_OUT[2:0] SCART1_OUT[2:0] DELAY_OUT[2:0] 0 CM_MATRIX_LS[2:0] NORMALIZ E
LS_DUAL_SELECT[1:0] CENTER_FACTOR[1:0]
SRND_FACTOR[1:0] HP_OUT[2:0]
SCART2_OUT[2:0] SPDIF_OUT[2:0] 0
AUTOSTD_ AUTOSTD_ CONTROL_ CONTROL_ LS SPDIF AUTOSTD_ CONTROL_ HP AUTOSTD_ CONTROL_ SCART1 AUTOSTD_ CONTROL_ SCART2
CHANNEL_MATRIX_HP
A6h
0000 0000
CM_SOURCE_HP[2:0]
CM_POSTION_HP[2:0]
CM_MATRIX_HP[2:0]
CHANNEL_MATRIX_SC ART1 CHANNEL_MATRIX_SC ART2 CHANNEL_MATRIX_SP DIF DEMOD_DC_LEVEL
A7h
0000 0000
CM_SOURCE_SCART1[ 2:0] CM_SOURCE_SCART2[ 2:0]
CM_POSTION_SCART1[ 2:0] CM_POSTION_SCART2[ 2:0] CM_POSTION_SPDIF[ 2:0] DEMOD_DC_LEVEL[7:0] (S)
CM_MATRIX_SCART1[2:0]
A8h
0000 0000
CM_MATRIX_SCART2[2:0]
A9h AAh ABh ACh
0000 0000 (0000 0000) 0000 0000 0000 0000 0 0
CM_SOURCE_SPDIF[3:0]
CM_MATRIX_SPDIF[2:0]
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Audio Processing
AV_DELAY_CONFIG AV_DELAY_TIME_LS AV_DELAY_TIME_HP PROLOGIC2_CONTROL PROLOGIC2_CONFIG PROLOGIC2_DIMENSIO N PROLOGIC2_LEVEL NOISE_GENERATOR PCM_SRND_DELAY PCM_CENTER_DELAY ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h 0000 0000 0000 0000 0000 0000 0111 0110 0000 0000 0000 0000 0000 0011 0000 0000 0000 0000 0000 0000 10_DB_ATT ENUATE 0 0 SRIGHT_ NOISE 0 0 SLEFT_ NOISE 0 0 0 PL2_LFE 0 0 0 0 0 0 0 0 DOLBY_DE AV_DELAY_ LAY_ON ON
AV_DELAY_TIME_LS[7:0] AV_DELAY_TIME_HP[7:0] PL2_OUTPUT_DOWNMIX[2:0] 0 0 PL2_MODES[2:0] PL2_RS_P OLARITY PL2_PANO RAMA PL2_ACTIV E PL2_AUTO BALANCE
PL2_SRND_FILTER[1:0] 0 PL2_LEVEL[7:0] SUB_ NOISE CENTER_ NOISE
PL2_C_WIDTH[2:0]
PL2_DIMENSION[2:0]
RIGHT_ NOISE
LEFT_ NOISE
NOISE_ON
DOLBY_DELAY_SRND[4:0] DOLBY_DELAY_CENTER[3:0]
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STV82x8
Table 8: List of I²C Registers (Sheet 3 of 5) Name
TRUSRND_CONTROL TRUSRND_DC_ELEVATI ON TRUSRND_INPUT_GAIN TRUBASS_LS_CONTRO L TRUBASS_LS_LEVEL TRUBASS_HP_CONTRO L TRUBASS_HP_LEVEL SVC_LS_CONTROL SVC_LS_TIME_TH SVC_LS_GAIN SVC_HP_CONTROL SVC_HP_TIME_TH SVC_HP_GAIN WIDESRND_CONTROL WIDESRND_FREQ WIDESRND_LEVEL OMNISRND_CONTROL DYNAMIC_BASS_LS DYNAMIC_BASS_HP
Register List
Addr.
B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h
Reset
0000 1000 0000 1100 0000 0000 0000 0110 00001 1001 0000 0110 0000 1001 0000 0010 0000 0000 0000 1111 0000 0010 0000 0000 0000 1111 0000 0100 0001 0101 1000 0000 0000 1100 0110 0010 0110 0010
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIALOG_CL HEADPHO ARITY_ON NE_ON
TRUSRND_INPUT_MODE[3:0] TRUSRND_DC_ELEVATION[7:0] TRUSRND_INPUT_GAIN[7:0]
TRUSRND_ TRUSRND_ BYPASS ON
0
0
0
0
TRUBASS_LS_SIZE[2:0]
TRUBASS_ LS_ON
TRUBASS_LS_LEVEL[7:0] SRS_TSXT _GAIN_ON 0 0 0 TRUBASS_HP_SIZE[2:0] TRUBASS_ HP_ON
TRUBASS_HP_LEVEL[7:0] 0 0 SVC_LS_TIME[2:0] 0 0 0 0 SVC_HP_TIME[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 SVC_LS_INPUT[1:0] SVC_ LS_AMP SVC_ LS_ON
SVC_LS_THRESHOLD[4:0] SVC_LS_MAKE_UP_GAIN[5:0] 0 0 SVC_ LHP_AMP SVC_ HP_ON
SVC_HP_THRESHOLD[4:0] SVC_HP_MAKE_UP_GAIN[5:0] 0 WIDESRND WIDESRND WIDESRND _STEREO _MODE _ON WIDESRND_TREBLE[ 1:0]
WIDESRND_BASS[1:0]
WIDESRND_MEDIUM[ 1:0]
WIDESRND_GAIN[7:0] ST_VOICE[1:0] SRND_PHA SE_INV LS_BASS_LEVEL[4:0] HP_BASS_LEVEL[4:0] LS_BASS_ ENHANCE_ HP_FILTER 0 0 OMNISRND_INPUT_MODE[3:0] LS_BASS_FREQ[1:0] HP_BASS_FREQ[1:0] OMNISRND _ON LS_DYN_B ASS_ON HP_DYN_B ASS_ON
BASS_ENHANCE_LS
CAh CBh
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0100 0000 0100
0 0 0
0 0 0
LS_BASS_ENHANCE_SCALE[2:0] 0 0 0 0 0
LS_BASS_ LS_BASS_ ENHANCE_ ENHANCE_ CUTOFF ON 0 0 LS_EQ_ON
EQ_BT_CONTROL LS_EQ_BAND1 LS_EQ_BAND2 LS_EQ_BAND3 LS_EQ_BAND4 LS_EQ_BAND5 LS_BASS_GAIN LS_TREBLE_GAIN HP_BASS_GAIN HP_TREBLE_GAIN OUTPUT_BASS_MNGT LS_LOUDNESS HP_LOUDNESS
CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h
LS_EQ_BT HP_BT_ON _SW
EQ_BAND1[7:0] (S) EQ_BAND2[7:0] (S) EQ_BAND3[7:0] (S) EQ_BAND4[7:0] (S) EQ_BAND5[7:0] (S) LS_BASS[7:0] (S) LS_TREBLE[7:0] (S) HP_BASS[7:0] (S) HP_TREBLE[7:0] (S) BASS_MAN ST_LFE_AD DOLBY_PR AGE_ON D OLOGIC 0 0 SUB_ ACTIVE GAIN_ SWITCH OCFG_NUM[2:0] LS_ LOUD_ON HP_ LOUD_ON
LS_LOUD_THRESHOLD[2:0] HP_LOUD_THRESHOLD[2:0]
LS_LOUD_GAIN_HR[2:0] HP_LOUD_GAIN_HR[2:0]
Volume
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Register List
Table 8: List of I²C Registers (Sheet 4 of 5) Name
VOLUME_MODES LS_L_VOLUME_MSB LS_L_VOLUME_LSB LS_R_VOLUME_MSB LS_R_VOLUME_LSB LS_C_VOLUME_MSB LS_C_VOLUME_LSB LS_SUB_VOLUME_MSB LS_SUB_VOLUME_LSB LS_SL_VOLUME_MSB LS_SL_VOLUME_LSB LS_SR_VOLUME_MSB LS_SR_VOLUME_LSB LS_MASTER_VOLUME_ MSB LS_MASTER_VOLUME_ LSB HP_L_VOLUME_MSB HP_L_VOLUME_LSB HP_R_VOLUME_MSB HP_R_VOLUME_LSB AUX_VOLUME_INDEX AUX_L_VOLUME_MSB AUX_L_VOLUME_LSB AUX_R_VOLUME_MSB AUX_R_VOLUME_LSB
STV82x8
Addr.
D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h
Reset
1101 1111 1001 1000 0000 0000 0000 0000 0000 0000 1001 1000 0000 0000 1001 1000 0000 0000 1001 1000 0000 0000 0000 0000 0000 0000 1110 1000 0000 0000 1001 1000 0000 0000 0000 0000 0000 0000 0000 0001 1101 1101 0000 0000 0000 0000 0000 0000
Bit 7
Bit 6
Bit 5
0
Bit 4
SCART2_ VOLUME_ MODE
Bit 3
SCART1_ VOLUME_ MODE
Bit 2
HP_ VOLUME_ MODE
Bit 1
SRND_ VOLUME_ MODE
Bit 0
LS_ VOLUME_ MODE
ANTCLIP_H ANTICLIP_L P_VOL_CL S_VOL_CL AMP AMP
LS_L_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_L_VOLUME_LSB[1:0]
LS_R_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_R_VOLUME_LSB[1:0]
LS_C_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_C_VOLUME_LSB[1:0]
LS_SUB_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_SUB_VOLUME_LSB[ 1:0]
LS_SL_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_SL_VOLUME_LSB[ 1:0]
LS_SR_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_SR_VOLUME_LSB[ 1:0]
LS_MASTER_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_MASTER_VOLUME_ LSB[1:0]
HP_L_VOLUME_MSB[7:0] 0 0 0 0 0 0 HP_L_VOLUME_LSB[1:0]
HP_R_VOLUME_MSB[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 HP_R_VOLUME_LSB [1:0] AUX_VOLUME_SELECT [1:0]
AUX_L_VOLUME_MSB[7:0] 0 0 0 0 0 0 AUX_L_VOLUME_LSB[ 1:0]
AUX_R_VOLUME_MSB[7:0] 0 0 0 0 0 0 AUX_R_VOLUME_LSB[ 1:0]
Mute
MUTE_SOFTWARE F1h 1111 1111 HP D_MUTE SPDIF_D_M UTE SCART2_ D_MUTE SCART1_D SRND_D_M _MUTE UTE SUB_ D_MUTE C_ D_MUTE LS_ D_MUTE
Beeper
BEEPER_ON F2h 0000 0000 0 0 0 0 0 BEEPER_SOUND_SELE CT[1:0] BEEPER_ ON
BEEPER_MODE BEEPER_FREQ_VOL
F3h F4h
0100 0011 0111 0110
BEEPER_DECAY[1:0] BEEPER_FREQ[2:0]
BEEPER_ BEEPER_DURATION[1:0] CONTINUO US
BEEPER_PATH[1:0]
BEEPER_VOLUME[4:0]
SPDIF Out Configuration
SPDIF_OUT_CHANNEL_ STATUS F5h 0000 0010 0 0 0 0 0 SPDIF_CO SPDIF_CO SPDIF_NO_ NSUMER_P PYRIGHT PCM RO
Headphone Configuration
HP_SCART2_CONFIG F6h 0000 0010 0 KARAOKE_ MIX SCART2_OUT_SELECT HP_FORCE HP_LS_ MUTE HP_DET_ ACTIVE HP_ DETECTED
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STV82x8
Table 8: List of I²C Registers (Sheet 5 of 5) Name
DAC Control
DAC_CONTROL DAC_SW_CHANNELS SPDIF_SW_CHANNELS F7h F8h F9h 0001 1111 0000 0000 0000 0000 0 0 SPDIF_ MUX
Register List
Addr.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DAC_SCAR DAC_SHP_ DAC_CSUB DAC_LSLR T_MUTE MUTE _MUTE _MUTE SCART_SW[1:0] DELAY_SW[1:0]
POWER_ UP
C_SUB_SW[1:0] 0 0
SUR_HP_SW[1:0] 0 0
SPDIF_SW[1:0] L_R_SW[1:0]
AutoStandard Coefficients Settings
AUTOSTD_FSM AUTOSTD_COEFF_CTR L AUTOSTD_COEFF_IND EX_MSB AUTOSTD_COEFF_IND EX_LSB AUTOSTD_COEFF_VAL UE PATCH_VERSION FAh FBh 0000 0000 0000 0001 0 0 0 0 0 0 0 0 0 FSM_STATE 0 AUTOSTD_COEFF_ CTRL[1:0] 0 AUTOSTD_ COEFF_IN DEX_MSB
FCh
0000 0000
0
0
0
0
0
0
FDh FEh FFh
0000 0000 0000 0000 0000 0000
AUTOSTD_COEFF_INDEX_LSB[7:0] AUTOSTD_COEFF_VALUE[7:0] PATCH_VERSION[7:0]
12.3
STV82x8 General Control Registers
CUT_ID Version Identification
Address: 00h Type: R Bit 7 0 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CUT_NUMBER[5:0]
Bit Name
Bits[7:6] CUT_NUMBER[5:0]
Reset
00 Reserved
Function
0 0 01 Dice Version Identification
RESET
Address: 01h Type: R/W Bit 7 BUS_EXP Bit 6 I2S_CO_EN Bit 5 I2S_DO_EN
Software Reset Register
Bit 4 EN_STBY
Bit 3 CLOCK_DOW N
Bit 2 0
Bit 1 SOFT_LRST1
Bit 0 SOFT_RST
Description The built-in Automatic Standard Recognition System (Autostandard) can be disabled. In this case, the Software Reset function (bits SOFT_LRST1 and SOFT_LRST2) can be used to implement the
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Register List
STV82x8
Automatic Standard Recognition by I²C Software. This is not required if the built-in Automatic Standard Recognition System function is used (default).
Bit Name
BUS_EXP I²2S_CO_EN I²2S_DO_EN EN_STBY
Reset
0 0 0 0
Function
Static control by I2C of hardware pin BUS_EXP 0 = I²2S Input (I2S_SCK , I2S_LR_CLK, I2S_PCM_CLK in input mode) 1 = I²2S Output (I2S_SCK , I2S_LR_CLK, I2S_PCM_CLK in output mode) 0 = I²2S Input (I2S_DATA0 in input mode) 1 = I²2S Output (I2S_DATA0 in output mode) Standby mode enabling 0: Normal mode 1: To lock the digital signals before to settle the device in standby mode
CLOCK_DOWN Bit [2] SOFT_LRST1 SOFTR_RST
0 0 0 0
clock down of the dsp, decoder. Reserved Softreset (active high) of Decoder.. General softreset (active high) to reset all hardware registers except for I²2C data.
I2S_CTRL
Address: 04h Type: R/W Bit 7 I2S_PLL Bit 6 SYNC_SIGN Bit 5 I2S_SRC
I²S Synchronization Control Register
Bit 4
Bit 3
Bit 2 LOCK_MODE
Bit 1
Bit 0
LOCK_TH[1:0]
SYNC_CST[1:0]
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STV82x8
Register List
Bit Name
I2S_PLL
Reset
0
Function
Selects the i2s source for the synchronization with the synthesizer (at 48KHz only) 0: I2S_LR_CLK selected 1: I2SA_LR_CLK selected
SYNC_SIGN I2S_SRC
0 0
Reverse the sign of the loop - To be used in case of gain inversion of the Frequency Synthesizer Selects the i2s source for the src 0: I2S_LR_CLK selected 1: I2SA_LR_CLK selected
LOCK_TH[1:0]
00
Lock Detector Threshold Programming 00: 1 CLK period error of accumulation 01: 2 CLK period error of accumulation 10: 4 CLK period error of accumulation 11: 8 CLK period error of accumulation
LOCK_MODE
0
Lock Detector Mode 0: Lock when accumulation error within lock threshold and LR detected (period counter not saturated) 1: Lock when only accumulation error within lock threshold. Don't care of the LR detection
SYNC_CST[1:0]
00
Synchronization Time Constant Defines the measurement period of LR 00: Half period measured (lowest accuracy) 01: One full period measured 10: Two full periods measured 11: Four full periods measured (highest accuracy)
I2S_STAT
Address: 05h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
I²S Synchronization Status Register
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 LR_OFF
Bit 0 LOCK_FLAG
Bit Name
Bits[7:2] LR_OFF
Reset
0 0 Reserved. LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected
Function
LOCK_FLAG
0
Lock Flag allowing unmute of Audio Output
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Register List I2S_SYNC_OFFSET
Address: 06h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82x8 I²S Synchronization Offset Frequency Register
Bit 0
I2S_SFO[7:0]
Bit Name
I2S_SFO[7:0]
Reset
0000 0000
Function
I²S synchronization frequency offset (450 ppm full scale)
12.4
Clocking 1
A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described below. By default, the programming is defined for a 27-MHz crystal oscillator, which is the frequency recommended for reducing potential RF interference in the application. However, if necessary, the PLL Clock can be re-programmed for other crystal oscillator frequencies within a range from 23 to 30 MHz. Other crystal frequencies can be programmed on your demand.
Note:
A Crystal Frequency change is compatible with other default I²C programming including the built-in Automatic Standard Recognition System.
SYS_CONFIG
Address: 07h Type: R/W Bit 7 SYNC_PLL Bit 6 OPEN_PLL Bit 5
System Configuration Control Register
Bit 4
Bit 3
Bit 2
Bit 1 BIT[1:0]
Bit 0
INPUT_FREQ[3:0]
Bit Name
SYNC_PLL
Reset
0 Status of the loop wyth the synthesizer 0: Open 1: Closed
Function
OPEN_PLL
0
Force the loop with the synthesizer to be open 0: No Action 1: Loop Open
INPUT_FREQ[3:0]
0010
I2S Input frequency 0010: 48 kHz
BIT[1:0]
10
Reserved
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STV82x8 FS1_DIV
Address: 08h Type: R/W Bit 7 EN_PROG Bit 6 0 Bit 5 NDIV1[1:0] Bit 4 Bit 3 0 Bit 2 Bit 1 SDIV1[2:0]
Register List FS1 I/O Divider Programming Register
Bit 0
Bit Name
EN_PROG
Reset
0 FS1 programmation enable
Function
0: FS1 I2C registers programmation ignored by system - FS1 pre-programmed automatically by SYS-CONFIG register (normal use with standard oscillator of 27 MHz) 1: FS1 I2C registers programmation used by system - FS1 pre-programmation by SYS-CONFIG desactivated (to be used in case of no standard oscillator, other than 27 MHz) Bit 6 NDIV1[1:0] Bit 3 SDIV1[2:0] 0 01 0 011 Reserved. FS1 Input clock divider selection Reserved. FS1 Output clock divider selection
FS1_MD
Address: 09h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
FS1 Coarse Selection Register
Bit 4
Bit 3
Bit 2 MD1[4:0]
Bit 1
Bit 0
Bit Name
Bits[7:5] MD1[4:0]
Reset
000 10001 Reserved. FS1 Coarse Selection
Function
FS1_PE_H
Address: 0Ah Type: R/W Bit 7 Bit 6 Bit 5
FS1 Fine Selection Register (MSBs)
Bit 4 PE_H1[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
PE_H1[7:0]
Reset
0011 0110 FS1 Fine Selection (MSBs)
Function
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Register List FS1_PE_L
Address: 0Bh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 PE_L1[7:0] Bit 3 Bit 2 Bit 1
STV82x8 FS1 Fine Selection Register (LSBs)
Bit 0
Bit Name
PE_L1[7:0]
Reset
0000 0000 FS1 Fine Selection (LSBs)
Function
12.5
Demodulator
DEMOD_CTRL Demodulator Control Register
Address: 0Ch Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 DEMOD_MODE[2:0] Bit 0
Bit Name
Bits [7:3] DEMOD_MODE[ 2:0]
Reset
0 0 0 001 Reserved Demodulator Mode Select Demod FM 000: 001: Normal Wide
Function
other configuration: Reserved
DEMOD_STAT
Address: 0Dh Type: R Bit 7 0 Bit 6 0 Bit 5 0
Demodulator Detection Status Register
Bit 4
Bit 3
Bit 2
Bit 1 FM1_CAR
Bit 0 FM1_SQ
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STV82x8
Register List
Bit Name
Bits [7:2] FM1_CAR
Reset
000 0 Reserved. Channel 1 FM Carrier Detector Flag 0: Not detected 1: Detected
Function
FM1_SQ
0
Channel 1 FM Squelch Detector Flag 0: Not detected 1: Detected
Note:
These registers allow direct access to the demodulator signal detectors.
AGC_CTRL
Address: 0Eh Type: R/W Bit 7 0 Bit 6 0 Bit 5 IF_SELECT
IF AGC Control Register
Bit 4
Bit 3 AGC_REF[2:0]
Bit 2
Bit 1
Bit 0
AGC_CST[1:0]
Bit Name
Bits[7:5] IF_SELECT
Reset
00 0 Reserved. Selection of the IF input. 0: IF input SIF 1 1: IF input SIF 2
Function
AGC_REF[2:0]
100
This bitfield is used to defines the clipping level which adjusts the allowable proportion of samples at the input of the ADC which will be clipped. The AGC tries to maximize the use of the full scale range of the ADC. The default setting gives a ratio of 1/256. Clipping Ratio 000: 001: 010: 011: 1/16 (Single carrier) 1/32 1/64 1/128 100: 101: 110: 111: Clipping Ratio 1/256 (Default) 1/512 1/1024 1/2048 (Multiple carriers)
AGC_CST[1:0]
01
AGC Time Constant This is the time constant between each step of 1.5 dB by the AGC. Step Duration (ms) 00 01 10 11 1.33 2.66 5.33 10.66
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Register List AGC_GAIN
Address: 0Fh Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 AGC_ERR[4:0] Bit 3 Bit 2 Bit 1 SIG_OVER
STV82x8 IF AGC Control and Status Register
Bit 0 SIG_UNDER
Bit Name
Bit 7 AGC_ERR[4:0]
Reset
0 0 0 0 Reserved. Amplifier Gain Control
Function
This is the Gain Control value of AGC. There are 20 steps of +1.5 dB (see Note below). 0 0 0: Gain-min 10100: Gain-min + 30 dB 11111: Gain-min + 30 dB SIG_OVER 0 AGC Input SIgnal Upper Threshold 0: Normal signal 1: Signal too large and AGC is overloaded SIG_UNDER 0 AGC Input SIgnal Lower Threshold 0: Normal signal 1: Signal too small and AGC is underloaded When the AGC is in Automatic mode (AGC_CMD = 0), bits SIG_OVER and SIG_UNDER indicate if the input signal is too small/large and the AGC is under/overloaded. This is useful when setting the STV82x7 SIF input level.
Note:
When AGC_CMD = 0, AGC_ERR[4:0] can be read -- indicating the input level. It can also be written to -- presetting the AGC level which will then adjust itself to the final value. When AGC_CMD = 1, the AGC is off and writing to AGC_ERR[4:0] directly controls the AGC amplifier gain. Reading AGC_ERR just confirms the fixed value.
DC_ERR_IF
Address: 10h Type: R Bit 7 Bit 6 Bit 5
DC Offset Status for IF ADC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DC_ERR[7:0]
Bit Name
DC_ERR[7:0]
Reset
0 0 0000 DC offset error of IF ADC output
Function
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STV82x8
Register List
12.6
Demodulator Channel 1
CARFQ1H, CARFQ1M, CARFQ1L Channel 1 Carrier DCO Frequency
Address: 12h to 14h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CARFQ1[23:16], CARFQ1[15:8], CARFQ1[7:0]
Bit Name
CARFQ1[23:16] CARFQ1[15:8] CARFQ1[7:0]
Reset
00101110 1110 0 0 0 0 0000
Function
Channel 1 DCO Carrier Frequency (8 MSBs) Channel 1 DCO Carrier Frequency Channel 1 DCO Carrier Frequency (8 LSBs), see Table 2.
Table 9: Mono Carrier Frequencies by System System
M/N
Mono Carrier Freq. (MHz)
4.5
CARFQ1[23:0] (dec)
3072000
CARFQ1[23:0]
2EE000h
Note:
Carrier Freq: CARFQ1(dec).fS / 224 with fS = 24.576 MHz (crystal oscillator frequency independent)
FIR1C[0:7]
Address: 15h to 1Ch Type: R/W Bit 7 Bit 6 Bit 5
Channel 1 FIR Coefficients
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FIR1C0[7:0] to FIR1C7[7:0]
Description Bitfield
(reset state) FM 27 kHz FIR1C0[7:0] FIR1C1[7:0] FIR1C2[7:0] FIR1C3[7:0] FIR1C4[7:0] FIR1C5[7:0] FIR1C6[7:0] FFh FEh FEh 00h 06h 0Eh 16h FM 50 kHz 00h FEh FCh FDh 02h 0Dh 18h FM 200 kHz 00h 01h 01h FCh 08h F6h F8h FM 350 kHz 02h 01h FCh 03h 04h F2h 06h FM 500 kHz 01h 00h 04h FAh 05h 00h F2h BTSC 01h 00h FEh FCh 00h 0Bh 19h
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Register List
STV82x8
Description Bitfield
(reset state) FM 27 kHz FIR1C7[7:0] 1Bh FM 50 kHz 1Fh FM 200 kHz 4Ah FM 350 kHz 43h FM 500 kHz 4Dh BTSC 24h
ACOEFF1
Channel 1 Baseband PLL Loop Filter Proportional Coefficient
Address: 1Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ACOEFF1[7:0]
Bit Name
ACOEFF1[7:0]
Reset
00100010
Function
Used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 1) Defines the damping factor of the loop. For values, refer to Table 3.
BCOEFF1
Channel 1 Baseband PLL Loop Filter Integral Coefficient & DCO Gain
Address: 1Eh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BCOEFF1[7:0]
Bit Name
BCOEFF1[7:0]
Reset
00001001
Function
Used to program the Integral Coefficient of the baseband PLL loop filter and DCO gain Defines the bandwidth of the loop. For values, refer to Table 3.
Table 10: Baseband PLL Loop Filter Adjustment (FM Mode) FM Mode
ACOEFF BCOEFF FM_DEV max (kHz) DCO Range (kHz)
Small
10h 1Ah 62.5 96
Standard
22h 12h 125 192
Medium
2Ch 0Ah 250 384
Wide*
2Ch 0Ah 500 768
BTSC
22h 09h 500 768
(*)
Refer to DEMOD_CTRL (DEMOD_MODE[2:0])
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STV82x8 CRF1
Address: 1Fh Type: R Bit 7 Bit 6 Bit 5 Bit 4 CRF1[7:0] Bit 3 Bit 2 Bit 1
Register List Channel 1 Baseband PLL Demodulator Offset
Bit 0
Bit Name
CRF1[7:0]
Reset
(0 0 0000) Channel 1 Carrier Recovery Frequency
Function
Displays the instantaneous frequency offset of the Channel 1 Baseband PLL Demodulator.
CETH1
Address: 20h Type: R/W Bit 7 Bit 6 Bit 5
Channel 1 FM Carrier Level Threshold
Bit 4 CETH1[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
CETH1[7:0]
Reset
0010 0 0
Function
This register is used to compare the carrier level in the channel and the threshold value. This level is measured after the channel filter and is relative to the full scale reference level (0 dB). This is used as part of the validation of an FM signal, if the carrier level is below the threshold, the signal is considered to be non-valid. Recommended value is 10h. CETH FFh 80h 40h 20h Threshold (dB) -6 -12 -18 -24 (Default) CETH 10h 08h 00h Threshold (dB) -32 (Recommended Value) -38 OFF (all carrier levels are accepted)
SQTH1
Address: 21h Type: R/W Bit 7 Bit 6 Bit 5
Channel 1 FM Squelch Threshold Register
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SQTH1[7:0]
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Register List
STV82x8
Bit Name
SQTH1[7:0]
Reset
00111100
Function
The squelch detector measures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is below this value, the S/N of the FM signal is considered to be acceptable. Values are given for FM with standard deviation. SQTH FAh 77h 3Ch 23h 19h S/N (dB) 0 10 15 (Default) 20 25
CAROFFSET1
Address: 22h Type: R/W Bit 7 Bit 6 Bit 5
Channel 1 DCO Carrier Offset Compensation
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CAROFFSET1[7:0] (S)
Bit Name
CAROFFSET1[7:0]
Reset
0 0 0000
Function
This value is used to correct the carrier frequency offset of the incoming IF signal. Automatic frequency control in FM mode can be implemented by registers DC_REMOVAL_L and DC_REMOVAL_R. A DCO frequency offset (in two's complement format) is added to the pre-programming value by AUTOTSD in the CARFQ1 registers (corresponding to the standard IF carrier frequency). The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of 1.5 kHz. For standard FM deviation, the value displays by DC_REMOVAL_L and DC_REMOVAL_R can be directly loaded in CAROFFSET1 to exactly compensate the carrier offset on Channel 1
CHANNEL_GAIN
Address:45h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Demodulator channel gain
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
CH_GAIN[1:0]
Bit Name
Bits[7:2]
Reset
0 0 00 Reserved.
Function
Channel 1 Gain after the FM Demodulation CH_GAIN[1:0] 10 00: Gain 10: Gain*4 (Default) 01: Gain * 2 11: Gain *8
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STV82x8 STEREO_CONF
Address:43h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 FREQ_PIL
Register List BTSC Stereo Configuration
Bit 0 RESET
LOCK_TH_STE[7:4]
LOOP_GAIN[1:0]
Bit Name
LOCK_TH_STE[ 7:4]
Reset
0011 10 BTSC Lock Stereo Threshold Gain of Stereo PLL 00: Gain * 4 10: Gain (Default) 0 Pilot Frequency Selection 0: 15.625-15.734 kHz 0 Stereo Reset 1: Reset Active
Function
LOOP_GAIN[1:0]
01: Gain * 2 11: Gain / 2
FREQ_PIL
1: Reserved
RESET
STEREO_FSM_CONF
Address:44h Type: R/W Bit 7 0 Bit 6 0 Bit 5 BYPASS
BTSC Finite State Machine Configuration
Bit 4 FSM_OFF
Bit 3
Bit 2 GAIN_INI[2:0]
Bit 1
Bit 0 STE_DEM
Bit Name
BIT[7:6] BYPASS
Reset
00 0 Reserved. Bypass of the Stereo Block 0: Stereo Block is On 0 FSM Switch Off 0: FSM is On 111 0 Initial loop gain for FSM
Function
1: Stereo Block is Bypassed
FSM_OFF GAIN_INI[2:0] STE_DEM
1: FSM is Off. Gain set by I²C
Stereo dematrix inside the stereo block (before DBX) 1: reset active
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Register List STEREO_LEVEL_H
Address:45h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82x8 BTSC Threshold High for Stereo Detection
Bit 0
STE_LEV_H[7:0]
Bit Name
STE_LEV_H[7:0]
Reset
00100011 Threshold High for Stereo Detection
Function
If carrier level is > STE_LEV_H, stereo is detected
STEREO_LEVEL_L
Address:46h Type: R/W Bit 7 Bit 6 Bit 5
BTSC Threshold Low for Stereo Detection
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STE_LEV_L[7:0]
Bit Name
STE_LEV_L[7:0]
Reset
00001100 Threshold Low for Stereo Detection
Function
If carrier level is
SAP_CONF
Address:47h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
BTSC SAP Selection
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 SAP_SEL
Bit Name
bit[7:1] SAP_SEL
Reset
0 0 000 0 Reserved. Selection of the SAP 0: Stereo selected
Function
1: SAP is selected on second channel
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STV82x8 SAP_LEVEL_H
Address:48h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List BTSC Threshold High for SAP Detection
Bit 0
SAP_LEV_H[7:0]
Bit Name
SAP_LEV_H[7:0]
Reset
01010000 Threshold high for SAP detection
Function
If SAP signal level is > SAP_LEV_H, SAP is detected
SAP_LEVEL_L
Address:49h Type: R/W Bit 7 Bit 6 Bit 5
BTSC Threshold Low for SAP Detection
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SAP_LEV_L[7:0]
Bit Name
SAP_LEV_L[7:0]
Reset
00110000 Threshold low for SAP detection
Function
If sap signal level is
STE_CAR_LEV
Address:4Ah Type: R Bit 7 Bit 6 Bit 5
BTSC Stereo Carrier Level
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STE_CAR_LEV[7:0]
Bit Name
STE_CAR_LEV[7:0]
Reset
0 0 0000 Stereo carrier level
Function
STE_PLL_STAT
Address:4Bh Type: R Bit 7 0 Bit 6 0 Bit 5
BTSC Stereo PLL Status
Bit 4 LOOP_GAIN[3:0]
Bit 3
Bit 2 OVER
Bit 1 LOCK_DET
Bit 0 STE_DET
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Register List
STV82x8
Bit Name
Bits[7:6] LOOP_GAIN[3:0] OVER
Reset
00 000 0 Reserved.
Function
Final FSM gain at the end of the stereo search process Overflow append in stereo search process 1: overflow
LOCK_DET
0
Stereo PLL lock status 0: no lock on pilot 1: lock on pilot or no pilot detected (no stereo)
STE_DET
0
Stereo Detection 0: no stereo dectected 1: stereo detected
STE_SAP_STAT
Address:4Ch Type: R Bit 7 0 Bit 6 OVER Bit 5 LOCK_DET
BTSC Stereo SAP Status
Bit 4 STE_DET
Bit 3 0
Bit 2 0
Bit 1 SQ_DET
Bit 0 SAP_DET
Bit Name
Bit 7 OVER
Reset
0 0 Reserved.
Function
Overflow append in stereo search process 1: overflow
LOCK_DET
0
Stereo PLL lock status 0: no lock on pilot 1: lock on pilot or no pilot detected (no stereo)
STE_DET bit[3:2] SQ_DET
0
Stereo detection 0: no stereo dectected 1: stereo detected
00 0
Reserved. Squelch detection of SAP 0: problem of noise 1: level of noise is good
SAP_DET
0
Signal detection of SAP 0: SAP not detected 1: SAP detected
PLL_P_G
Address:4Dh Type: R/W Bit 7 Bit 6 Bit 5
BTSC PLL Proportionnal Gain
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL_P_G[7:0]
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STV82x8
Register List
Bit Name
PLL_P_G[7:0]
Reset
01101100 PLL Proportional Gain
Function
PLL_I_G
Address:4Eh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
BTSC PLL Integral Gain
Bit 4 0
Bit 3
Bit 2
Bit 1
Bit 0
PLL_I_G[3:0]
Bit Name
Bits [7:4] PLL_I_G[3:0]
Reset
0000 0011 Reserved. PLL integral Gain
Function
SAP_SQ_TH
Address:4Fh Type: R/W Bit 7 Bit 6 Bit 5
SAP Squelch Threshold
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SAP_SQ_TH[7:0]
Bit Name
SAP_SQ_TH[7:0]
Reset
00110000 SAP squelch threshold
Function
12.7
I2S and Analog Control
I2S_ADC_CTRL I2S_DATA0 and ADC Input Selection and Power-up
Address: 56h Type: R/W Bit 7 Bit 6 I2S_DATA0_CTRL[2:0] Bit 5 Bit 4 0 Bit 3 ADC_ POWER_UP Bit 2 Bit 1 ADC_INPUT_SEL[2:0] Bit 0
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Register List
STV82x8
Bit Name
Reset
Source selection for output I2S_DATA0
Function
I2S_DATA0_CTRL[ 2:0]
000
000: LR 001: HP_LSS 010: LS_C and LS_SUB 011: SCART DAC Reserved.
100: S/PDIF_OUT 101: DELAY 110: reserved 111: reserved
Bit[4]
0
Control of the power up of the Audio ADC ADC_POWER_UP 1 0: ADC in power down mode 1: Wake up of the ADC Selection of the ADC input signal ADC_INPUT_SEL [2:0] 000 000: Input SCART 1 (Default) (B SDIP64)100: Input Mono 001: Input SCART 2 (res. SDIP 64) 101: Input SCART (res. TQFP) (A SDIP64) (1_BIS) 010: Input SCART 3 (res. SDIP 64) 110: Input SCART (5 TQFP100) (C SDIP64) (3_BIS) 011: Input SCART 4 (res. SDIP 64) 111: reserved (mute)
SCART1_2_OUTPUT_CTRL
Address: 57h Type: R/W Bit 7 SC2_MUTE Bit 6 Bit 5 SC2_OUTPUT_SEL[2:0]
SCART 1_2 Input Selection and Mute
Bit 4
Bit 3 SC1_MUTE
Bit 2
Bit 1 SC1_OUTPUT_SEL[2:0]
Bit 0
Bit Name
SC2_MUTE
Reset
Mute command for the output SCART 2 1 0: output not muted 1: output muted
Function
Selection of the output SCART 2 configuration: SC2_OUTPUT_ SEL[2:0] 010 000: DSP 001: Input Mono 010: Input SCART 1 (Def) (B SDIP 64) 011: Input SCART 2 (res. SDIP 64) 100: Input SCART 3 (res. SDIP 64) 101: Input SCART 4 (res. SDIP 64) 110: Input SCART (res. TQFP) (A SDIP 64) (1_BIS) 111: Input SCART (5 TQFP 100) (C SDIP 64) (3_BIS)
Mute command for the output SCART 1 SC1_MUTE 1 0: output not muted 1: output muted Selection of the output SCART 1 configuration: 000 000: DSP (Default) 001: Input Mono 010: Input SCART 1 (B SDIP 64) 011: Input SCART 2 (res SDIP 64) 100: Input SCART 3 (res. SDIP 64) 101: Input SCART 4 (res. SDIP 64) 110: Input SCART (res. TQFP) (A SDIP 64) (1_BIS) 111: Input SCART (5 TQFP100) (C SDIP64) (3_BIS)
SC1_OUTPUT_ SEL[2:0]
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STV82x8 SCART3_OUTPUT_CTRL
Address: 58h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 SC3_MUTE Bit 2 Bit 1
Register List SCART 3 Input Selection and Mute
Bit 0
SC3_OUTPUT_SEL[2:0]
Bit Name
Bits[7:4]
Reset
0000 Reserved. Mute command for the output SCART 3
Function
SC3_MUTE
1
0: output not muted 1: output muted Selection of the output SCART 3 configuration:
SC3_OUTPUT_SE L[2:0] 011
000: DSP 100: Input SCART 3 (res. SDIP 64) 001: Input Mono 101: Input SCART 4 (res. SDIP 64) 010: Input SCART 1 (B SDIP) 110: Input SCART (res. TQFP) (A SDIP64) (1_BIS) 011: Input SCART 2 (Default) (res. SDIP 64)111: Input SCART (5 TQFP 100) (C SDIP 64) (3_BIS)
I2SO_DATA_CTRL
Address: 59h Type: R/W Bit 7 0 Bit 6 Bit 5 I2SO_DATA1_CTRL[2:0]
I2S Data Source Control
Bit 4
Bit 3 0
Bit 2
Bit 1 I2SO_DATA0_CTRL[2:0]
Bit 0
Bit Name
Bit [7]
Reset
0 000 Reserved.
Function
Source Selection for I2SO_DATA1 Output 000: Mute 001: LR 010: HP_LSS 011: LS_C and LS_SUB 100: SCART DAC 101: S/PDIF_OUT 110: Delay 111: Mute
I2SO_DATA1_CTRL [2:0]
Bit [3]
0 000
Reserved. Source Selection for I2SO_DATA0 Output 000: Mute 001: LR 010: HP_LSS 011: LS_C and LS_SUB 100: SCART DAC 101: S/PDIF_OUT 110: Delay 111: Mute
I2SO_DATA0_CTRL [2:0]
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Register List
STV82x8
12.8
Clocking 2
FS2_DIV FS2 I/O Divider Programming Register
Address: 5Ah Type: R/W Bit 7 0 Bit 6 0 Bit 5 NDIV2[1:0] Bit 4 Bit 3 Bit 2 Bit 1 SDIV2[2:0] Bit 0
Bit Name
Bit [7:6] NDIV2[1:0] Bit 4 SDIV2[2:0]
Reset
0 01 0 001 Reserved. FS2 Input clock divider selection Reserved. FS2 Output clock divider selection
Function
FS2_MD
Address: 5Bh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
FS2 Coarse Selection Register
Bit 4
Bit 3
Bit 2 MD2[4:0]
Bit 1
Bit 0
Bit Name
Bits[7:5] MD2[4:0]
Reset
000 10001 Reserved. FS2 Coarse Selection
Function
FS2_PE_H
Address: 5Ch Type: R/W Bit 7 Bit 6 Bit 5
FS2 Fine Selection Register (MSBs)
Bit 4 PE_H2[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
PE_H2[7:0]
Reset
0101 1100 FS2 Fine Selection (MSBs)
Function
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STV82x8 FS2_PE_L
Address: 5Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 PE_L2[7:0] Bit 3 Bit 2 Bit 1
Register List FS2 Fine Selection Register (LSBs)
Bit 0
Bit Name
PE_L2[7:0]
Reset
0010 1001 FS2 Fine Selection (LSBs)
Function
12.9
DSP Control
HOST_CMD DSP Hardware Control
Address: 80h Type: R/W Bit 7 IT_IN_DSP Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 HW_RESET Bit 1 PATCH_WRIT E_ENABLE Bit 0 EMUL_SW
Bit Name
IT_IN_DSP Bits[6:3] HW_RESET Bits[1:0]
Reset
0 0000 0 00 Valid I2C table. Reserved. DSP Hardware reset when set. Reserved.
Function
IRQ_STATUS
Address: 81h Type: R/W Bit 7 IRQ7 Bit 6 IRQ6 Bit 5 IRQ5
IRQ Status
Bit 4 IRQ4
Bit 3 IRQ3
Bit 2 IRQ2
Bit 1 IRQ1
Bit 0 IRQ0
Bit Name
Bits[7:6] IRQ5 IRQ4
Reset
00 0 0 Reserved. Hp/Srnd DAC unmute ready HP detected
Function
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Register List
STV82x8
Bit Name
IRQ3 IRQ2 IRQ1 IRQ0
Reset
0 0 0 0 I2S SRC freq change detected I2S sync found IRQ I2S sync lost IRQ Auto-Standard IRQ
Function
FW_VERSION
Address: 82h Type: R Bit 7 Bit 6 Bit 5
Embedded Firmware Version
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FW_VERSION[7:0]
Bit Name
SOFT_VERSION [7:0]
Reset
0000 0011 Version of the Embedded software.
Function
ONCHIP_ALGOS
Address: 83h Type: R Bit 7 0 Bit 6 0 Bit 5
Display Algorithms available on the chip
Bit 4
Bit 3 TRUBASS
Bit 2 TRU SURROUND
Bit 1 PROLOGIC
Bit 0 MULTICHANN EL_OUT
PROLOGIC_T MULTI_I2S_IN YPE
Bit Name
Bits[7:6] PROLOGIC_TYPE MULTI_I2S_IN TRUBASS TRUSURROUND PROLOGIC MULTICHANNEL_O UT
Reset
00 0 0 0 0 0 0 Reserved. 0: ProLogic 1 1: ProLogic 2 0: 1 I2S input 1: 3 I2S inputs
Function
SRS TruBass algorithm is present when set. SRS TruSurround algorithm is present when set. Dolby Pro Logic algorithm is present when set. Multi-Channel output is present when set.
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STV82x8 DSP_STATUS
Address: 84h Type: R Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0
Register List DSP Status
Bit 0 INIT_MEM
Bit Name
Bits[7:1]
Reset
0 0 000 Reserved. DSP Initialization
Function
INIT_MEM
0
0: 1:
DSP is not initialized. DSP is initialized.
DSP_RUN
Address: 85h Type: R/W Bit 7 0 Bit 6 TEST_MODE_ INPUT Bit 5
DSP Configuration and Run
Bit 4
Bit 3
Bit 2
Bit 1 REGISTERS_ RESET
Bit 0 HOST_RUN
TEST_MODE
INPUT_CONFIG
Bit Name
Bits[7]
Reset
0 Reserved.
Function
active in TEST_MODE = 1 (bypass processing) 0: TEST_MODE_INP UT I2S_0 input -> L/R output I2S_1 input -> C/LFE output I2S_2 input -> Ls/Rs output I2S_0 input -> SCART out |
