L6743, L6743Q
High current MOSFET driver
Data Brief
Features
Dual MOSFET driver for synchronous rectified converters High driving current for fast external MOSFET switching Integrated bootstrap diode High frequency operation Enable pin Adaptive dead-time management Flexible gate-drive: 5V to 12V compatible High-impedance (HiZ) Management for output stage shutdown Preliminary OV protection SO8 and DFN10 3x3 Package Combined with ST PWM Controllers, the driver allows implementing complete voltage regulator solutions for modern high-current CPUs and DCDC conversion in general. L6743, L6743Q embeds high-current drivers for both high-side and low-side MOSFETs. The device accepts flexible power supply (5V to 12V) to optimize the gatedrive voltage for High-Side and Low-Side maximizing the System Efficiency. The Bootstrap diode is embedded saving the use of external diodes. Anti shoot-through management avoids high-side and low-side MOSFET to conduct simultaneously and, combined with Adaptive Dead-Time control, minimizes the LS body diode conduction time. L6743, L6743Q embeds Preliminary OV Protection: after Vcc overcomes the UVLO and while the device is in HiZ, the LS MOSFET is turned ON to protect the load in case the output voltage overcomes a warning threshold protecting the output against HS failures. The driver is available is SO8 and DFN10 3x3 packages.
SO8, DFN10 3x3
Applications
High current VRM / VRD for Desktop / Server / Workstation CPUs High current and high efficiency DC / DC Converters
Description
L6743, L6743Q is a flexible, high-frequency dualdriver specifically designed to drive N-Channel MOSFETs connected in Synchronous-Rectified Buck topology.
Table 1.
Device summary
Part Number L6743 L6743TR L6743Q L6743QTR Package SO8 SO8 DFN10 DFN10 Rev 1 Packaging Tube Tape & Reel Tube Tape & Reel 1/8
www.st.com 8
March 2007
For further information contact your local STMicroelectronics sales office.
Typical application circuit and block diagram
L6743, L6743Q
1
1.1
Typical application circuit and block diagram
Application circuit
Figure 1. Typical application circuit
VCC = 5V to 12V CDEC VCC BOOT CHF PWM Input CBULK
VIN = 5V to 12V
L6743
PWM
UGATE
HS L Vout
EN Input
EN
PHASE
GND NC*
L6743 Reference Schematic
LGATE NC*
LS
COUT
1.2
Block diagram
Figure 2. Block diagram
OD VCC
ADAPTIVE ANTI CROSS CONDUCTION HS
BOOT UGATE PHASE
VCC
L6743
PWM
CONTROL LOGIC & PROTECTIONS PWM
LS
LGATE
GND
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L6743, L6743Q
Pins description and connection diagrams
2
Pins description and connection diagrams
Figure 3. Pins connection (Top view)
1 2 3 4 8
BOOT PWM EN VCC
L6743
7 6 5
UGATE PHASE GND LGATE
BOOT PWM EN VCC VCC
1 2 3 4 5
10 9
L6743Q
8 7 6
UGATE PHASE GND GND LGATE
2.1
Table 2.
Pin #
Pin description
Pins descriptions
Name Function High-Side Driver Supply. This pin supplies the High-Side floating driver. Connect through a RBOOT - CBOOT capacitor to the PHASE pin. Internally connected to the cathode of the integrated Bootstrap diode. Control input for the driver, 5V compatible. This pin controls the state of the driver and which external MOSFET have to be turned-ON according to EN status. If left floating and in conjunction with EN asserted, it causes the driver to enter the High-Impedance (HiZ) state which causes all MOSFETs to be OFF. Enable Input for the Driver. Pull High to enable the driver according to the PWM status. If pulled low will cause the drive to enter HiZ state with all MOSFET OFF regardless of the PWM status. Device and LS Driver power supply. Connect to any voltage between 5V and 12V. Bypass with low-ESR MLCC capacitor to GND. Low-Side Driver Output. Connect directly to the Low-Side MOSFET gate. A small series resistor can be useful to reduce dissipated power especially in high frequency applications. All internal references, logic and drivers are referenced to this pin. Connect to the PCB ground plane. High-Side Driver return Path. Connect to the High-Side MOSFET Source. This pin is also monitored for the adaptive dead-time management and Pre-OV Protection. High-Side Driver Output. Connect to High-Side MOSFET gate. Thermal pad connects the Silicon substrate and makes good thermal contact with the PCB. Connect to the PGND plane. (DFN10 only)
SO8
DFN10
1
1
BOOT
2
2
PWM
3
3
EN
4, 5
4
VCC
6
5
LGATE
7, 8
6
GND
9
7
PHASE
10 PAD
8 -
UGATE TH. PAD
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Package mechanical data
L6743, L6743Q
3
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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L6743, L6743Q
Package mechanical data
Table 3.
Dim.
SO8 Mechanical data
mm. Min Typ Max 1.75 0.25 1.65 0.51 0.25 5.00 4.00 1.27 5.80 0.25 0.40 6.20 0.50 1.27 0.10 0.228 0.010 0.016 Mi n 0.053 0.004 0.043 0.013 0.007 0.189 0.15 0.050 0.244 0.020 0.050 0.004 inch Typ Ma x 0.069 0.010 0.065 0.020 0.010 0.197 0.157
A A1 A2 B C
D
1.35 0.10 1.10 0.33 0.19 4.80 3.80
(1)
E e H h L k ddd
0 (min.), 8 (max.)
1. Dimensions D does not include mold flash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side).
Figure 4.
SO8 package dimensions
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Package mechanical data
L6743, L6743Q
Table 4.
Ref.
DFN10 mechanical data
mm Min. Typ. 0.90 0.02 0.70 0.20 0.18 0.23 3.00 2.21 2.26 3.00 1.49 1.64 0.50 0.3 0.4 0.5 0.012 1.74 0.059 2.31 0.087 0.30 0.007 Max. 1.00 0.05 Min. 0.031 inch Typ. 0.035 0.001 0.028 0.008 0.009 0.118 0.089 0.118 0.065 0.20 0.016 0.020 0.069 0.091 0.012 Max. 0.039 0.002
A A1 A2 A3 b D D2 E E2 e L
0.80
Figure 5.
Package dimensions
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L6743, L6743Q
Revision history
4
Revision history
Table 5.
Date 30-Mar-2007
Document revision history
Revision 1 Initial release. Changes
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L6743, L6743Q
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