STLS2F01
High performance 64-bit superscalar
Features
MIPS
Loongson 2F: microprocessor
Data Brief
64-bit superscalar architecture 900 MHz clock frequency Single/double precision floating-point units New streaming multimedia instruction set support (SIMD) 64 Kbyte instruction cache, 64 Kbyte data cache, on-chip 512 Kbyte unified L2 cache On chip DDR2-667 and PCI-X controller 4 W @ 900 MHz power consumption: Best in class for power management Voltage/frequency scaling Stand-by mode support L2 cache disable/enable option Leading edge 90 nm process technology 27x27 heat spreader flip-chip BGA package MIPS based instruction set (MIPS III compatible)
HFCBGA452 (27x27x2.9mm)
The memory hierarchy is composed by the first level of 64 Kbyte 4-way set associative caches for instructions and data, the second level of 512 Kbyte unified 4-way set associative cache and the memory management unit (MMU) with translation lookaside buffer (TLB). The Loongson microprocessor family is the outcome of a successful collaboration started in 2004 between STMicroelectronics and the Institute of Computing Technology, part of the Chinese Academy of Science. Loongson microprocessors were co-developed by STMicroelectronics and the Institute of Computing Technology to address all the applications requiring high level of performance and low power dissipation. Compared to the STLS2E02 processor, the STLS2F01 has an enhanced architecture providing higher performance, reduced power consumption, integrated DDR2 memory controller and PCI-X bus interface.
Description
The STLS2F01 is a MIPS based 64-bit superscalar microprocessor, able to issue four instructions per clock cycle among six functional units: two integer, two single/double-precision floating-point, one 64-bit SIMD and one load/store unit. The micro architecture is organized with ninestage of pipeline and support of dynamic branch prediction. Table 1. Device summary
Part numbers STLS2F01
Package HFCBGA452 (27x27x2.9mm)
Packing Tray
June 2008
Rev 2
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www.st.com 6
For further information contact your local STMicroelectronics sales office.
Architectural features and block diagram
STLS2F01
1
Architectural features and block diagram
CPU Out-of-order superscalar 64-bit architecture MIPS based, compatible with MIPS III instruction set Nine-stage pipeline organized in fetch, pre-decode, decode, reg-map, dispatch, issue, reg-read, execution and commit Up to 64 instructions executed out-of-order with four issue mechanism 64-bit register file (32 fix + 32 float) Register renaming unit composed by 64-entry physical register files Branch prediction unit Six functional units: two integer, two float, one SIMD unit, one load/store unit 64 Kbyte + 64 Kbyte four-ways set-associative first level instruction and data cache 512 Kbyte four-ways set associative unified second level cache Up to 24 non-blocking accesses with on-the-fly memory disambiguation Load speculation through value returned from previous pending stores Miss word first access for cache miss access Instruction 16-entry TLB (table lookside buffer) and unified 64-entry TLB with page size from 4 Kbyte to 4 Mbyte
Memory Hierarchy
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STLS2F01 Figure 1. Block diagram
Architectural features and block diagram
Commit Bus Branch Bus Reorder Queue BRQ BTB PC + 16 Map Bus Register Mapper Fix RS Integer Register File ALU1 ALU2 AGU Float RS Floating Point Register File FPU1 FPU2 TLB D-Cache 64KB TAG Compare DDR2 Controller 333MHz DDR CP0 Queue ROQ Writeback Bus
Pre-Decoder Refill Bus
BHT PC
ITLB
I-Cache 64KB
Decoder
Miss Writeback Cache Interface Queue Queue
L2 cache
I/O Controller
AXI Crossbar
133MHz PCI-X Local IO GPIO, INT
AC00117
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Package information
STLS2F01
2
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. HFCBGA452 mechanical data and package dimensions
mm D IM . MIN. A A1 A3 A4 b D D1 E E1 e F aaa ddd eee fff 0.450 0.250 1.300 1.000 0.500 TYP. M AX . 3.150 0.0098 0.0512 0.0394 0.550 0.0177 0.0197 0.0217 MIN. TYP. MAX. 0.1240 inch
OUTLINE AND MECHANICAL DATA
26.800 27.000 27.200 1.0551 1.0630 1.0709 25.000 0.9843
26.800 27.000 27.200 1.0551 1.0630 1.0709 25.000 1.000 1.000 0.200 0.200 0.250 0.100 0.9843 0.0394 0.0394 0.0079 0.0079 0.0098 0.0039
HFCBGA452 (27x27x2.9mm)
Heat Spreader Flip Chip Ball Grid Array
8061758 A
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STLS2F01
Revision history
3
Revision history
Table 2.
Date 31-May-2007 06-Jun-2008
Document revision history
Revision 1 2 Initial release. Change in the Features sections: "clock frequency" Changes
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STLS2F01
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