STEVAL-IPC001V1
Electronic fiscal cash register
Data Brief

Features

4-Mbyte Flash, 32-Mbyte NAND and 1-Mbyte SRAM on board Two smartcard readers STM1404 secure chip, FIPS 140-2 compliant Ethernet 10Base-T, 3 UARTs, 1 RS-485, 1 PS/ 2, 1 USB full speed, 4 x I2C, 1 x SPI, 2 LCDs Expandable connector for upgrading to a 64Mbyte Flash or 64-Mbyte SRAM Firmware available Cash register demo TCP/IP stack PS/2 firmware driver RFID CRX14 driver RFID manager Smartcard manager for reader and writer Fidelity card demo The PC GUI is a user-friendly PC application to manage both goods information and board parameters through a dedicated protocol. STEVAL-IPC001V1

Description
The STEVAL-IPC001V1 is an integrated system to allow designers to evaluate a complete and ready-to-use cash register application. It is intended for the low to medium-end POS/cash register market and consists of a hardware board, firmware and PC GUI (graphical user interface). At the core of the board, the STR710FZ2 microcontroller controls all tasks of the system. The STR710FZ2 gives the board a wide scope of communication capabilities, incorporating four UARTs, one 10T-LAN, one PS/2 interface and various IC and SPI connectors. The firmware is a modular suite which simultaneously implements a typical cash register application and provides a suitable library to develop an optimized and customized final application.

September 2008

Rev 2

1/4
www.st.com 4

For further information contact your local STMicroelectronics sales office.

1

+1V8

TP 4 TP 1
TP 2

47 51 WAKEUP ORANGE 6 +3V3 22 40 83 104 113 138

66

58 129 55

1

1

1

V33.1 V33.2 V33.3 V33.4 V33.5 V33.6 V33.7

AVDD

V18.1 V18.2 V18BKP

SW 1
R5 33

+3 V 3
D4

POWER

1

P0.15/WAKEUP STBY

D7 D6 D5 D4 D3 D2 D1 D0
ADC
P 1 .0 /T3 .O CMP B /A IN.0 P 1 .1 /T3 .ICA P A /A IN.1 P 1 .2 /T3 .O CMP A /A IN.2 P 1 .3 /T3 .ICA P B /A IN.3 71 72 73 74

EMI

SPI0

MICROCONTROLLER

CS .2 n RD W E0
SPI1

UART0

UART1

RD W E .0 W E .1

RX _ 1 _ IO TX _ 1 _ RS T S CClk
1 2 TX _ 1 _ RS T
3

PRINTER CONNECTOR

UART2

DEBUG

GPIO PORT

ETHERNET

42 59 84 103 112 128 139 5 21 54 67 110 109 87 70 69 68 60 57 56 53

VSS1 TIMER1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSSBKP AVSS NC NC NC NC NC NC NC NC NC NC

2/4

Board schematic

Figure 1.

5

4
3

2

1

V18BKP
J1
D1

+1 V 8
+3 V 3

RX _ 1 _ IO
+5 V

+5 V
+3 V 3

BOOT
C1 22u
C2 33n

SW 4

+3 V 3
D6 6 6

LOGIC
P IN2 TX _ 1 _ RS T

C4 1u

C1 2 0 0 33n

P 1 .1 5
VBKP
B Z1
D2

1
LL4148

R1 560

G RE E N

S CClk

+5 V
+1 V 8
+3 V 3

B O O TE N
D3

2
LL4148

3

R9 10K

R1 0 1K

R3 560

B O O T_ E N

+3 V 3
O RA NG E
R4 560
BLU

R2 10k
B UZZE R

+1 V 8
+3 V 3
VBKP

CK
G ND

+3 V 3 Y2 1 6 MHz 471-9376 1 4 E /D V CC 3 O UT G ND 2

D

R1 3 10k

3

n O RA NG E
+3 V 3

D5

VBKP
P W RMNG T

TX _ 1 _ RS T
YE L L O W
SUPPLY
P 1 .1 0 /US B CL K USB US B DN US B DP 106 91 90

2

R7 10k

B O O T_ 1 S W 2

1

CS .0 CS .1 R6 CS .2 2 2
P 2 .0 /CS .0 P 2 .1 /CS .1 P 2 .2 /CS .2 P 2 .3 /CS .3
C3 10nF

CS .3
SW 3 L CD Select
U2
V CC 6A 6Y 13 12
C7 100n

R1 1 22 R8 22

R1 5 22

P 2 .0 P 2 .1 P 2 .2 P 2 .3

7 8 11 12

GENERAL CK P 1 .8 P 1 .9

46 86 105

+1 V 8
R1 2 560
LED

CK P 1 .8 DS R
R1 6 10k

D

R1 4 560

3
U1
14

+3 V 3
+5 V O U T +3 V 3 O U T +1 V 8 O U T P W RO UT G ND

Schematic

Tx_ 0
SYSTEM RS TIN CK O UT
52 45

2

US B Clk US B DN US B DP

P 1 .8
R1 7 0
C5 100n
3 O RA NG E2 A 4E n O RA NG2 Y
R1 8 560

1

B O O T_ 0

+5 V +3 V 3 VBKP

n ot Reset
3

Y3 3 2 .7 6 8 K h z 472-0887 2

1 A21 Q 1A 21 nQA21 Y

Board schematic

L CD
3A 3Y G ND
4A 4Y 9 8

RTC RTCX TI RTCX TO

49 50

n E _ L CD C6 + E _ L CD 4 7 u

PW R G ND

RTCX TI RTCX TO

RTCX TI

4

1

RTCX TO
+3 V 3S W 5 MO ME NTA RY

n RD 5 6 Rn otW

5A 5Y

11 10

E E CS n CS 9 5
p ower

A22
C1 0 100n

A22

n otE Rn otW

n E _ L CD Rn otW

C8 15pF

C9 15pF

W A K E UP
7

P S 2 _ CL K P S 2 _ DA TA

B O O TE N JTDI STS JTDO JTCK JTMS JTRS T

16 30 33 32 31 34

B O O TE N JTDI JTDO JTCK JTMS n ot JTRST
R1 9 560
7 4 L CX 1 4 TTR

QA23 nQA23

Tx_ 0 Rx_ 0 P 0 .7 S CL K MO S I G ND +3 V 3 P IN1 3 7 P IN1 3 6 A19 A18 A17 A16 A15 A14 +1 V 8 G ND MIS O P 0 .3 P 0 .2 P 0 .1 P 0 .0 A13 A12 A11 A10 A9 A8 A7 A6 A5 +3 V 3 G ND P 1 .1 5

G ND +3 V 3 +5 V
U1 8
J2

P RN_ TM1 MO T1 _ A P RN_ S NS MO T1 _ B
J3

E _ L CD0 E _ L CD1
CAN P 1 .1 1 /CA NRX P 1 .1 2 /CA NTX

CL K _ P S 2 D7 DA TA _ P S 2 D6 D5 D4 D3 G ND D2 +3 V 3 D1 +5 V D0 E _ L CD0 E _ L CD1

R1 4 1 47k

88 89

R1 4 2 47k

A0 98 A1 99 TP A2 3 100 A3 101 A4 102 A5 114 A6 115 A7 116 A8 117 A9 118 A10 119 A11 120 A12 121 A13 122 A14 130 A15 131 132 A16 133 A17 134 A18 135 A19 13 A20 14 A21 15 A22 17 A23
A .0 A .1 A .2 A .3 A .4 A .5 A .6 A .7 A .8 A .9 A .1 0 A .1 1 A .1 2 A .1 3 A .1 4 A .1 5 A .1 6 A .1 7 A .1 8 A .1 9 P 2 .4 /A .2 0 P 2 .5 /A .2 1 P 2 .6 /A .2 2 P 2 .7 /A .2 3

S cDetect MO T2 _ O N
CMD_ IO _ S C0 1 1 0 G ND 9
+3 V 3
A B

V DD

1 6 +3 V 3

CONs
+3 V 3
R2 3 1 0 k J4

C

n CS 9 5 E E CS
R2 1 4 .7 K
P 0 .0 /S 0 .MIS O /U3 .TX P 0 .1 /S 0 .MO S I/U3 .RX P 0 .2 /S 0 .S CL K /I1 .S CL P 0 .3 /S 0 .S S N/I1 .S DA 123 124 125 126

n CS 9 5 E E CS

+3 V 3

+3 V 3
R2 5
R2 2 0

P 1 .1 3 /HCL K /IO .S CL P 1 .1 4 /HCL K /IO .S CL P 1 .1 4 /HTX D I2C0

107 108 111

P 1 .1 3 nSAL P 1 .1 5
+3 V 3
R2 0 4 .7 K

G ND 6 I_ O 1 3 S CClk 3
INH X CO M YCO M NC
G ND 8

S CL K MIS O MO S I P RN_ L P RN_ S TB +3 V 3 P RN_ TM1 30k P RN_ TM2 R2 4 P RN_ S NS
P RN_ TM1
C1 1 0 .1 u

C

nQA23 QA23

G ND

G ND

P 0 .0 P 0 .1 0
S CL S DA
7

X0 X1 X2 X3 Y0 Y1 Y2 Y3

IO _ S C0 12 IO _ S C1 14 15 11 CL K _ S C0 1 CL K _ S C1 5 2 4

nA23 QA23

RE S E T

P 1 .7

P 0 .2 P 0 .3
G ND
CO N3
M7 4 HC4 8 5 2 TTR

R1 4 3 47k

R1 4 4 47k

P 0 .7

1 2 3

n E _ L CD
IC2 6
1

n E _ L CD

n RD
P 0 .4 /S 1 .MIS O P 0 .5 /S 1 .MO S I P 0 .6 /S 1 .S CL K P 0 .7 /S 1 .S S N 127 140 141 142

P RN_ TM2

CS .2 n RD nW E0

nW E0
I_ O
2 RX _ 1 _ IO 3

nW E1
P 0 .8 /U0 .RX /U0 .TX P 0 .9 /U0 .TX /B O O T.0 143 144

R2 7 22

MIS O MO S I S CL K P 0 .7

INT_ 0
P 0 .1 0 /U1 .RX /U1 .TX P 0 .1 1 /U1 .TX /B O O T.1 P 0 .1 2 /S CCL K
9 10

IRQ _ L A N
1 3 4

R2 8 22

D0 D1 D2 D3 D4 D5 D6 D7 D8 R2 6 D9 22 D1 0 D1 1 D1 2 D1 3 D1 4 D1 5
Rx_ 0 Tx_ 0
G ND 1 A23 2 A21 3 G ND 4 5
SW 7

61 62 63 64 65 78 79 80 81 82 92 93 94 95 96 97 D.0 D.1 D.2 D.3 D.4 D.5 D.6 D.7 D.8 D.9 D.1 0 D.1 1 D.1 2 D.1 3 D.1 4 D.1 5

Rx_ 1

nSAL P 1 .1 3 US B Clk DS R +3 V 3 G ND A4 A3 A2 A1 A0 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 US B DN US B DP MO T2 _ O N S cDetect
RS T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MO T2 _ O N MO T1 _ A MO T1 _ E A MO T1 _ B MO T1 _ E B +5 V G ND PW R G ND PW R G ND PW R

P 0 .1 3 /U2 .RX /T2 .O CMP A P 0 .1 4 /U4 .TX /T2 .ICA P A

Rx_ 2 Tx_ 2
7 4 L V X 5 7 3 TTR
IC2 5

6 7 8 9 10
SW 8

OE D0 D1 D2 D3 D4 D5 D6 D7 G ND

V CC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE

2 0 +3 V 3 19 QA23 18 QA21 17 16 15 14 13 12 1 1 CS .2

Tx_ 1
3

J5

P S 2 _ DA TA
1

DB G RO S NC

44 35

DB G RQ S
P IN3 5
R2 9 0

+3 V 3

P 1 .1 3

2 SW 9
3

RTC_ IRQ

P 0 .7 P 1 .6 +3 V 3 MO S I
2

P 2 .8 P 2 .9 P 2 .1 0 P 2 .1 1 P 2 .1 2 P 2 .1 3 P 2 .1 4 P 2 .1 5

STR710FZ2T6
P IN3 6 P IN3 8 R3 0 0
R3 1 0

Tx_ 3

P 0 .0

1

B

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 D1 3 D1 4 D1 5
SW 10
3
1 E _ L CD 2 QA21 3 E _ L CD0 4 E _ L CD 5 n Q A 2 16 E _ L CD1 7 1 V DD 13 2 12 3 11 4 10 5 9 6 G ND 8 7 4 L V Q 0 8 TTR
14 13 12 11 10 9 8
P 1 .4 /T1 .ICA P A P 1 .5 /T1 .ICA P B P 1 .6 /T1 .O CMP B P 1 .7 /T1 .OCMP A

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 D1 3 D1 4 D1 5

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 L A N-1 0 T A 0
36 38 19 20 37 39 41 43 48

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2

DTR
Rx_ 3 P 0 .1
1

MIS O S CL K

1 2 3 4 5 6 7

CO N7

1 2 3 4 G ND 5 +3 V 3 6 P 2 .0 7 P 2 .1 8 Rx_ 2 9 Tx_ 2 10 P 2 .2 1 1 P 2 .3 1 2 A20 13 A21 14 A22 15 B O O TE1 6 N A23 17 FL A S H VPP 18 19 20 G ND 2 1 +3 V 3 2 2 P S 2 _ CL K 2 3 IRQ _ L A N 2 4 n O FF 25 P 2 .1 2 26 P RN_ L 2 7 P RN_ S TB2 8 P 2 .1 5 2 9 JTDI 3 0 JTMS 3 1 JTCK 3 2 JTDO 3 3 34 n ot JTRST P IN3 5 3 5 P IN3 6 3 6 37 P IN3 8 3 8 39 +3 V 3 4 0 41 G ND 4 2 43 4S DB G RQ 4 45 46 CK 4P W A K E U7 48 RTCX T4 9 I 5 RTCX TO0 5E O RA NG 1 52 n ot Reset 53 G ND 5 4 5 V18BKP 5 56 57 +1 V 8 5 8 G ND 5 9 60 61 D0 62 D1 63 D2 64 D3 65 D4 66 G ND 6 7 68 69 70 P RN_ TM1 7 1 72 MOT1 _ A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 CO N5 8
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

P 1 .8 P 1 .7 G ND +3 V 3 D9 D8 D7 D6 D5 P 1 .6 CMDV CC MO T1 _ E B MOT1 _ B P RN_ S NS
B

2 P IN2 3 7 1 P IN1 3 7 3 6 1 P IN1 3 6 18 23 FL A S H VPP P S 2 _ CL K 2 4 IRQ _ L A N 2 5 26 n O FF 27 P 2 .1 2 28 P RN_ L P RN_ S TB 2 9 P 2 .1 5 75 76 MO T1 _ E B 77 CMDV CC 85 P 1 .6 P 1 .7
TE S T1 TE S T2 NC NC NC NC NC NC NC

SW 11

CMD_ IO _ S C0 1

1

1

2

RS T_ S C1
P _ DRA W E R

P 2 .1 2
3

COMMUNICATIONs
2

P 2 .1 5

3

MO T1 _ E A
SW 12

V CC_ S C0

SW 26
E MI_ S RA M

S C-UA RT1

MEMORIES
FL A S H

DRAWER
P _ DRA W E R
P 2 .1 2 P W R +5 V DRA W E R G ND

JTAG
JTA G

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 +5 V +3 V 3 G ND MO T2 _ O N CS .0 CS .1 CS .2 CS .3 n RD nW E0 nW E1 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 CO N5 0
+3 V 3 G ND

+3 V 3 G ND n ot Reset CS .3 n RD nW E0
A22 A21 R/B

+3 V 3 G ND
CS .3 n RD nW E0
A22 A21 Tx_ 3

+3 V 3 +3 V 3 G ND G ND

Tx_ 0 Tx_ 1 Tx_ 2 Tx_ 3

Tx_ 0 Tx_ 1 Tx_ 2 Tx_ 3

+3 V 3 G ND

+3 V 3 G ND

CL K _ S C0 IO _ S C0 RS T S cDetect V CC_ S C0

C L K _ S C 0 +5 V I O _ S C 0 +3 V 3 RS T_ S C0 G ND DE T_ S C0 V CC_ S C0

+5 V +3 V 3 G ND

n ot Reset

+3 V 3+3 V 3 V O UT V O UT G ND G ND

PW R +5 V G ND

+3 V 3 G ND

DTR DS R

DTR DS R

CMDV CC IO _ S C1 CL K _ S C1 RS T_ S C1

Rx_ 0 Rx_ 1 Rx_ 2 Rx_ 3
NA ND

Rx_ 0 Rx_ 1 Rx_ 2 Rx_ 3

UA RTx

n O FF

V CC_ S C1 IO _ S C1 CL K _ S C1 RS T_ S C1 n O FF

ESD

RTC SECURE

JTDI JTDI JTDO JTDO JTCK JTCK JTMS JTMS n n ot JTRST ot JTRst n ot Reset n ot Reset DB G RQ S DB G RQ S

A

S C-UA RT1

+5 V G ND

CL K P S 2 _ CL K DA TA P S 2 _ DA TA PS2

+5 V G ND
FL A S H VPP

MIS O S CL K
nW E0 n RD CS .0

+3 V 3 MIS O CL K _ S P I G ND

+3 V 3 G ND

D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7

D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

+3 V 3 S DA S DA S CL G ND U3 S CL V O UT 6 1 RTCX TI IRQ JTDI2 I/O1 I/O5 5 JTCK RTCX TI RTCX TO IRQ_ S C G ND I/O 4 G ND JTMS 4 3 RTCX TO M4 1 T8 1 S n ot JTRST JTDO I/O2 I/O3 E S DA 6 V 1 -5 W 6
U7

+3 V 3 G ND n ot Reset RE S E T V O UT RTC_ IRQ RE S E T nSAL

+3 V 3 G ND

+3 V 3 G ND
A

D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

U6 1 2 P RN_ L G ND 3 I/O 1 I/O 5 G ND I/O 4 I/O 2 I/O 3
6 5 4

U5

K E YP A D

S CL S DA

S CL S DA
n ot Reset

+5 V G ND +3 V 3

S C L +3 V 3 S CL S DA G ND S DE E P RO M A

+3 V 3 G ND

RE S E T

A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A21
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
W E0 W E1 n ot OE n ot CS_SRAM A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

D1 5 D1 4 D1 3 D1 2 A20 A19 D1 1 A18 D1 0 D9 A17 D8 A16 D7 A15 D6 A14 D5 A13 D4 A12 D3 A11 D2 A10 D1 A9 D0 A8 A7 VPP A6 A5 n ot WR A4 n ot OE A3 n ot CS_FLASH A2 A1 n ot Reset A21

nW E0 nW E1 n RD CS .1

1 I/O 1 I/O 5 6 2 G ND I/O 4 5 RS T 3 I/O 2 I/O 3 4 G ND n O FFE S DA 6 V 1 -5 W 6

I_ O S CClk P RN_ S TB

P RN_ S TB DA 6 V 1 -5 W 6 ES

n ot Reset DB G RQ S P 2 .1 2

1 I/O 1 I/O 5 6 2 P RN_ S NS G ND I/O 4 5 G ND 3 I/O 2 I/O 3 4 MO T1 _ B E S DA 6 V 1 -5 W 6

MO T2 _ O N MO T1 _ E A MO T1 _ E B

U4 6 1 MIS O2 I/O1 I/O5 5 G ND 3 G ND I/O 4 4 I/O 2 I/O 3 MO S I E S DA 6 V 1 -5 W 6

MO T1 _ A P RN_ TM1 S CL K

I2 C

n ot Reset

+5 V US B Clk G ND +3 V 3 U S B D N US B DP

US B Clk +3 V 3 +3 V 3 G ND G ND US B DN US B DP US B

STEVAL-IPC001V1

5

4

3

2

1

STEVAL-IPC001V1

Revision history

2

Revision history
Table 1.
Date 26-Nov-2007 01-Sep-2008

Document revision history
Revision 1 2 Initial release Minor text changes, to improve readability Changes

3/4

STEVAL-IPC001V1

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4/4

Document Number: 14197



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