SPEAR-09-H042
SPEArTM Head200 ARM 926, 200 K customizable eASICTM gates, large IP portfolio SoC
Data Brief
Features
ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces 200K customizable equivalent ASIC gates (16K LUT equivalent) with 8 channels internal DMA high speed accelerator function and 87 dedicated general purpose I/Os Multilayer AMBA 2.0 compliant bus with fMAX 133 MHz Programmable internal clock generator with enhanced PLL function, specially optimized for E.M.I. reduction 16 KB single port SRAM embedded Dynamic RAM interface: 8/16 bit DDR, 8/16 bit SDRAM SPI interface connecting serial ROM and Flash devices 2 USB 2.0 Host independent ports with integrated PHYs USB 2.0 device with integrated PHY Ethernet MAC 10/100 with MII management interface 1 independent UART up to 115 Kbps (software flow control mode) I2C master mode, fast and slow speed 6 general purpose I/Os Device summary
Order code SPEAR-09-H042 Package LFBGA289 (15x15x1.7mm) Packing Tray
LFBGA289
Real time clock WatchDog 4 general purpose timers Operating temperature: - 40 to 85 C Package: LFBGA289 (15x15x1.7mm pitch 0.8mm)
Description
SPEAr Head200 is a powerful digital engine belonging to SPEAr family, the innovative customizable system-on-chip. The device integrates an ARM core with a large set of proven IPs (Intellectual Properties) and a configurable logic block that allows very fast customization of unique and/or proprietary solutions, with low effort and low investment. Optimized for embedded applications.
Table 1.
Januar y 2008
Rev 1
1/16
www.st.com 16
For further information contact your local STMicroelectronics sales office.
Contents
SPEA R-09-H042
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 2.5 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 eASIC GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 External FPGA emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic RAM data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 3.3 Interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ballout top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 5
Package outline assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/16
SPEAR-09-H042
Introduction
1
Introduction
This data brief describes the differences between SPEAr Head200 (SPEAR-09-H022) and the one packaged in LFBGA289 balls 0.8mm pitch (SPEAR-09-H042). In this document the main package characteristics are described as well as the chip features modifications. The reference specifications, for the SPEAR-09-H022 are available on the web at: www.st.com.
3/16
Features modification
SPEA R-09-H042
2
Features modification
To fit the new small package a number of features has been reduced or limited:
Analog to digital converter (ADC) eASIC GPIOs External FPGA emulation mode Dynamic RAM data path UARTs
2.1
Analog to digital converter (ADC)
ADC feature has been completely deleted so the 16 analog channels, the related test output, the power balls and the reference voltages have been removed.
2.2
eASIC GPIOs
SPEAR-09-H022 features 112 GPIOs in the eASIC customizable part, some of these I/Os have been removed, but 87 are still available on SPEAR-09-H042. Unusable hidden eASIC GPIOs (74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100-111) must be configured as inputs.
2.3
External FPGA emulation mode
SPEAR-09-H022 has the capability to emulate the internal eASIC behavior with an external FPGA through the component GPIOs. This feature has been completely removed on SPEAR-09-H042 hence the developement boards must use the 420 PBGA components.
2.4
Dynamic RAM data path
The SPEAr component features a multi purpose memory controller to interface SDRAM or DDR memories able to work with different data path widths. While SPEAR-09-H022 handles 8 and 16-bit DDRs or 8, 16 and 32-bit SDRAMs, on SPEAR-09-H042 to save 16 data balls and the related "data mask" balls, the SDRAM data path has been limited to 16-bit like the DDR one.
2.5
UARTs
Two of the original UART interfaces have been removed, SPEAR-09-H042 features just the UART1 interface.
4/16
SPEAR-09-H042
Pin description
3
Pin description
Table 2 shows the component signals, grouped by function, and the relative ballout diagram.
3.1
Interface signals
Table 2.
Group
Interface signals
Signal Name TEST0 TEST1 Ball A14 H14 H13 H12 G1 G4 H7 H6 H5 F3 E4 F5 D2 E3 D3 D1 G6 G7 D4 C1 E5 F6 B1 E6 B4 F7 A1 Input I/O Enable / disable PLL bypass eASIC general purpose I/O Input Test configuration port. For the functional mode they have to be set to 0 Direction Function
Debug
TEST2 TEST3 PLL_BYPASS
eASIC
eASICGP_IO[00] eASICGP_IO[01] eASICGP_IO[02] eASICGP_IO[03] eASICGP_IO[04] eASICGP_IO[05] eASICGP_IO[06] eASICGP_IO[07] eASICGP_IO[08] eASICGP_IO[09] eASICGP_IO[10] eASICGP_IO[11] eASICGP_IO[12] eASICGP_IO[13] eASICGP_IO[14] eASICGP_IO[15] eASICGP_IO[16] eASICGP_IO[17] eASICGP_IO[18] eASICGP_IO[19] eASICGP_IO[20] eASICGP_IO[21]
5/16
Pin description Table 2.
Group
SPEA R-09-H042 Interface signals (continued)
Signal Name eASICGP_IO[22] eASICGP_IO[23] eASICGP_IO[24] eASICGP_IO[25] eASICGP_IO[26] eASICGP_IO[27] eASICGP_IO[28] eASICGP_IO[29] eASICGP_IO[30] eASICGP_IO[31] eASICGP_IO[32] eASICGP_IO[33] eASICGP_IO[34] eASICGP_IO[35] eASICGP_IO[36] eASICGP_IO[37] eASICGP_IO[38] eASICGP_IO[39] eASICGP_IO[40] eASICGP_IO[41] eASICGP_IO[42] eASICGP_IO[43] eASICGP_IO[44] eASICGP_IO[45] eASICGP_IO[46] eASICGP_IO[47] eASICGP_IO[48] eASICGP_IO[49] eASICGP_IO[50] eASICGP_IO[51] eASICGP_IO[52] eASICGP_IO[53] eASICGP_IO[54] eASICGP_IO[55] eASICGP_IO[56] Ball A3 A4 C2 F4 C3 C5 B5 H8 B2 G5 B3 A2 C4 A5 H9 C6 G9 C7 D5 B6 A6 G8 E8 E9 D8 B7 E7 F8 A7 B8 A8 D9 D6 F9 D7 Direction Function
6/16
SPEAR-09-H042 Table 2.
Group
Pin description Interface signals (continued)
Signal Name eASICGP_IO[57] eASICGP_IO[58] eASICGP_IO[59] eASICGP_IO[60] eASICGP_IO[61] eASICGP_IO[62] eASICGP_IO[63] eASICGP_IO[64] eASICGP_IO[65] eASICGP_IO[66] eASICGP_IO[67] eASICGP_IO[68] eASICGP_IO[69] eASICGP_IO[70] eASICGP_IO[71] eASICGP_IO[72] eASICGP_IO[73-74] eASICGP_IO[75-76] eASICGP_IO[77-78] eASICGP_IO[79-80] eASICGP_IO[81-82] eASICGP_IO[83-84] eASICGP_IO[85-86] eASICGP_IO[87-88] eASICGP_IO[89-90] eASICGP_IO[91-92] eASICGP_IO[93-94] eASICGP_IO[95-96] eASICGP_IO[97-98] eASICGP_IO[99] eASIC_EXT_CLOCK eASIC_PI_CLOCK Ball F10 C9 B9 A9 G10 C8 E10 D10 C10 B10 A10 G11 F11 E11 D11 C11 B11 A11 A12 B12 C12 D12 E12 A13 B13 C13 D13 E13 C14 D14 E14 K15 C15 C16 C17 Input eASIC program interface out clock Ethernet input TX clock Ethernet TX output data Ethernet TX output data Direction Function
Ethernet
TX_CLK TXD[0] TXD[1]
7/16
Pin description Table 2.
Group
SPEA R-09-H042 Interface signals (continued)
Signal Name TXD[2] TXD[3] TX_EN CRS COL RX_CLK RXD[0] RXD[1] RXD[2] RXD[3] RX_DV RX_ER MDC MDIO GP_IO[0] GP_IO[1] Ball D15 D16 D17 E15 E16 E17 F15 F16 F17 G15 G16 G17 H15 H16 M1 5 L17 L16 L15 K17 K16 H17 J15 F12 F13 F14 G12 G13 G14 N1 N2 G3 T12 R12 T13 R13 I/O Output Output Input Input Output Input Output Input Output Input I2C serial data I2C clock JTAG TDO JTAG TDI JTAG TMS JTAG output clock JTAG clock JTAG reset 12MHz input crystal 12MHz output crystal Master reset I/O General purpose I/O Input Input Output I/O Data valid on RX Data error detected Output timing reference for MDIO I/O data to PHY Input Ethernet RX input data Input Input Direction Output Function Ethernet TX output data Ethernet TX output data Ethernet TX enable Carrier sense input Collision detection input Ethernet input RX clock
GPI/Os
GP_IO[2] GP_IO[3] GP_IO[4] GP_IO[5] SDA
I2C SCL TDO TDI JTAG TMS RTCK TCK nTRST Master clock Master reset MPMC MCLK_in MCLK_out MRESET MPMCDATA[00] MPMCDATA[01] MPMCDATA[02] MPMCDATA[03]
8/16
SPEAR-09-H042 Table 2.
Group
Pin description Interface signals (continued)
Signal Name MPMCDATA[04] MPMCDATA[05] MPMCDATA[06] MPMCDATA[07] MPMCDATA[08] MPMCDATA[09] MPMCDATA[10] MPMCDATA[11] MPMCDATA[12] MPMCDATA[13] MPMCDATA[14] MPMCDATA[15] MPMCADDROUT[00] MPMCADDROUT[01] MPMCADDROUT[02] MPMCADDROUT[03] MPMCADDROUT[04] MPMCADDROUT[05] MPMCADDROUT[06] MPMCADDROUT[07] MPMCADDROUT[08] MPMCADDROUT[09] MPMCADDROUT[10] MPMCADDROUT[11] MPMCADDROUT[12] MPMCADDROUT[13] MPMCADDROUT[14] nMPMCDYCSOUT[0] nMPMCDYCSOUT[1] nMPMCDYCSOUT[2] nMPMCDYCSOUT[3] MPMCCKEOUT[0] MPMCCKEOUT[1] MPMCCLKOUT[0] nMPMCCLKOUT[0] Ball T14 R14 T15 R15 T17 P16 P17 N15 N16 N17 M16 M17 R6 U7 T7 R7 U8 T8 R8 U9 T9 R9 U10 T10 R10 T11 R11 U4 T4 T5 R5 U11 U12 U16 U15 Output DDR / SDRAM clock 1 DDR / SDRAM clock 1 neg. Output DDR / SDRAM clock enable Output DDR / SDRAM chip select Output DDR / SDRAM address I/O DDR / SDRAM data Direction Function
9/16
Pin description Table 2.
Group
SPEA R-09-H042 Interface signals (continued)
Signal Name MPMCCLKOUT[1] nMPMCCLKOUT[1] MPMCDQMOUT[0] MPMCDQMOUT[1] MPMCDQS[0] MPMCDQS[1] nMPMCCASOUT nMPMCRASOUT nMPMCWEOUT RTC RTCXO RTCXI SMINCS[0] SMINCS[1] SMINCS[2] SMI SMINCS[3] SMICLK SMIDATAIN SMIDATAOUT UART1_RXD UART UART1_TXD DMNS DPLS HOST1_DP HOST1_DM HOST2_DP HOST2_DM USBs HOST1_VBUS HOST2_VBUS OVERCURH1 OVERCURH2 VBUS RREF J16 R2 R1 L1 L2 J1 J2 F1 F2 E1 E2 G2 J6 Output I/O I/O I/O I/O I/O I/O Output Output I/O I/O I/O Input UART1 TX data D- port of USB device D+ port of USB device D+ port of USB host1 D- port of USB host1 D+ port of USB host2 D- port of USB host2 USB host1 VBUS signal USB host2 VBUS signal USB host1overcurrent USB host2 overcurrent USB device VBUS signal USB reference resistor Ball U14 U13 T16 Output U17 R16 Output R17 T6 Output U6 U5 U2 U1 B15 A17 A16 A15 B16 B17 B14 J17 Output Input Output Input Serial flash output clock Serial flash data in Serial flash data out UART1 RX data Output Serial flash chip select Output Output Input DDR / SDRAM write enable 32.768KHx output crystal 32.768KHz input crystal DDR / SDRAM strobes DDR data strobe DDR / SDRAM data mask Direction Function DDR / SDRAM clock 2 DDR / SDRAM clock 2 neg.
10/16
SPEAR-09-H042
Pin description
3.2
Power connections
Table 3.
Group
Power connections
Signal Name vdd3v3 vdd gnd vdd_dith vss_dith SSTL_VREF vdd2v5_DDR vdd1v2_date_osci vdd_date_osci gnd_date_osci gnde_date_osci anavdd_3v3_pll1600 anagnd_3v3_pll1600 digvdd_1v2_pll1600 diggnd_1v2_pll1600 vddl_1v2_d vddb_1v2_d Ball
(1) (2) (3)
Function Digital 3.3V power Digital 1.2V power Digital ground DDR / SDR dedicated digital PLL 3.3V power DDR / SDR dedicated digital PLL ground Voltage reference SSTL / CMOS mode. This pin is used both as logic state and as power supply DDR / SDR digital 2.5V / 3.3V power 1.2V dedicated power for RTC 1.2V dedicated power for RTC Dedicated digital ground for RTC Dedicated digital ground for RTC Dedicated USB PLL analog 3.3V power Dedicated USB PLL analog ground Dedicated USB PLL analog 1.2V power Dedicated USB PLL analog ground Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 1.2V power Dedicated USB 3.3V power Dedicated USB 3.3V power Dedicated USB 3.3V power Dedicated USB 3.3V power Dedicated USB ground Dedicated USB ground Dedicated USB ground
P6 P7 P15
(4)
T1 U3 T3 T2 M3 M4 N3 N4 P5 P2 P1 M5 L4 L3 K3 J5 J4 H3 R3 M2 K2 H2 R4 P4 P3
Power
vddc_1v2_d vdd_usb vddc_1v2_h1 vddb_1v2_h1 vddl_1v2_h1 vddc_1v2_h0 vddb_1v2_h0 vddl_1v2_h0 vdd3_3v3_d vdde3v3_usb vdd3_3v3_h1 vdd3_3v3_h0 vssl_3v3_d vssb_1v2_d vssc_1v2_d
11/16
Pin description Table 3.
Group
SPEA R-09-H042 Power connections (continued)
Signal Name gnde_usb gnd_usb vssc_1v2_h1 vssb_1v2_h1 vssb_1v2_h0 vssc_1v2_h0 vssl_3v3_h0 vssl_3v3_h1 Ball M1 L5 K5 K4 H4 J3 H1 K1 Function Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground
1. Signal spread on the following balls: H11, J08, J09, J13, J14, K14, M14, N14, P14. 2. Signal spread on the following balls: H10, J07, J12, L14, N05, P09, P13. 3. Signal spread on the following balls: J10, J11, K06 to K13, L06 to L13, M06 to M13, N08 to N13. 4. Signal spread on the following balls: N06, N07, P08, P10 to P12.
12/16
SPEAR-09-H042
Pin description
3.3
Figure 1.
Ballout top view
Ballout top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G P _ IO [ 2 1 P _ IO [ 3 3 P _ IO [ 2 2 P _ IO [ 2 3 P _ IO [ 3 5 P _ IO [ 4 2 P _ IO [ 5 0 P _ IO [ 5 2 P _ IO [ 6 0 P _ IO [ 6 7 P _ IO [ 7 5 P _ IO [ 7 7 P _ IO [ 8 7 T E S T 0 ] ] ] ] ] ] ] ] ] ] ] ] ]
S M IN C S M IN C S M IN C S[ 3 ] S[ 2 ] S [ 1]
A
B
e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G S M ID A S M IN C S M IC L S M ID A P _ IO [ 17 P _ IO [ 3 0 P _ IO [ 3 2 P _ IO [ 19 P _ IO [ 2 8 P _ IO [ 4 1 P _ IO [ 4 7 P _ IO [ 5 1 P _ IO [ 5 9 P _ IO [ 6 6 P _ IO [ 7 3 P _ IO [ 7 9 P _ IO [ 8 9 TA O UT S[ 0 ] K T A IN ] ] ] ] ] ] ] ] ] ] ] ] ] e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G TX_ C L P _ IO [ 14 P _ IO [ 2 4 P _ IO [ 2 6 P _ IO [ 3 4 P _ IO [ 2 7 P _ IO [ 3 7 P _ IO [ 3 9 P _ IO [ 6 2 P _ IO [ 5 8 P _ IO [ 6 5 P _ IO [ 7 2 P _ IO [ 8 1 P _ IO [ 9 1 P _ IO [ 9 7 T X D [ 0 ] T X D [ 1] K ] ] ] ] ] ] ] ] ] ] ] ] ] ] e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G P _ IO [ 10 P _ IO [ 13 P _ IO [ 4 0 P _ IO [ 5 4 P _ IO [ 5 6 P _ IO [ 4 6 P _ IO [ 5 3 P _ IO [ 6 4 P _ IO [ 7 1 P _ IO [ 8 3 P _ IO [ 9 3 P _ IO [ 9 9 T X D [ 2 ] T X D [ 3 ] T X _ E N P _ IO [ 7 ] P _ IO [ 9 ] ] ] ] ] ] ] ] ] ] ] ] ] e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC _ O V E R C O V E R C e A S IC G e A S IC G P _ IO [ 15 P _ IO [ 18 P _ IO [ 4 8 P _ IO [ 4 4 P _ IO [ 4 5 P _ IO [ 6 3 P _ IO [ 7 0 P _ IO [ 8 5 P _ IO [ 9 5 E X T _ C U R H 1 U R H 2 P _ IO [ 8 ] P _ IO [ 5 ] ] ] ] ] ] ] ] ] ] LO C K e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G H O S T 1_ H O S T 2 e A S IC G e A S IC G P _ IO [ 2 5 P _ IO [ 16 P _ IO [ 2 0 P _ IO [ 4 9 P _ IO [ 5 5 P _ IO [ 5 7 P _ IO [ 6 9 V B U S _ V B U S P _ IO [ 4 ] P _ IO [ 6 ] ] ] ] ] ] ] ] P LL_ B YP A SS VB US TD O TD I TM S CRS C OL R X_ C L K
B
C
C
D
D
E
E
F
R X D [ 0 ] R X D [ 1] R X D [ 2 ]
F
G
e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G e A S IC G M R E S E e A S IC G e A S IC G P _ IO [ 3 1 P _ IO [ 12 P _ IO [ 4 3 P _ IO [ 3 8 P _ IO [ 6 1 P _ IO [ 6 8 R T C K T P _ IO [ 0 ] P _ IO [ 11 ] ] ] ] ] ] v dd v dd3 v 3 T E S T 3
TC K
nT R S T R X D [ 3 ] R X _ D V R X _ E R
G
H
e A S IC G e A S IC G v s s l_ 3 v v dd3 _ 3 v ddl_ 1v v s s b_ 1v e A S IC G e A S IC G e A S IC G P _ IO [ 2 9 P _ IO [ 3 6 3 _ h0 v 3 _ h0 2 _ h0 2 _ h0 P _ IO [ 3 ] P _ IO [ 2 ] P _ IO [ 1] ] ] H O S T 2 H O S T 2 v s s c _ 1 v v ddb_ 1 v v ddc _ 1 v R R EF _D P _D M 2 _ h0 2 _ h0 2 _ h0 v s s l_ 3 v v dd3 _ 3 v ddl_ 1v v s s b_ 1v v s s c _ 1v 3 _ h1 v 3 _ h1 2 _ h1 2 _ h1 2 _ h1 H O S T 1 _ H O S T 1 _ v ddb_ 1 v v ddc _ 1 v gnd_ us DP DM 2 _ h1 2 _ h1 b a na v dd a na gnd gnde _ u v dde 3 v v dd_ us _ 3 v 3 _ pll _ 3 v 3 _ pll sb 3 _ us b b 16 0 0 16 0 0 digv dd_ diggnd_ M C LK _ i M C LK _ 1v 2 _ pll1 1v 2 _ pll1 n o ut 600 600 v dd v dd v dd3 v 3 v dd3 v 3
TEST2
TEST1
M DC
M D IO
SD A
H
J
gnd
gnd
v dd
v dd3 v 3 v dd3 v 3
SC L
U A R T 1_ U A R T 1_ TXD R XD
J
K
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
e A S IC _ G P _ IO [ G P _ IO [ v dd3 v 3 P I_ C LO 5] 4] CK v dd G P _ IO [ G P _ IO [ G P _ IO [ 1 3] 2] ] M PM C M PM C G P _ IO [ D A TA [ 1 D A TA [ 1 0] 4] 5]
K
L
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
L
M
gnd
gnd
gnd
gnd
gnd
gnd
gnd
gnd
v dd3 v 3
M
N
v dd2 v 5 v dd2 v 5
gnd
gnd
gnd
gnd
gnd
gnd
M PM C M PM C M PM C v dd3 v 3 D A T A [ 1 D A T A [ 1 D A T A [ 1 1] 2] 3] v dd3 v 3 M PM C M PM C S S T L_ V D A TA [ D A TA [ 1 R EF 9] 0]
N
P
v ddc _ 1v v ddb_ 1v v s s c _ 1v v s s b_ 1v v ddl_ 1v v dd_ dit v s s _ dit v dd2 v 5 2_d 2_d 2_d 2_d 2_d h h
v dd
v dd2 v 5 v dd2 v 5 v dd2 v 5
v dd
P
R
D P LS
DM NS
nM P M M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C v dd3 _ 3 v s s l_ 3 v M PM C M PM C C D YC S A D D R A D D R A D D R A D D R A D D R A D D R D A TA [ 1 D A TA [ D A TA [ D A TA [ v3_d 3_d D Q S [ 0 ] D Q S [ 1] O U T [ 3 ] O U T [ 0 ] O U T [ 3 ] O U T [ 6 ] O U T [ 9 ] O U T [ 12 ] O U T [ 14 ] ] 3] 5] 7]
R
T
v dd1 v 2 _ gnde _ d nM P M nM P M nM P M M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C gnd_ da t da t e _ o s a t e _ o s c C D YC S C D YC S C C A SO A D D R A D D R A D D R A D D R A D D R D A TA [ D A TA [ D A TA [ D A TA [ D Q M O D A TA [ e_o sci ci i O U T [ 1] O U T [ 2 ] UT O U T [ 2 ] O U T [ 5 ] O U T [ 8 ] O U T [ 11 O U T [ 13 ] 0] 2] 4] 6] UT[ 0 ] 8] R TC XI R TC XO nM P M nM P M nM P M M P M C M P M C M P M C M P M C M P M C M P M C nM P M M P M C nM P M M P M C M P M C v dd_ da t C D Y C S C WE O U C R A S O A D D R A D D R A D D R A D D R C K E O U C K E O U C C LK O C LK O U C C LK O C LK O U D Q M O e_o sci O UT[ 0 ] T UT O U T [ 1] O U T [ 4 ] O U T [ 7 ] O U T [ 10 ] T [ 0 ] T [ 1] U T [ 1] T [ 1] UT[ 0 ] T[ 0 ] U T [ 1]
T
U
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
13/16
Package information
SPEA R-09-H042
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. LFBGA289 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 0.350 0.400 0.270 0.985 0.200 0.800 TYP. M AX . 1.700 0.0106 0.0387 0.0078 0.0315 MIN. TYP. MAX. 0.0669 inch
OUTLINE AND MECHANICAL DATA
0.450 0.0137 0.0157 0.0177
14.850 15.000 15.150 0.5846 0.5906 0.5965 12.800 0.5039
14.850 15.000 15.150 0.5846 0.5906 0.5965 12.800 0.800 1.100 0.120 0.150 0.080 0.5039 0.0315 0.0433 0.0047 0.0059 0.0031
Body: 15 x 15 x 1.7mm
LFBGA289 Low profile Fine Pitch Ball Grid Array
8077927 B
14/16
SPEAR-09-H042
Revision history
5
Revision history
Table 4.
Date 31-Jan-2008
Document revision history
Revision 1 Initial release. Changes
15/16
SPEAR-09-H042
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
16/16
|
