STEVAL-PSQ001V1
Power management for CPU, FPGA and memory based on the PM6680A
Data Brief
Features
Input: 5 - 36 VDC, surge protection Output voltages: Output1 (Vcore) selectable from: 0.9, 1.0, 1.2, 1.5, 1.8 or 2.5 V, 4 A continuously (6 A peak), tolerance: 3% Output2 (Vi/o) selectable from: 1.0, 1.2, 1.5, 1.8, 2.5 V or 3.3 V, 2 A continuously (3 A peak), tolerance: 3% Output3 Vsys: 3.3 V 0.4 A (0.8 A peak), tolerance: 4% Output3 Vaux: 2.5 V, 0.4 A, tolerance: 2% Analog 5: 5 V, 0.8 A, tolerance: 4% Analog 3.3 V: 3.3 V, 0.15 A, tolerance: 2% STEVAL-PSQ001V1 reset. This limit is typically 3 or 5 %. On the other hand, digital device consumption can change very fast (approx. several amps in several hundred nanoseconds). The power supply must be capable of reacting very quickly with a minimum of over/under voltage, especially in cases where very low voltage output is required. There is additional stress placed on power supplies in digital applications for industrial use. The industrial standard bus is 24 V, but this voltage fluctuates and the maximum required input voltage level can be up to 36 V. Additional surge protection is also mandatory for power supply input in industrial applications. The purpose of this evaluation board is to address all of required parameters outlined above. This means satisfying industrial input requirements (operating voltage of up to 36 V) and generating several output voltages for middle power applications (up to several amps). The main output voltage level can be set easily.
Description
The main purpose of this evaluation board is to show basic principles used for design of the power supply and to give users a working prototype for testing and daily use. The trend in recent years in the supply of MCUs, CPUs, memories, FPGAs etc. is to reduce the supply voltage, increase supply current and provide various voltage levels for different devices in one platform. A typical example of this is the FPGA. FPGAs contain core parts which operate with low level voltage, interface parts placed between the core and the output, system parts, etc. It is important to note that each family of parts has a slightly different voltage level and the trend is toward decreasing voltage for each new family. The lowest operating voltage currently is 1 V, and this can be expected to drop to 0.9 V or 0.8 V in the near future. The situation is similar with other parts of digital solutions. Typically, the main CPU, memory, and interfaces require different supply voltage levels. Low operating voltage also bring another challenge - transient. Digital devices are typically sensitive to voltage level. If voltage drops below or crosses over established limits, the device is
Februar y 2008
Rev 1
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For further information contact your local STMicroelectronics sales office.
1
SYNC
GND
VREF
INH
2
6
7
C2 4.7u/35V
3
VREF
SY SYNC
GND
INH INH
C11 100u/6V D6 STPS2L40
D6A STPS1L40M
2
6
7
C8 4.7u/35V
C10 22n
36V
2 3 6 7
C9 220p
3
R8 10k
C12 100n
GND GND GND GND GND
C 15 470n C17 100n
MR
C32 1n C33 1n
C14 4.7u/10V
C1 6 3.3u/35V
2
Vss
Vin
Vcc
Vio 0.9 - 2.5V/2A S34 S35 3
R23 10R
4
HGATE2
10
LDO5
C18 10u/50V
9 BOOT2 BOOT1 23
6 5
C1 9 100n
31 31 18 19
EN2
EN1
VREF
SKIP
FSEL
R107 9k1
Vin VLDO
NC
4
3
25
32
24
6
3
S32 S33
2
2
1
2/4
Vin
U1 L5970AD
Circuit schematic
J16
L1 15uH/1.5A
OUT
U2 LK112_33 5 IN 3.3V/150mA SHDN BYPASS GND OUT 4
Figure 1.
2
8 Vcc
1 5
V5V
S18
1
4 COMP
D3
FB
R2 120k R3 20k C5 47uF/10V C6 100n
3 2 1
5V/400mA S19
R1 4k7
C7 10u/6V
S20 GND Analog
Input
C1 47uF/50V
36V L 5 1 0 u H /1 A
C3 220p
C4 22n
D4 STPS2L40
D4A STPS1L40M
R4 5k6
R41
D1 SMAJ33A
S1 Vanalog EN
Vin
5k6
U3 L5970AD L2 15uH/1.5A OUT FB 5
VIN INH VOUT
Schematic
8 Vcc COMP
8 5 1
1
Vsys
S2 1 Vsys 3.3V/400mA S 22
Vaux
4
R6 18k
R7 240k
U4 KF25_SOIC8
D5
R5 10k
Vaux 2.5V/400mA
C13 10u/4V
S23 GND
Circuit schematic
R42
S2 Vsys EN VLDO Vin
5k6
VLDO
Vaux
FB2R
Vin
U6 STM6719TEWB6F 6
R9 3R3
Vcc1 4 5 3 Vcc2
RST RSTIN
1
R209 110k
J 1 4 Re s e t
BAW56/SOT
R3 7 4 7 R
J15
Reset GND
Vin
C31 220n
D7
R26 10R
Vin
D11
PGOOD2
STPS2L40
Q1
R2 5 10R C25 100n2 Q
STS7NF60L
HGATE1 PHASE1 LGATE1 CSENSE1 PGND OUT1 COMP1 PGOOD1 30 26 29 14 20 R1 9 1 k 2 15 21
R21 10R
22
C23 10u/50V
C24 10u/50V
11 PHASE2 LGATE2 13
8 7 1
17 V5SW OUT2
S8 0.9V
S9 1V
S10 1.2V
2
CSENSE2
R24 10R R10 1k2
S11 1.5V
12
S12 1.8V
R22 10R
D9 Q3 STS7NF60L
3.3uH/6A L4 C 34
S17 2.5V
S16 1.8V
S15 1.5V
S14 1.2V
Vcore 0.9 - 2.5V/4A S24 S25 S26 S27 S13 1V
R101 1k
R 1 0 2 2k
R103 3k
STS4DNF60
2 COMP2 PGOOD2 FB2
8
R104 3k
R105 R106 7k5 110k
L3 4.7uH/3A C3 5 D8 STPS2L40 R40 10R 100n R3 9 1 0 R
R27 10R STPS2L40
C2 9 330u/6.3V
100n R38 10R
C22 330u/6.3V
C28 330u/6.3V
R32 10k C26 560pF R20 300R
R206 R205 110k 7k5
R 2 0 4 3k
R203 3k
R202 2k
R201 1k
R11 30 0 R PGOOD2
27 7
VLDO
C20 5 6 0 pF
R28 10k
FB1
C 21 10 0p F
U5 PM6680 R30 0R
5 SHDN
FB1 SGND1 SGND2
28 1 16
R33 0R VLDO
VLDO
FB2 C27 100pF
R 2 07 2k2
FB2R
R108 820k
R29 100k
S5
S6
S7
R208 6 k8
GND io
D10 C36 100pF
S3 CH2 EN/SUS 1
R31 10k R34 10k R35 51 k
S31 S30 S29 S28 Vcore GND
S4 3 CH1 EN/SUS
R36 51k
SKIP mode
4V7
STEVA L-PSQ001V1
C3 0 100n
STEVAL-PSQ001V1
Revision history
2
Revision history
Table 1.
Date 18-Feb-2008
Document revision history
Revision 1 Initial release. Changes
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STEVAL-PSQ001V1
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