STEVAL-ISA053V2
Demonstration board for the PM6680A dual synchronous step-down controller with adjustable output voltages plus LDO
Data Brief
Features
Constant on-time control allows very fast load transients 6 V to 36 V input voltage range 5 V auxiliary output voltage Adjustable switching outputs Lossless current sensing Negative current limit Soft-start internally fixed at 2.8 ms Soft-end for output discharge 200 kHz / 300 kHz, 300 kHz / 400 kHz, 400 kHz / 500 kHz (OUT1 / OUT2 selectable switching frequency) Selectable pulse skip and no-audible skip modes at light loads Independent power good signals STEVAL-ISA053V2
Description
The PM6680A is a dual step-down controller with adjustable output voltages. This demonstration board is designed to test the performance of the PM6680A by employing a typical application circuit which allows testing of all the PM6680A device functions. The kit features two switching sections, with (typically) 3.3 V and 1.8 V outputs, from a 6 V to 36 V input voltage. The typical operating switching frequency of the two switching sections is 200 kHz / 300 kHz, respectively. Each switching section delivers more than 2.5 A of output current. Moreover, an internal linear regulator can provide 5 V @ 100 mA peak current.
June 2008
Rev 1
1/4
www.st.com 4
For further information contact your local STMicroelectronics sales office.
1
31
18
NM C14
19
8 7 6 5
2
VIN
VCC
OUT5V M2 MOSFET-N-SO8 R22
NM
NM
C6 100n 10R
5 6 7 8
LDO LDO5
S5 JP2SO
23 BOOT1
R20
Circuit schematic
J4
L2
4
L1
BOOT2 4 1 2 3 1 5 6 7 8
3V3 R18 560K
9 10
0R
C5 100n M1 MOSFET-N-SO8
NM
NM
2
1
3 2 1
1 8 7 6 5
5V M4 MOSFET-N-SO8
2 21 PHASE1 PHASE2 13 1 1 2 3 12 14
PGND SGND R7 500R R21 0R R23
1 11 4
M3 MOSFET-N-SO8 D3 SMA
HGATE1
HGATE2
1
1
Schematic diagram
OUT1+
3
1
3
1
3 2 1
2
C25 100n
330uF
330uF
D2 SMA 0R
20 CSENSE1 V5SW PGND SGND OUT2 COMP2 FB2 FB1 LDO 7
S13 2
CSENSE2
2
2
500R C10 100n V5SW OUT5V
17 29 OUT1 COMP1 LDO_FB PGOOD1 PGOOD2 SHDN 28
JP2SO 1 FB1
C9 100n
2
EN2
EN1
VREF
SKIP
R17 560K
FSEL
4
25
32
24
3
8 7 6 5
2
3
4
2
3
1 2 3 4
CREF 100n
S10 JP4I
4
1
OUT5V
EXT5V
SGND SGND
1
2/4
Circuit schematic
Figure 1.
J3 LDO5V+ VIN R26
D1
V+
1
2
BOOT1
VIN V+
+
NM R9 47R C20 1uF C21 4u7 RLD5V 100K C19 100n C1 15u C2 15u
+
3R9 C26 4u7
+ CIN
J5 +VIN
3 1
BOOT2
1
SGND PGND PGND R5 R11 U1 BOOT2 R3 NM C13 PGND C22 SGND V+ 220nF SGND SGND SGND PGND
J2 -VIN
C3 15u
C4 15u
BAT54A/SOT
R6 SGND PGND R10 BOOT1 R4 10R PGND
S4 JP2SO J1
0R
22
2
1
OUT2+ C24 100n
S9 JP3SO
4 LGATE1 LGATE2
R8
15
+ C7
NM
+ C8
NM
S8 JP3SO
+ C11
+ C12
R19 560K
J9
J8
1 1 8
C15 LDO_FB OUT2PGND R25
1 30 16 26 27 5 6
S12 2 JP2SO 1
OUT1-
PGND
2
150pF C17 NM LIKE 4-PIN JUMPER A - S12 CLOSED B - S14 CLOSED C - S12.1 TO S14.2 SGND 1K PGND R30 ? J10
R24 C16 V+ 100pF C18 NM J6 PGOOD1 J7 PGOOD2 C27 1uF V+ R13 100K R12 100K
1
PGND
1K
R28 ? SGND
VIN
+
C28 4u7 R33 ? R32 ? SGND PM6681_VFQFPN32 LDO_FB S1 SGND SGND
FB1
1
LDO_ADJ
R29 ?
R27 ?
1 2 3
JP3SO SGND R31 ? V+
SGND
SGND C23 10pF R16 100K V+ 100K R14
V+
100K
R15
SGND SGND
S2 SWDIP-4
SGND
S3 JP4I
STEVAL-ISA053V2
V5SW
J11
STEVAL-ISA053V2
Revision history
2
Revision history
Table 1.
Date 06-June-2008
Document revision history
Revision 1 Initial release. Changes
3/4
STEVAL-ISA053V2
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