STE40NK90ZD
N-channel 900V - 0.14 - 40A ISOTOP Super FREDmeshTM MOSFET
General features
Type STE40NK90ZD
VDSS 900V
RDS(on) <0.18
ID 40A
Pw 600W
Extremely high dv/dt capability 100% avalanche tested Very low intrinsic capacitances Very good manufacturing repeatibility
ISOTOP
Description
The SuperFREDMeshTM series is obtained through an extreme optimization of ST's well established strip-based PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STE40NK90ZD Marking E40NK90ZD Package ISOTOP Packaging TUBE
July 2006
Rev 5
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Contents
STE40N K90ZD
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Protection features of gate-to-source zener diodes . . . . . . . . . . . . . . . . . . 5 Electrical characteristics (curves) . . .. . .. . .. . .. . .... 6
3 4 5
Test circuit
. . .. . .. . .. . .. . .. . .. . .. . .. . .... 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STE40NK90ZD
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VDGR VGS ID ID IDM(1) PTOT
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Drain-gate voltage (RGS = 20 k) Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor Value 900 900 30 40 25 160 600 5 7 8 2500 - 65 to 150 Unit V V V A A A W W/C KV V/ns V C
VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5K) dv/dt
(2)
Peak diode recovery voltage slope Insulation withstand voltage (AC-RMS) from all four terminals to external heatsink Operating junction temperature Storage temperature
VISO Tj Tstg
1. Pulse width limited by safe operating area 2. ISD 40A, di/dt 500 A/s, VDD V(BR)DSS
Table 2.
Rthj-amb
Thermal data
0.2 40 C/W C/W Thermal resistance junction-ambient max
Rthj-case Thermal resistance junction-case max
Table 3.
Symbol IAR EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (star ting Tj = 25 C, ID = IAR, VDD = 35 V) Max. Value 40 1.2 Unit A J
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Electrical characteristics
STE40NK90ZD
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1 mA, VGS = 0 VDS = max rating VDS = max rating, TC = 125 C VGS = 20V VDS = VGS, ID = 150A VGS = 10V, ID = 20A 2.5 3.75 0.14 Min. 900 10 100 10 4.5 0.18 Typ. Max. Unit V A A A V
IDSS
IGSS VGS(th) RDS(on)
Table 5.
Symbol gfs (1) Ciss Coss Crss Coss eq. (2) td(on) tr td(off) tf Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 15V, ID = 20A Min. Typ. 35 25000 1450 280 720 92 102 450 200 590 89 323 826 Max. Unit S pF pF pF
VDS = 25V, f = 1 MHz, VGS = 0 VGS = 0V, VDS = 0V to 720V VDD = 450V, ID = 18A RG = 4.7 , VGS = 10V (Figure 14)
pF ns ns ns ns nC nC nC
VDD = 720 V, ID = 36A, VGS = 10V
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
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STE40NK90ZD
Electrical characteristics
Table 6.
Symbol ISD ISDM (1) VSD (2) t rr Qrr IRRM t rr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 40A, VGS = 0 450 3.6 16.2 930 12 26 Test conditions Min. Typ. Max. 40 160 1.6 Unit A A V ns C A ns C A
Reverse recovery time ISD = 36A, di/dt = 100A/s Reverse recovery charge VDD = 50V, Tj = 25C Reverse recovery current (see Figure 16) Reverse recovery time ISD = 36A, di/dt = 100A/s Reverse recovery charge VDD = 50V, Tj = 150C Reverse recovery current (see Figure 16)
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
Table 7.
Symbol BVGSO
Gate-source zener diode
Parameter Test conditions Min. 30 Typ. Max. Unit V
Gate-source breakdown Igs= 1mA (open voltage drain)
2.1
Protection features of gate-to-source zener diodes
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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Electrical characteristics
STE40NK90ZD
2.2
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
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STE40NK90ZD Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized BVDSS vs temperature
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Electrical characteristics Figure 13. Avalanche energy vs starting Tj
STE40NK90ZD
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STE40NK90ZD
Test circuit
3
Test circuit
Figure 15. Gate charge test circuit
Figure 14. Switching times test circuit for resistive load
Figure 16. Test circuit for inductive load Figure 17. Unclamped Inductive load test switching and diode recovery times circuit
Figure 18. Unclamped inductive waveform
Figure 19. Switching time waveform
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Package mechanical data
STE40NK90ZD
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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STE40NK90ZD
Package mechanical data
ISOTOP MECHANICAL DATA
DIM. MIN. A B C D E F G H J K L M N O 11.8 8.9 1.95 0.75 12.6 25.15 31.5 4 4.1 14.9 30.1 37.8 4 7.8 8.2 4.3 15.1 30.3 38.2 mm TYP. MAX. 12.2 9.1 2.05 0.85 12.8 25.5 31.7 MIN. 0.466 0.350 0.076 0.029 0.496 0.990 1.240 0.157 0.161 0.586 1.185 1.488 0.157 0.307 0.322 0.169 0.594 1.193 1.503 inch TYP. MAX. 0.480 0.358 0.080 0.033 0.503 1.003 1.248
G O B
A
N
D E F
J K L M
H
C
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Revision history
STE40NK90ZD
5
Revision history
Table 8.
Date 24-May-2005 10-Jun-2005 28-Sep-2005 14-Oct-2005 12-Jul-2006
Revision history
Revision 1 2 3 4 5 First Release Inser ted new row in Table 6.: Switching times Complete version Modified Figure 3, Figure 6 New template, no content change Changes
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STE40NK90ZD
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