STS8DNH3LL
Dual n-channel 30 V - 0.018 - 8 A - SO-8 low gate charge STripFETTM III Power MOSFET
Features
Type STS8DNH3LL
VDSS 30 V
RDS(on) max < 0.022
ID 8A
Optimal RDS(on) x Qg trade-off @ 4.5 V Conduction losses reduced Switching losses reduced
S0-8
Application
Switching applications
Description
This product utilizes the latest advanced design rules of ST's proprietary STripFETTM technology which is suitable for the most demanding DC-DC converter applications where high efficiency is required. Figure 1. Internal schematic diagram
Table 1.
Device summary
Order code Marking 8DH3LL Package SO-8 Packaging Tape & reel
STS8DNH3LL
June 2008
Rev 2
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www.st.com 12
Contents
STS8D NH3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . .. . .. . .. . .. . .. 6
3 4 5
Test circuit
. . .. . .. . .. . .. . .. . .. . .. . .. . .... 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STS8DNH3LL
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID ID IDM
(1)
Absolute maximum ratings
Parameter Drain-source voltage (vGS = 0) Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Single pulse avalanche energy Value 30 16 8 5 32 2 100 Unit V V A A A W mJ
PTOT EAS(2)
1. Pulse width limited by safe operating area 2. Starting TJ = 25 C, ID = 6 A
Table 3.
Symbol Rthj-a (1) TJ Tstg
Thermal data
Parameter Thermal resistance junction-ambient max Thermal operating junction-ambient Storage temperature Value 62.5 150 -55 to 150 Unit C/W C C
1. When mounted on 1 inch² FR-4 board, 2 oz. Cu., t 10s
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Electrical characteristics
STS8DNH3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source Breakdown voltage Zero gate voltage Drain current (VGS = 0) Zero gate voltage Drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS = 0 VDS = Max rating VDS =Max rating @125C VGS = 16 V VDS = VGS,ID = 250 A VGS = 10 V, ID = 4 A VGS = 4.5 V, ID = 4 A 1 0.018 0.020 0.022 0.025 Min. 30 1 10 100 Typ. Max. Unit V A A nA V
Table 5.
Symbol gfs Ciss Coss Crss Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge VDS = 25 V, f = 1 MHz, VGS = 0 Test conditions VDS = 15 V, ID = 4 A Min. Typ. 8.5 857 147 20 VDD = 15 V, ID = 8 A, VGS = 4.5 V (see Figure 14) 7 2.5 2.3 10 Max. Unit S pF pF pF nC nC nC
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STS8DNH3LL Table 6.
Symbol td(on) tr td(off) tf
Electrical characteristics Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=15 V, ID=4 A, RG=4.7 , VGS= 4.5 V (see Figure 16) VDD=15 V, ID=4 A, RG=4.7 , VGS= 4.5 V (see Figure 16) Min. Typ. 12 14.5 23 8 Max. Unit ns ns ns ns
Table 7.
Symbol ISD ISDM (1) VSD (2) t rr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Test conditions VDD=15 V, ID=4 A, RG=4.7 , VGS= 4.5 V VDD=15 V, ID= 4A , RG=4.7 VGS=4.5 V ISD = 8 A, VGS = 0 15 5.7 0.76 Min Typ. Max 8 32 1.5 Unit A A V ns nC A
ISD = 8 A,VDD = 15 V Reverse recovery time di/dt = 100 A/s, Reverse recovery charge T = 150C Reverse recovery current j (see Figure 15)
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5%
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Electrical characteristics
STS8DNH3LL
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area Figure 3. Thermal resistance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Static drain-source on resistance
Figure 7.
Normalized BVDSS vs temperature
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STS8DNH3LL Figure 8. Gate charge vs gate-source voltage Figure 9. for Q1
Electrical characteristics Capacitance variations
Figure 10. Normalized gate threshold voltage vs temperature for Q1
Figure 11. Normalized on resistance vs temperature
Figure 12. Source-drain diode forward characteristics
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Test circuit
STS8D NH3LL
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
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STS8DNH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STS8DNH3LL
SO-8 MECHANICAL DATA
DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP M AX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. M AX . 0.068 0.009 0.064 0.033 0.018 0.010 0.019
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STS8DNH3LL
Revision history
5
Revision history
Table 8.
Date 15-Jun-2004 16-Jun-2008
Document revision history
Revision 1 2 First release Modified marking Changes
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STS8DNH3LL
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