STSJ50NH3LL
N-channel 30 V - 0.008 - 12 A - PowerSO-8TM ultra low gate charge STripFETTM Power MOSFET
Features
Type STSJ50NH3LL
VDSS 30V
RDS(on) (max) < 0.0105
ID 12A(1)
Optimal RDS(on) x Qg trade-off @ 4.5V Reduced switching losses Reduced conduction losses Improved junction-case thermal resistance
PowerSO-8TM
Applications
Switching application Figure 1. Internal schematic diagram
Description
This series utilizes the latest advanced design rules of ST's proprietary STripFETTM technology, and a propriertary process for integrating a monolithic Scottky diode. The new Power MOSFET is optimized for the most demanding synchronous switch function in DC-DC converter for computer and telecom.
Drain contact also on the backside
Table 1.
Device summary
Order code Marking 50H3LLPackage PowerSO-8 Packaging Tape & reel
STSJ50NH3LL
December 2007
Rev 6
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www.st.com 13
Contents
STSJ50NH3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . .. . .. . .. . .. . ..... 6
3 4 5
Test circuit
. . .. . .. . .. . .. . .. . .. . .. . .. . .... 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STSJ50NH3LL
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS(1) VGS(2) ID(4) ID(3) ID(4) ID(3) IDM(5) PTOT TJ Tstg
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC=25C Drain current (continuous) at TC=100C Drain current (continuous) at TC=100C Drain current (pulsed) Total dissipation at TC = Total dissipation at TC = 25C (4) Operating junction temperature Storage temperature 25C (3) Value 30 16 18 50 12 31.3 7.5 48 3 50 -55 to 150 Unit V V V A A A A A W W C
1. Continuous mode 2. Guaranteed for test time < 15ms 3. This value is rated accordingly to Rthj-pcb 4. This value is rated accordingly to Rthj-c 5. Pulse width limited by safe operating area
Table 3.
Symbol Rthj-c Rthj-pcb
(1)
Thermal resistance
Parameter Thermal resistance junction-case Max Thermal resistance junction-pcb Max Value 2.5 42 Unit C/W C/W
1. When mounted on 1 inch² FR-4 board, 2oz Cu (t<10sec.)
Table 4.
Symbol IAV EAS
Avalanche data
Parameter Not repetitive avalanche current Single pulse avalanche energy (starting Tj=25 C, ID=7.5 A) Value 7.5 150 Unit A mJ
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Electrical characteristics
STSJ50NH3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 5.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = Max rating VDS = Max rating TC=125C VGS = 16 V VDS= VGS, ID =250 A VGS= 10 V, ID= 6 A VGS= 4.5 V, ID= 6 A VGS= 10 V, ID= 6 A @125C VGS= 4.5 V, ID= 6 A @125C 1 0.008 0.010 0.012 0.016 0.0105 0.013 Min. 30 1 10
100
Typ.
Max.
Unit V A A nA V
RDS(on)
Table 6.
Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Gate input resistance Test conditions VDS =10 V, ID = 12 A Min. Typ. 38 965 285 38 9 3.7 3 0.5 1.5 12 Max. Unit S pF pF pF nC nC nC
VDS =25 V, f=1 MHz, VGS=0
VDD=15 V, ID =12 A VGS =4.5V,(see Figure 16) f=1 MHz Gate DC Bias=0 Test signal level =20 mv open drain
2.5
1. Pulsed: pulse duration=300s, duty cycle 1.5%
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STSJ50NH3LL
Electrical characteristics
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Test conditions VDD=15 V, ID=6 A, RG=4.7 , VGS=4.5 V (see Figure 15) VDD=15 V, ID=6 A, RG=4.7 , VGS=4.5 V (see Figure 15) Min. Typ. 15 32 Max. Unit ns ns
Turn-off delay time Fall time
18 8.5
ns ns
Table 8.
Symbol ISD ISDM(1) VSD(2) trr Q rr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD=12 A, VGS=0 ISD=12 A, di/dt = 100 A/s, VDD=20 V, Tj=150 C (see Figure 20) 24 17.4 1.45 Test conditions Min. Typ. Max. 12 48 1.3 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
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Electrical characteristics
STSJ50NH3LL
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area Figure 3. Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Transconductance
Figure 7.
Static drain-source on resistance
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STSJ50NH3LL Figure 8. Gate charge vs gate-source voltage Figure 9.
Electrical characteristics Capacitance variations
Figure 10. Normalized gate threshold voltage vs temperature
Figure 11. Normalized on resistance vs temperature
Figure 12. Source-drain diode forward characteristics
Figure 13. Normalized BVDSS vs temperature
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Electrical characteristics Figure 14. Allowable Iav vs time in avalanche
STSJ50NH3LL
The previous curve gives the single pulse safe operating area for unclamped inductive loads under the following conditions: PD(AVE) =0.5*(1.3*BVDSS *IAV ) EAS(AR) =PD(AVE) *tAV Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalanche (single pulse) tav is the time in avalanche
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STSJ50NH3LL
Test circuit
3
Test circuit
Figure 16. Gate charge test circuit
Figure 15. Switching times test circuit for resistive load
Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test switching and diode recovery times circuit
Figure 19. Unclamped inductive waveform
Figure 20. Switching time waveform
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Package mechanical data
STSJ50NH3LL
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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STSJ50NH3LL
Package mechanical data
PowerSO-8TM MECHANICAL DATA
mm. MIN. 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 2.79 3.8 0.4 4.0 1.27 0.6 8 (max.) 0.1 4 0.01 5 TY P MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 5.0 6.2 0.18 8 0.22 8 0.0 50 0.1 50 0.1 10 0.1 57 0.0 50 0.0 23 0.1 96 0.2 44 0.02 5 0.01 3 0.00 7 0.01 0 0.00 3 MI N. inch TYP. MAX. 0.0 68 0.0 09 0.0 64 0.0 33 0.0 18 0.0 10 0.0 19
DIM. A a1 a2 a3 b b1 C c1 D E e e3 e4 F L M S
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Revision history
STSJ50NH3LL
5
Revision history
Table 9.
Date 21-Jul-2004 24-May-2005 23-Jun-2005 16-Nov-2005 30-Mar-2006 10-Dec-2007
Document revision history
Revision 1 2 3 4 5 6 Initial release. New value on Table 7 New Rg value on Table 7 Complete version New template Updated data on Table 4: Avalanche data Changes
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STSJ50NH3LL
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