L6563 L6563A
Advanced transition-mode PFC controller
Features
Very precise adjustable output overvoltage protection Tracking boost function Protection against feedback loop failure (Latched shutdown) Interface for cascaded converter's PWM controller Input voltage feedforward (1/V2) Inductor saturation detection (L6563 only) Remote ON/OFF control Low ( 90A) start-up current 5mA max. quiescent current 1.5% (@ TJ = 25C) internal reference voltage -600/+800 mA totem pole gate driver with active pull-down during UVLO SO14 package Block diagram
INV 1
TRACKING BOOST
SO-14
Applications
PFC pre-regulators for:
HI-END AC-DC adapter/charger Desktop PC, server, WEB server IEC61000-3-2 OR JEIDA-MITI compliant SMPS, in excess of 350W
Table 1. Device summary
Part number L6563 L6563TR L6563A L6563ATR Package SO-14 SO-14 SO-14 SO-14 Packaging Tube Tape & Reel Tube Tape & Reel
Figure 1.
COMP 2
MULT 3 Ideal diode
VFF 5 1/V2
TBO
6
1:1 CURRENT MIRROR 1:1 BUFFER
2.5V + Voltage references Vbias
( INTERNA L SUPPLY BUS)
MULTIPLIER
LINE VOLTAGE FEEDFORWARD
3V
from VFF
VOLTAGE REGULATOR
1.7V + INDUCTOR SATURATION DETECTION ( not in L6563A )
LEADING-EDGE BLANKING
4 CS
+ Q VCC
SAT
VCC
14 R R1 UVLO COMPARATOR + R2 VREF2 UVLO S
Q
15 V 13 GD Driver
GND
12
11 ZCD 10 RUN 1.4V 0.7V -
ZERO CURRENT DETECTOR
Starter OFF STARTER + 0.2V 0.26V PFC_OK 7
DISABLE 0.52V 0.6V ON/OFF CONTROL (BROWNOUT DETECTION) +
LATCH
SAT
9 PWM_STOP
8 PWM_LATCH
March 2007
Rev 4
-
Vbias
FEEDBACK FAILURE PROTECTION
-
+
+ 2.5V
1/39
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Contents
L6563 - L6563A
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 3 4 5 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Feedback Failure Protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Tracking Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Inductor saturation detection (L6563 only) . . . . . . . . . . . . . . . . . . . . . . . . 27 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 28 Summar y of L6563/A idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 8 9
Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2/39
L6563 - L6563A
Description
1
Description
The device is a current-mode PFC controller operating in Transition Mode (TM). Based on the core of a standard TM PFC controller, it offers improved performance and additional functions. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @TJ = 25C) internal voltage reference. The stability of the loop and the transient response to sudden mains voltage changes are improved by the voltage feedforward function (1/V2 correction). Additionally, the IC provides the option for tracking boost operation (where the output voltage is changed tracking the mains voltage). The device features extremely low consumption ( 90 A before start-up and 5 mA running). In addition to an effective two-step OVP that handles normal operation overvoltages, the IC provides also a protection against feedback loop failures or erroneous output voltage setting. In the L6563 a protection is added to stop the PFC stage in case the boost inductor saturates. This function is not included in the L6563A. This is the only difference between the two part numbers. An interface with the PWM controller of the DC-DC converter supplied by the PFC preregulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core saturation) in the L6563 only and to disable the PFC stage in case of light load for the DCDC converter, so as to make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote ON/OFF control both in systems where the PFC pre-regulator works as a master and in those where it works as a slave. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable to drive high current MOSFETs or IGBTs. This, combined with the other features and the possibility to operate with the proprietary Fixed-Off-Time control, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W. Figure 2. Typical system block diagram
PFC PRE-REGULATOR DC-DC CONVERTER
Vinac
Voutdc
PWM is turned off in case of PFC's anomalous operation for safety
L6563 L6563A
PWM or Resonant CONTROLLER
PFC can be turned off at light load to ease compliance with energy saving regulations.
3/39
Description
L6563 - L6563A
1.1
Pin connection
Figure 3. Pin connection (top view)
INV COMP MULT CS VFF T BO PFC_OK
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc GD GND ZCD RUN PWM_ST OP PWM_LAT CH
1.2
Pin description
Table 2. Pin description
Pin N Name Description Inver ting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to change the output voltage so that it tracks the mains voltage. Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET's turn-off. A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, shuts down the IC, reduces its consumption almost to the start-up level and asserts PWM_LATCH (pin 8) high. This function is not present in the L6563A. Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak voltage at pin MULT (pin 3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND.
1
INV
2
COMP
3
MULT
4
CS
5
VFF
4/39
L6563 - L6563A Table 2. Pin description (continued)
Pin N Name Description
Description
6
TBO
Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected between this pin and GND defines a current that is sunk from pin INV (pin 1). In this way, the output voltage is changed proportionally to the mains voltage (tracking boost). If this function is not used leave this pin open. PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high. Normal operation can be resumed only by cycling the Vcc. This function is used for protection in case the feedback loop fails. If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V.
7
PFC_OK
8
Output pin for fault signaling. During normal operation this pin features high impedance. If either a voltage above 2.5V at PFC_OK (pin 7) or a voltage above 1.7V on CS (pin 4) of PWM_LATCH L6563 is detected the pin is asserted high. Normally, this pin is used to stop the operation of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of its PWM controller. If not used, the pin will be left floating. Output pin for fault signaling. During normal operation this pin features high impedance. If the IC is disabled by a voltage below 0.5V on RUN (pin 10) the voltage at the pin is pulled PWM_STOP to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC converter supplied by the PFC pre-regulator by disabling its PWM controller. If not used, the pin will be left floating. Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC restarts as the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin 5) either directly or through a resistor divider to use this function as brownout (AC mains undervoltage) protection, tie to INV (pin 1) if the function is not used. Boost inductor's demagnetization sensing input for transition-mode operation. A negativegoing edge triggers MOSFET's turn-on. Ground. Current return for both the signal part of the IC and the gate driver. Gate driver output. The totem pole output stage is able to drive power MOSFET's and IGBT's with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages. Supply Voltage of both the signal part of the IC and the gate driver.
9
10
RUN
11 12 13 14
ZCD GND GD VCC
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Absolute maximum ratings
L6563 - L6563A
2
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol VCC ----IPWM_STOP IZCD PTOT TJ TSTG Pin 14 Parameter IC supply voltage (Icc = 20mA) Value self-limited -0.3 to 8 Self-limited 3 -10 (source) 10 (sink) 0.75 -25 to 150 -55 to 150 Unit V V V mA mA W C C
2, 4 to 6, 8 Analog inputs & outputs to 10 1, 3, 7 10 9 Max. pin voltage (Ipin = 1 mA) Max. sink current Zero current detector max. current Power dissipation @TA = 50C Junction temperature operating range Storage temperature
3
Thermal data
Table 4. Thermal data
Symbol RthJA Parameter Maximum thermal resistance junction-ambient Value 120 Unit C/W
6/39
L6563 - L6563A
Electrical characteristics
4
Electrical characteristics
Table 5. Electrical characteristics ( -25C < TJ < +125C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1F between pin VFF and GND; unless otherwise specified)
Symbol Supply voltage Vcc VccOn VccOff Hys VZ Operating range Turn-on threshold Turn-off threshold Hysteresis Zener Voltage Icc = 20 mA After turn-on
(1) (1)
Parameter
Test condition
Min
Typ
Max
Unit
10.3 11 8.7 2.3 22 25 12 9.5
22 13 10.3 2.7 28
V V V V V
Supply current Istar t-up Iq ICC Star t-up current Quiescent current Before turn-on, Vcc = 10V After turn-on 50 3 3.8 180 1.5 2 90 5 5.5 250 2.2 3 A mA mA A mA mA
Operating supply current @ 70kHz Latched by PFC_OK > Vthl or Vcs > VCSdis Disabled by PFC_OK < Vth or RUN < VDIS During static/dynamic OVP
Iqdis
Idle state quiescent Current
Iq
Quiescent current
Multiplier input IMULT VMULT VCLAMP V c ---------------s---- V M U L T KM Input bias current Linear operation range Internal clamp level Output max. slope IMULT = 1 mA VMULT=0 to 0.5V, VFF=0.8V VCOMP = Upper clamp VMULT = 1 V, VCOMP= 4 V, VVFF = VMULT VMULT = 0 to 3 V 0 to 3 9 2.2 9.5 2.34 -0.2 -1 A V V V/V
Gain (3)
0.375
0.45
0.525
V
Error amplifier VINV Voltage feedback input threshold Line regulation IINV Input bias current TJ = 25 C 10.3 V < Vcc < 22 V (2) Vcc = 10.3 V to 22V TBO open, VINV = 0 to 4 V 2.465 2.44 2 -0.2 2.5 2.535 V 2.56 5 -1 mV A
7/39
Electrical characteristics
L6563 - L6563A
Table 5. Electrical characteristics (continued) ( -25C < TJ < +125C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1F between pin VFF and GND; unless otherwise specified)
Symbol Parameter IINV = 1 mA Open loop Test condition Min 9 60 Typ 9.5 80 1 VCOMP = 4V, VINV = 2.4 V VCOMP = 4V, VINV = 2.6 V ISOURCE = 0.5 mA ISINK = 0.5 mA (2) -2 2.5 5.7 2.1 -3.5 4.5 6.2 2.25 6.7 2.4 -5 Max Unit V dB MHz mA mA V V VINVCLAMP Internal clamp level Gv GB ICOMP Voltage gain Gain-bandwidth product Source current Sink current Upper clamp voltage VCOMP Lower clamp voltage
Current sense comparator ICS tLEB td(H-L) VCSclamp Input bias current Leading edge blanking Delay to output Current sense reference clamp Current sense offset Ic latch-off level (L6563 only) VCOMP = Upper clamp, VVFF = VMULT =0.5V VMULT = 0, VVFF = 3V VMULT = 3V, VVFF = 3V
(2)
VCS = 0 100 200 120 1.0 1.08 25
-1 300
A ns ns
1.16
V
Vcsoffset VCSdis
mV 5 1.6 1.7 1.8 V
Output overvoltage IOVP Hys Dynamic OVP triggering current Hysteresis Static OVP threshold Voltage feedforward VVFF V Linear operation range Dropout VMULTpk-VVFF RFF = 47 k to GND 0.5 3 20 V mV
(4) (2)
17
20 15
23
A A
2
2.15
2.3
V
8/39
L6563 - L6563A
Electrical characteristics
Table 5. Electrical characteristics (continued) ( -25C < TJ < +125C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1F between pin VFF and GND; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
Zero current detector VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk Upper clamp voltage Lower clamp voltage Arming voltage (positive-going edge) Triggering voltage (negative-going edge) Input bias current Source current capability Sink current capability IZCD = 2.5 mA IZCD = - 2.5 mA
(4)
5.0 -0.3
5.7 0 1.4 0.7 1 0.3
V V V V A mA mA
(4)
VZCD = 1 to 4.5 V -2.5 2.5
Tracking boost function V ITBO Dropout voltage VVFF - VTBO Linear operation IINV - ITBO current mismatch VTBOclamp Clamp voltage PFC_OK Vthl Vth VEN IPFC_OK Vclamp Latch-off threshold Disable threshold Enable threshold Input bias current Clamp voltage Voltage rising (2) Voltage falling (2) Voltage rising (2) VPFC_OK = 0 to 2.5V IPFC_OK = 1 mA 9 2.4 2.5 0.2 0.26 -0.1 9.5 -1 2.6 V V V A V ITBO = 25 A to 0.25 mA VVFF = 4V (2) ITBO = 0.25 mA 0 -3.5 2.9 3 20 0.25 3.5 3.1 mV mA % V
PWM_LATCH Ileak VH Low level leakage current High level VPWM_LATCH=0 IPWM_LATCH = -0.5 mA 3.7 -1 A V
PWM_STOP Ileak VL Vclamp High level leakage current Low level Clamp voltage VPWM_STOP = 6V IPWM_STOP = 0.5 mA IPFC_OK = 2 mA 9 9.5 1 1 A V V
9/39
Electrical characteristics
L6563 - L6563A
Table 5. Electrical characteristics (continued) ( -25C < TJ < +125C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1F between pin VFF and GND; unless otherwise specified)
Symbol Run function IRUN VDIS VEN Start timer tSTART Gate driver VOHdrop VOLdrop tf tr VOclamp Current fall time Current rise time Output clamp voltage UVLO saturation IGDsource = 5mA; Vcc = 20V Vcc=0 to VccOn, Isink=10mA 10 Dropout voltage IGDsource = 20 mA IGDsource = 200 mA IGDsink = 200 mA 2 2.5 1 30 40 12 2.6 3 2 70 80 15 1.1 V V V ns ns V V Star t timer period 75 150 300 s Input bias current Disable threshold Enable threshold VRUN = 0 to 3 V Voltage falling (2) Voltage rising (2) 0.5 0.56 0.52 0.6 -1 0.54 0.64 A V V Parameter Test condition Min Typ Max Unit
(1), (2) Parameters tracking each other (3) The multiplier output is given by:
V M U L T ( V C O M P 2.5 ) -V C S = K M ----------------------------2-----------------------------VV F F
(4) Parameters guaranteed by design, functionality tested in production.
10/39
L6563 - L6563A
Typical electrical performance
5
Figure 4.
Icc (mA) 10 5 1 0.5 0.1 0.05 0.01 0.005 0 0
Typical electrical performance
Supply current vs supply voltage Figure 5. VCC Zener voltage vs TJ
Vccz (pin 14) (V) 28
27 26 25 24
Co = 1nF f = 70 kHz Tj = 25C
23 22 -50
5
10
15 Vcc(V)
20
25
0
50
Tj (C)
100
150
Figure 6.
Icc
10 5 2 1 0.5 0.2 0.1 0.05
IC consumption vs TJ
Figure 7.
Feedback reference vs TJ
VREF (pin 1) (V) 2.6
Operating Quiescent
(mA)
Vcc = 12 V
2.55
Vcc = 12 V Co = 1 nF f = 70 kHz Disabled or during OVP Latched off
2.5
2.45
Before start-up
0.02 -50 -50
0
50
100
150
2.4 -50
0
50
Tj (C)
100
150
Tj (C)
Figure 8.
Start-up & UVLO vs TJ
Figure 9.
(V)
E/A output clamp levels vs TJ
12.5
VCC-ON (V) 12
VCOMP (pin 2)
7 6
Upper clamp
Vcc = 12 V
11.5
5
11 10.5 10
VCC-OFF 9.5 (V)
4 3 2
Lower clamp
9 -50
0
50
Tj (C)
100
150
1 -50
0
50
Tj (C)
100
150
11/39
Typical electrical performance Figure 10. Static OVP level vs TJ
VCOMP (pin 2) (V)
L6563 - L6563A Figure 11. Vcs clamp vs TJ
VCSx (pin 4) (V) 1.5
Vcc = 12 V VCOMP = Upper clamp
2.5
2.4
Vcc = 12 V
1.4
2.3
1.3
2.2
1.2
2.1
1.1
2 -50
0
50
Tj (C)
100
150
1 -50
0
50
Tj (C)
100
150
Figure 12. Dynamic OVP current vs TJ (normalized value)
IOVP
Figure 13. Current-sense offset vs mains voltage phase angle
VCSoffset (pin 4)
120%
Vcc = 12 V
(mV)
30
Vcc = 12 V Tj = 25
110%
25 20
VMULT = 0 to 3V VFF = 3V
100%
15 10
VMULT = 0 to 0.7V VFF = 0.7V
90%
5
80% -50
0
50
Tj (C)
100
150
0
0
0.628
1.256
1.884
2.512
3.14
()
Figure 14. Delay-to-output vs TJ
tD(H-L) (ns)
Figure 15. Ic latch-off level on current sense vs TJ (L6563 only)
Vpin4 2.0
Vcc = 12 V
300
(V)
Vcc = 12 V
250
1.8
200
1.6
150
1.4
100
1.2
50 -50
0
50
Tj (C)
100
150
1.0 -50
0
50
Tj (C)
100
150
12/39
L6563 - L6563A
Typical electrical performance
Figure 16. Multiplier characteristics @ VFF = 1V Figure 17. ZCD clamp levels vs TJ
VCS (pin 4) VCOMP (pin 2)
VZCD (pin 11) (V)
(V)
1 0.8
4.0
(V)
Vcc = 12 V Tj = 25 C
upper voltage clamp 5.5 5.0 4.5
7 6 5 4 3
Upper clamp
Vcc = 12 V IZCD = 2.5 mA
0.6
3.5
0.4 0.2 0
3.0
2 1 0
Lower clamp
2.6
0
0.2
0.4
0.6
0.8
1
1.2
-1 -50
0
50
Tj (C) Tj
100
150
VMULT (pin 3) (V)
Figure 18. Multiplier characteristics @ VFF = 3V Figure 19. ZCD source capability vs TJ
V CS (pin 4) VCOMP (pin 2)
Vcc = 12 V Tj = 25 C
upper voltage clamp 5.5
I
(V)
0.5 0.4 0.3 0.2
3.5
ZCDsrc
(V)
(mA) 0
Vcc = 12 V VZCD = lower clamp
-2
5.0 4.5 4.0
-4
-6
0.1 0
3.0 2.6
0
0.5
1
1.5
2
2.5
3
3.5
-8 -50
0
50
Tj (C)
100
150
VMULT (pin 3) (V)
Figure 20. Multiplier gain vs TJ
KM
Figure 21. VFF & TBO dropouts vs TJ
(mV) 6
1
Vcc = 12 V VCOMP =4 V VMULT = VFF =1V
Vpin6 - Vpin5
0.8
4
0.6
2
0.4
Vpin5 - Vpin3
Vcc = 12 V Vpin3 = 2.9 V
0
0.2
0 -50
0
50
Tj (C)
100
150
-2 -50
0
50
Tj (C)
100
150
13/39
Typical electrical performance Figure 22. TBO current mismatch vs TJ
100· I(INV)-I(TBO) I(INV)
L6563 - L6563A Figure 23. RUN thresholds vs TJ
Vpin10 (V)
Vcc = 12 V
1.0
Vcc = 12 V
-0.8 -1.0 -1.2 -1.4
ITBO = 250 A
0.8
ON OFF
0.6
-1.6
0.4
-1.8 -2.0
ITBO = 25 A
0.2
-2.2 -2.4 -5 0 0 50
Tj (C)
100
150
0.0 -50
0
50
Tj Tj (C)
100
150
Figure 24. TBO-INV current mismatch vs TBO currents
100· I(INV)-I(TBO) I(INV)
Figure 25. PWM_LATCH high saturation vs TJ
Vpin8 5.3
(V)
-1.6 -1.7 -1.8 -1.9 -2.0 -2.1 -2.2 -2.3 0 100 200 300
I(TBO) I(TBO)
Vcc = 12 V Tj = 25 C
5.2 5.1
Vcc = 12 V
Isource = 50 A
5.0 4.9 4.8 4.7 4.6 4.5 -50 0 50
Tj Tj (C)
Isource = 500 A
400
500
600
100
150
Figure 26. TBO clamp vs TJ
Vpin6 3.5
(V)
Figure 27. PWM_STOP low saturation vs TJ
Vpin9 5.0 0.50
(V)
0.40 4.0
3.25
Vcc = 12 V Isink = 0.5 mA
3.0 0.30
3
2.0 0.20
2.75
Vcc = 12 V Vpin3= 4 V
1.0 0.10 0.0 -50
2.5 -50
0
50
Tj Tj (C)
100
150
0
50
Tj Tj (C)
100
150
14/39
L6563 - L6563A Figure 28. PFC_OK thresholds vs TJ
Vpin7 (V) 3.0 2.0
Latch-off
Vcc = 12 V
Typical electrical performance Figure 29. UVLO saturation vs TJ
Vpin15 (V) 1.1
Vcc = 0 V
1 0.9 0.8 0.7 0.6 0.5 -50
1.0
0.5 0.3 0.2
OFF ON
0.1 -50
0
50
Tj (C) Tj
100
150
0
50
Tj (C) Tj
100
150
Figure 30. Start-up timer vs TJ
Tstart 150 (s)
Vcc = 12 V
Figure 31. Gate-drive output low saturation
Vpin15 (V)
4
Tj = 25 C Vcc = 11 V SINK
140
3
130
2
120 110
1
100 -50
0
50
Tj (C)
100
150
0
0
200
400
600
800
1,000
IGD(mA)
Figure 32. Gate-drive clamp vs TJ
Vpin15clamp (V) 12
Vcc = 20 V
Figure 33. Gate-drive output high saturation
Vpin15 (V)5 -1.
Vcc - 2-2 .0 Vcc --2.5
Tj = 25 C Vcc = 11 V SOURCE
11.5
11
Vcc - 3-3 .0 Vcc --3.5 3.5
10.5
Vcc - 4-4 .0 -4.5
10 -50
0
100
200
300
400
500
600
700
0
50
Tj (C)
100
150
IGD (mA)
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Application information
L6563 - L6563A
6
6.1
Application information
Overvoltage protection
Normally, the voltage control loop keeps the output voltage VO of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. Neglecting the ripple components, under steady state conditions the current through R1 equals that through R2. Considering that the non-inverting input of the error amplifier is internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then: Equation 1
V O 2.5 I R 2 = I R 1 = 2---- = -----------------------.5 R1 R2
If the output voltage experiences an abrupt change Vo the voltage at pin INV is kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant. Then the current through R2 remains equal to 2.5/R2 but that through R1 becomes: Equation 2
V O 2.5 + V O I' R 1 = --------------------------------------R1
The difference current IR1 = I'R1 - I'R1 = VO/R1 will flow through the compensation network and enter the error amplifier (pin COMP). This current is monitored inside the IC and when it reaches about 18 A the output voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 20 A, the OVP is triggered (Dynamic OVP), and the external power transistor is switched off until the current falls approximately below 5 A. However, if the overvoltage persists (e.g. in case the load is completely disconnected), the error amplifier will eventually saturate low hence triggering an internal comparator (Static OVP) that will keep the external power switch turned off until the output voltage comes back close to the regulated value. The output overvoltage that is able to trigger the OVP function is then: Equation 3
VO = R1 · 20 · 10-6
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Application information
An important advantage of this technique is that the overvoltage level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 15%, which means 15% tolerance on the VO. Since it is usually much smaller than Vo, the tolerance on the absolute value will be proportionally reduced. Example: VO = 400V, VO = 40V. Then: R1 = 40V/20A = 2M ; R2 = 2.5·2M·/(400-2.5) = 12.58k. The tolerance on the OVP level due to the L6563/A will be 40·0.15 = 6 V, that is 1.36%. When either OVP is activated the quiescent consumption is reduced to minimize the discharge of the Vcc capacitor. Figure 34. Output voltage setting, OVP and FFP functions: internal block diagram
Vout
R3
{
R3a R1
R3b
{
R1a
0.26V
+ -
FAULT (not latched)
R1b
PFC_OK 7
+ 9.5V -
FAULT (latched) 2.25V
INV
1 9.5V ITBO
2.5V
+ E/A -
Static OVP
+
Dynamic OVP
TBO FUNCTION
20 A 2 COMP
L6563 L6563A
Frequency Compensation
R4
R2
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Application information
L6563 - L6563A
6.2
Feedback Failure Protection (FFP)
The OVP function above described is able to handle "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. It cannot handle the overvoltage generated, for instance, when the upper resistor of the output divider (R1) fails open: the voltage loop can no longer read the information on the output voltage and will force the PFC pre-regulator to work at maximum ON-time, causing the output voltage to rise with no control. A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 34). This divider is selected so that the voltage at the pin reaches 2.5V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected, also including worst-case load/line transients. Example: VO = 400 V, Vox = 475V. Select: R3 = 3M; then: R4 = 3M ·2.5/(475-2.5) = 15.87k. When this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 250 A and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver 3.7V min. with 0.5 mA load, intended for tripping a latched shutdown function of the PWM controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. To restart the system it is necessary to recycle the input power, so that the Vcc voltages of both the L6563/A and the PWM controller go below their respective UVLO thresholds. The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will shut down the IC, reducing its consumption below 1 mA. In this case both PWM_STOP and PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at the pin go above 0.26 V. Note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator.
6.3
Voltage Feedforward
The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage Feedforward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 35).
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Application information
Figure 35. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic
Rectif ied mains current ref erence (V c s x ) E/A output (VC OMP) MULTIPLIER "ideal" diode
2
Vcsx 2
R5
1.5
VCOMP=4V
Actual Ideal
+
1/V
3 MULT R6
1
L6563 L6563A
V FF CFF
9.5V
5
0.5
RFF
0
0
0.5
1
2 VFF=VMULT
3
4
In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF); if it is too large there will be a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-off is required. The device realizes Voltage Feedforward with a technique that makes use of just two external parts and that limits the feedforward time constant trade-off issue to only one direction. A capacitor CFF and a resistor RFF , both connected from the VFF (pin 5) pin to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (pin 3). RFF provides a means to discharge CFF when the line voltage decreases (see Figure 35). In this way, in case of sudden line voltage rise, CFF will be rapidly charged through the low impedance of the internal diode and no appreciable overshoot will be visible at the pre-regulator's output; in case of line voltage drop CFF will be discharged with the time constant RFF·CFF, which can be in the hundred ms to achieve an acceptably low steady-state ripple and have low current distortion; consequently the output voltage can experience a considerable undershoot, like in systems with no feedforward compensation.
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Application information
L6563 - L6563A
The twice-mains-frequency (2·fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: Equation 4
2 VM U L T p k V F F = --------------------------------------1 + 4 fL RF F CF F
where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2·fL component, will be: Equation 5
D 3 % = ------------1--------------------00 2 fL RF F CF F
Figure 36 shows a diagram that helps choose the time constant RFF·CFF based on the amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the pin, the IC will not work properly if the pin is either left floating or connected directly to ground. Figure 36. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current
10
1
f L = 50 Hz
R
F F·
C F F [s]
0 .1
f L= 60 Hz
0 .0 1 0 .1
1
10
D3 %
The dynamics of the voltage feedforward input is limited downwards at 0.5V (see Figure 35), that is the output of the multiplier will not increase any more if the voltage on the VFF pin is below 0.5V. This helps to prevent excessive power flow when the line voltage is lower than the minimum specified value (brownout conditions).
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Application information
6.4
THD optimizer circuit
The L6563/A is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 37 shows the internal block diagram of the THD optimizer circuit. Figure 37. THD optimizer circuit
t 2
t
t
1/V
VFF
COMP
MULTIPLIER MULT
+ +
to PWM comparator
t
OFFSET GENERATOR
t
@ Vac1 @ Vac2 > Vac1
t
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Application information
L6563 - L6563A
Figure 38. THD optimization: standard TM PFC controller (left side) and L6563/A (right side)
Input current
Input current
Rectified mains voltage
Rectified mains voltage
Inpaitncurrent Im u s
MO SFET's drainVdrain voltage
Input current M OS FET's drainVdrain voltage
Imains
Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is modulated by the voltage on the VFF pin (see Section 6.3 on page 18 section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure 38, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness of the optimizer circuit.
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L6563 - L6563A
Application information
6.5
Tracking Boost function
In some applications it may be advantageous to regulate the output voltage of the PFC preregulator so that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators. This is commonly referred to as "tracking boost" or "follower boost" approach. With this IC the function can be realized by connecting a resistor (RT) between the TBO pin and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to V(TBO)/RT, that is internally 1:1 mirrored and sunk from pin INV (pin 1) input of the error amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connected between TBO and GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC preregulator will be forced to get higher. Obviously, the output voltage will move in the opposite direction if the input voltage decreases. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. If this function is not used, leave the pin open: the device will regulate a fixed output voltage. Star ting from the following data:
Vin1 = minimum specified input RMS voltage; Vin2 = maximum specified input RMS voltage; Vo1 = regulated output voltage @ Vin = Vin1; Vo2 = regulated output voltage @ Vin = Vin2; Vox = absolute maximum limit for the regulated output voltage; Vo = OVP threshold,
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Application information
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to set the output voltage at the desired values use the following design procedure: 1. Determine the input RMS voltage Vinclamp that produces Vo = Vox:
Equation 6
V o x V o1 V o x V o2 V i n c l a m p = -------------------------- V i n 2 -------------------------- V i n 1 V o2 V o1 V o2 V o1
and choose a value Vinx such that Vin2 = Vinx < Vinclamp. This will result in a limitation of the output voltage range below Vox (it will equal Vox if one chooses Vinx = Vinclamp) 2. Determine the divider ratio of the MULT pin (pin 3) bias:
Equation 7
3 k = ----------------------2 V i nx
and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than 0.65V. 3. Determine R1, the upper resistor of the output divider:
Equation 8
6 V o R 1 = ---------- 10 20
4.
Calculate the lower resistor R2 of the output divider and the adjustment resistor RT:
Equation 9
V i n2 V i n1 R 2 = 2.5 R 1 -------------------------------------------------------------------------------------------------( V o 1 2.5 ) V i n 2 ( V o 2 2.5 ) V i n 1 RT = V i n2 V i n1 2 k R 1 ----------------------------V o2 V o1
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Application information
5.
Check that the maximum current sourced by the TBO pin (pin 6) does not exceed the maximum specified (0.25mA):
Equation 10
3 3 I T B O m a x = ------ 0.25 10 RT
In the following Mathcad sheet, as an example, the calculation is shown for the circuit illustrated in Figure 40. Figure 41 shows the internal block diagram of the tracking boost function.
Design data
Vin1 := 88V Vin2 := 264V Vox ;= 400V Vo ;= 40V Vo1:= 200V Vo2:= 385V
Step 1
V o x V o1 V o x V o2 V i n c l a m p : = -------------------------- V i n 2 -------------------------- V i n 1 V o2 V o1 V o2 V o1
Vinclamp = 278.27V
choose: Vinx: = 270V
Step 2
3 k : = ----------------------2 V i nx
k = 7.857 x 10-3
Step 3
V o 6 R 1 : = ---------- 10 20
R1 = 2 x 106
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Application information
L6563 - L6563A
Step 4
V i n2 V i n1 R 2 : = 2.5 R 1 -------------------------------------------------------------------------------------------------( V o 1 2.5 ) V i n 2 ( V o 2 2.5 ) V i n 1
R2 = 4.762 x 104
V i n2 V i n1 R T : = k 2 R 1 ----------------------------V o2 V o1
RT = 2.114 x 104
Step 5
3 3 I T B O m a x : = ------ 10 RT
ITBOmax = 0.142 mA
Vo(Vi): =
VM U L T p k k 2 V i V T B O i f ( V M U L T p k < 3 ,V M U L T p k ,3 ) R1 2.5 1 + R--- + V T B O ----------1 RT R 2
Vo(Vin1) = 200V Vo(Vin2) = 385V Vo(VinX) = 391.307V
Figure 39. Output voltage vs. input voltage characteristic with TBO
400 Vin 2 in x V 350
Vo 2
Vo ( Vin ) 300
250
200
100
150
200 Vin
250
300
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Application information
Figure 40. 80W, wide-range-mains PFC pre-regulator with tracking boost function active
D1 STTH1L06 T Supply Voltage 10.3 to 22V R1a 3.3 M R3 68 k R5 62 k C5 1 F R8a 1 M R8b 1 M R10a 3.3 M R10b 3.3 M Vo=200 to 385 V Po=80W
NTC
C6 100 nF MOS STP8NM50
FUSE 4A/250V
+
BRIDGE 4 x 1N4007
C1 0.22 F 400V
R1b 3.3 M -
8 14 3 12
9
11
2
1 13 4
R6 10
Vac (88V to 264V)
L6563
5 10 6 7
C6 56 F 400V
R2 51.1 k
C2 2.2nF
C3 22m F 25V
C4 470 nF
R10 390 k
R4 21 k
C7 10 nF
R7a,b 0.68 1/4 W
R9 47.5 k
R11 34.8 k
Figure 41. Tracking boost and voltage feedforward blocks
Vout IR1 COMP 2 R1 2.5V INV 1 9.5V ITBO IR2 R2 1:1 CURRENT MIRROR 3V
+ + -
Rectified mains current reference
MULTIPLIER E/A
1/V 2 "ideal" diode
R5
3 MULT R6
L6563 L6563A
ITBO
9.5V
6 TBO RT VFF CFF
5
RFF
6.6
Inductor saturation detection (L6563 only)
Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current upslope becomes so large (50-100 times steeper, see Figure 42) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. However, in some applications such as ac-dc adapters, where the PFC pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, so that the output voltage may drop significantly below the rectified peak voltage. As a result, in the
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Application information
L6563 - L6563A
boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. To cope with a saturated inductor, the L6563 is provided with a second comparator on the current sense pin (CS, pin 4) that stops and latches off the IC if the voltage, normally limited within 1.1V, exceeds 1.7V. Also the cascaded DC-DC converter can be stopped via the PWM_LATCH pin that is asserted high. In this way the entire system is stopped and enabled to restart only after recycling the input power, that is when the Vcc voltages of the L6563 and the PWM controller go below their respective UVLO thresholds. System safety will be considerably increased. To better suit the applications where a certain level of saturation of the boost inductor needs to be tolerated, the L6563A does not support this protection function. Figure 42. Effect of boost inductor saturation on the MOSFET current and detection method
6.7
Power management/housekeeping functions
A special feature of this IC is that it facilitates the implementation of the "housekeeping" circuitry needed to coordinate the operation of the PFC stage to that of the cascaded DCDC converter. The functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power down sequencing or failures of either power stage be properly handled. This device provides some pins to do that. As already mentioned, one communication line between the IC and the PWM controller of the cascaded DC-DC converter is the PWM_LATCH pin, which is normally open when the PFC works properly and goes high if it loses control of the output voltage (because of a failure of the control loop) or if the boost inductor saturates, with the aim of latching off the PWM controller of the cascaded DC-DC converter as well (Section 6.2: Feedback Failure Protection (FFP) on page 18 for more details). A second communication line can be established via the disable function included in the PFC_OK pin (Section 6.2 on page 18 for more details ). Typically this line is used to allow the PWM controller of the cascaded DC-DC converter to shut down the L6563/A in case of light load, to minimize the no-load input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits like those shown in Figure 43, where the L6563/A works along with the L5991, PWM controller with standby function, can be used. Needless to say, this operation assumes that the cascaded DC-DC converter stage works as the master and the PFC stage as the slave or, in other words, that the DC-DC stage starts first, it powers both controllers and enables/disables the operation of the PFC stage.
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Application information
Figure 43. Interface circuits that let DC-DC converter's controller IC disable the L6563/A at light load
16 ST-BY 16 ST-BY
L5991/A
4 Vref 27 k BC557 100 k 150 k
L6563
7 PFC_OK
L5991/A
4 Vref 27 k BC557 100 k 150 k 150 k Vcc
L6563
14
BC557
Supply_Bus
100 nF
47 k BC547 BC547
100 nF
100 nF
15 k BC547
150 k
BC557 100 k 10 k Vcc 16 8.2 V 2.2 k 14 PFC_STOP Vcc 14 VREF 8 PFC_OK 7
L6563 L6563A
(RUN) (10)
L6668
L6563 L6563A
L6668
2.2 k
BC547
14 PFC_STOP
14
PFC_STOP
PFC_OK (RUN)
7 (10)
L6599
L6563 L6563A
The third communication line is the PWM_STOP pin (pin 9), which works in conjunction with the RUN pin (pin 10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded DC-DC converter. The pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0.52V on the RUN pin. It is important to point out that this function works correctly in systems where the PFC stage is the master and the cascaded DC-DC converter is the slave or, in other words, where the PFC stage starts first, powers both controllers and enables/disables the operation of the DC-DC stage. This function is quite flexible and can be used in different ways. In systems comprising an auxiliary converter and a main converter (e.g. desktop PC's silver box or hi-end LCD-TV), where the auxiliary converter also powers the controllers of the main converter, the pin RUN can be used to start and stop the main converter. In the simplest case, to enable/disable the PWM controller the PWM_STOP pin can be connected to either the output of the error amplifier (Figure 44 a) or, if the chip is provided with it, to its soft-start pin (Figure 44 b). The use of the soft-start pin allows the designer to delay the start-up of the DC-DC stage with respect to that of the PFC stage, which is often desired. An underlying assumption in order for that to work properly is that the UVLO thresholds of the PWM controller are certainly higher than those of the L6563/A.
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Application information
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Figure 44. Interface circuits that let the L6563/A switch on or off a PWM controller
If this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the DC-DC stage from starting up correctly) or, simply, the PWM controller is devoid of soft start, the arrangement of Figure 45 lets the DC-DC converter start-up when the voltage generated by the PFC stage reaches a preset value. The technique relies on the UVLO thresholds of the PWM controller. Figure 45. Interface circuits for actual power-up sequencing (master PFC)
Another possible use of the RUN and PWM_STOP pins (again, in systems where the PFC stage is the master) is brownout protection, thanks to the hysteresis provided. Brownout protection is basically a not-latched device shutdown function that must be activated when a condition of mains undervoltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shutdown the unit in case of brownout.
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Application information
IC shutdown upon brownout can be easily realized as shown in Figure 46 The scheme on the left is of general use, the one on the right can be used if the bias levels of the multiplier and the RFF·CFF time constant are compatible with the specified brownout level and with the specified holdup time respectively. In Table 6 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Figure 46. Brownout protection (master PFC)
AC mains
L6563 L6563A
5
RUN
10
RUN
10
VFF
L6563 L6563A
RFF
CFF
6.8
Summary of L6563/A idle states
. Table 6. Summary of L6563/A idle states
Condition UVLO Feedback disconnected Saturated Boost Inductor AC Brownout Standby Caused or revealed by Vcc < 8.7 V PFC_OK > 2.5 V Vcs > 1.7 V (L6563 only) RUN < 0.52 V PFC_OK < 0.2 V PWM_LATCH (pin 8) Open Active (high) Active (high) (L6563 only) Open Open PWM_STOP (pin 9) Open Open Open Active (low) Open Typical IC consumption 50 A 180 A 180 A (L6563 only) 1.5 mA 1.5 mA IC behavior Auto-restar t Latched Latched (L6563 only) Auto-restar t Auto-restar t
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Application examples and ideas
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7
Application examples and ideas
Figure 47. Demo board (EVAL6563-80W) 80W, Wide-range, Tracking Boost: Electrical schematic
Daux 1N4007 T R3A R3B D3 1N4148 C6 R2 33 R1 47 k C12 220 nF R18 47 k 8 14 3 C7 4.7 nF 12 C4 100 nF TP2 R20 47 k C2 33 F 25V 6 5 10 9 11 2 1 13 7 4 R15 0 R6 22 C8 1 F
D1 STTH2L06
NTC 2.5
Vo=220 to 390 V Po = 80 W
R9A 1 M R4 39 k R9B 1 M R12A 1 M
120 k 120 k D2 20 V FUSE 4A/250V + P1 1W08G C1 0.47 F 400V R11A 1 M R11B 1 M Vac (88V to 264V) -
15 nF TP1
Q1 STP8NM50
R12A 1 M C5 56 F 400 V
L6563
C9 470 nF R14 22.1 k
C11 4.7 nF
R10 15.8 k
R17 390 k
R7A C10 0.68 1/2 W N.A.
R7B 0.68 1/2 W
R8 37.4 k
R13 10.5 k
Boost inductor spec: E25x13x7 core, 3C85 ferrite or equivalent 1.6 mm gap for 0.43 mH primary inductance Primary: 80 turns 20 x 0.1 mm Secondary: 9 turns 0.1 mm
Figure 48. EVAL6563-80W: PCB and component layout (Top view, real size: 64 x 94 mm)
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Figure 49. EVAL6563-80W: PCB layout, soldering side (Top view)
Table 7. EVAL6563-80W: Evaluation results at full load
Vin (VAC) 90 115 135 180 230 265 Pin (W) 85.3 84.9 83.7 83.5 85.2 85.0 Vo (VDC) 219.4 244.1 263.7 307.6 356.7 390.6 Vo (Vpk-pk) 16.6 15.0 13.9 14.5 13.0 12.1 Po (W) 79.64 80.80 80.16 80.28 81.33 80.85 (%) 93.4 95.2 95.8 96.1 95.5 95.1 PF 0.999 0.998 0.997 0.993 0.984 0.974 THD (%) 3.7 4.3 4.8 6.0 7.7 9.5
Note:
Measurements done with the line filter shown in Figure 51. Table 8. EVAL6563-80W: Evaluation results at half load
Vin (VAC) 90 115 135 180 230 265 Pin (W) 43.4 42.6 43.1 43.8 45.6 46.0 Vo (VDC) 219.9 244.5 264.0 307.7 356.8 390.7 Vo (Vpk-pk) 8.6 7.7 7.3 7.7 6.8 6.7 Po (W) 40.90 40.10 40.39 40.31 41.03 40.63 (%) 94.2 94.1 93.7 92.0 90.0 88.3 PF 0.997 0.994 0.989 0.978 0.951 0.920 THD (%) 4.8 5.7 6.5 8.4 9.6 14.2
Note:
Measurements done with the line filter shown in Figure 51.
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Application examples and ideas Figure 50. EVAL6563-80W: Vout vs. Vin relationship (tracking boost)
L6563 - L6563A
Figure 51. Line filter (not tested for EMI compliance) used for EVAL6563-80W evaluation
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L6563 - L6563A
Application examples and ideas
Figure 52. 250W, wide-range-mains PFC pre-regulator with fixed output voltage
L1 D1 1N5 406 D2 ST T H 5 L 0 6 NTC1 2 .5 Vo u t = 400V Po u t = 250 W
R4 1M Vcc 1 0 .3 to 22 V R3 47 k R5 6 .8 k C4 1 F
R9 A 1M R9 B 1M R1 1 A 1 .8 7 M R11B 1 .8 7 M
R 1A 820 k R 1B 820 k
FUSE 8 A/ 2 5 0 V
B1 K BU 8 M +
C1 1 F 4 00 V
11 C2 1 F 3 14
2
1
7 D3 1N4148 6 C8 1 5 0 F 45 0 V
L6563
13 10 8 9 12 4
R6 33 M1 S T P1 2 N M 5 0 C6 4 7 0 nF 63 0 V
Va c 88 V to 2 64V
5 R7 3 90 k
C7 1 0 nF
R2 10 k
C3 10 nF
C5 4 70 n F
R 8 A, B 0.22 1W
R1 0 1 2 .7 k
R12 20 k
Bo o st Inductor (L1) Spec ET D2 9 x1 6 x1 0 core, 3C85 ferrite or equivalent 1 .5 mm gap for 150 H primary inductance Pr im a ry: 74 turns 20xAWG30 ( 0.3 mm) Se co n d a ry: 8 turns 0.1 mm
Figure 53. 350W, wide-range-mains PFC pre-regulator with fixed output voltage and FOT control
D1 1 N5 4 0 6 D2 ST T H 8 0 6 D T I NT C1 2 .5 Vo u t = 400V Po u t = 350W
L1
R4 1M Vcc 10 .3 to 22 V R5 6 .8 k C5 1 F
R13A 1M R13B 1M R1 5 A 1 .87 M R15B 1 .87 M
R1 A 620 k R1 B 620 k
B1 KBU 8 M + FUSE 8 A/ 2 5 0 V
C1 1 F 4 00 V
14 8 C2 1 F 3 10 5 R3 3 90 k R6 1 .5 k TR1 BC 5 5 7
9
2
1
7 D3 1N4148 6 M 1A ST P 1 2 N M 5 0 C9 4 7 0 nF 63 0 V M1B ST P1 2 NM 5 0 C1 0 1 0 nF R1 1 330 R 1 2 A, B, C 0 .33 1W R14 1 2 .7 k R16 20 k C11 2 2 0 F 4 50 V
L6 563
13 11 R8 1 .5 k C6 330 pF 12 4
R9 6.8 D4 1N4148 D5 1 N4 1 4 8 R10 6.8
Va c 8 8V to 2 64 V
-
R2 10 k
C3 10nF
C4 4 70nF
R7 12 k
C7 5 60 pF
C8 33 0 pF
L1: core E42*21*15, B2 material 1.9 mm air gap on centre leg, main winding inductance 0.55 mH 58 T of 20 x AWG32 ( 0.2 mm)
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Application examples and ideas Figure 54. Demagnetization sensing without auxiliary winding
L6563 - L6563A
RZCD Vinac ZCD 9
CZCD Vout
Rload
L6563 L6563A
Figure 55. Enhanced turn-off for big MOSFET driving
Vcc 14
13
DRIVER
GD Q
BC327
L6563 L6563A
12 GND
Rs
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L6563 - L6563A
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Table 9. SO-14 Mechanical data
Dim. Min A A1 A2 B C
D (1)
mm. Typ Max 1.75 0.30 1.65 0.51 0.25 8.75 4.0 1.27 5.8 0.25 0.40 6.20 0.50 1.27 0.10 0.228 0.01 0.016 Min 0.053 0.004 0.043 0.013 0.007 0.337 0.150
inch Typ Max 0.069 0.012 0.065 0.020 0.01 0.344 0.157 0.050 0.244 0.02 0.050 0.004
1.35 0.10 1.10 0.33 0.19 8.55 3.80
E e H h L k ddd
0 (min.), 8 (max.)
Figure 56. Package dimensions
0016019D
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Revision history
L6563 - L6563A
9
Revision history
Table 10. Revision history
Date 13-Nov-2004 24-Sep-2005 17-Nov-2006 Revision 1 2 3 First issue Changed the maturity from "Preliminary data" to "Datasheet" Added new part number L6563A (Table 2) Updated the Section 4 on page 7 & Section 7 on page 32 the document has been reformatted Replaced block diagram, added Figure 37 on page 21 and minor editor changes. Changes
12-Mar-2007
4
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L6563 - L6563A
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