TS4975
Stereo Headphone Drive Amplifier with Digital Volume Control via I2C Bus
Operating from VCC = 2.5V to 5.5V I²C bus control interface 40mW output power @ VCC = 3.3V, THD = 1%, F = 1kHz, with 16 load Ultra-low consumption in stdby mode: 0.6A Digital volume control range from 18dB to - 3 4 dB 14-step digital volume control 9 different output mode selections Pop & click noise reduction circuitry Flip-chip package, 12 x 300m bumps (leadf r ee) Pin out (top view) TS4975EIJT - Flip Chip
Description
The TS4975 is a stereo audio headphone driver capable of delivering up to 102mW per channel of continuous average power into a 16 singleended load with 1% THD+N from a 5V power supply. The overall gain of these headphone dr ivers is controlled digitally by volume control registers programmed via the I2C interface, minimizing the number of external components needed. This device can also easily be driven by an MCU to select the output modes, through the I2C bus interface. A phantom ground configuration allows one to avoid using bulky capacitors on the outputs of the headphone amplifiers. The TS4975 is packaged in a 1.8mm X 2.3mm Flip Chip package, ideally suited for spaceconscious portable applications. It has also an internal protection mechanism. thermal shutdown
OUT1
PHG 1
PHG2
O UT2
IN1
VCC
GND
IN2
BYP ASS
SCL
SDA
ADD
Applications
Mobile phones (cellular / cordless) PDAs Laptop/notebook computers Portable audio devices
Order Codes
Par t Number TS4975EIJT Temperature Range -40, +85C Package Flip-chip Packing Tape & Reel Marking A75 Rev 3 1/36
ww w.st .com
36
November 2005
Absolute Maximum Ratings
TS4975
1
Absolute Maximum Ratings
Table 1.
S y mb o l VCC Vi Toper Tstg Tj R thja P d i ss ESD ESD Latch-up
Key parameters and their absolute maximum ratings
Parameter Supply voltage (1) Input Voltage (2) Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient (3) Power Dissipation Susceptibility - Human Body Model(5) Susceptibility - Machine Model (min. Value) Latch-up Immunity Lead Temperature (soldering, 10sec) Value 6 GND to VCC -40 to + 85 -65 to +150 150 200 Internally Limited(4) 2 200 200 260 kV V mA C Unit V V C C C C/W
1. All voltages values are measured with respect to the ground pin. 2. The magnitude of input signal must never exceed VCC + 0.3V / GN D - 0.3V 3. Device is protected in case of over temperature by a thermal shutdown active @ 150C. 4. Exceeding the power derating curves during a long period, may involve abnormal operating condition. 5. Human body model, 100pF discharged through a 1.5kOhm resistor, into pin to VCC device.
Table 2.
S y mb o l VCC RL CL Toper R thja
Operating conditions
Parameter Supply Voltage Load Resistor Load Capacitor RL = 16 to 100, RL > 100, Operating Free Air Temperature Range Flip Chip Thermal Resistance Junction to Ambient Value 2.5 to 5.5v >16 Unit V
400 100 -40 to +85 90
pF
C C/W
2/36
TS4975
Typical Application Schematics
2
Typical Application Schematics
Typical application schematics for the TS4975 are show in Figure 1, for a single-ended output configuration and in Figure 2, for a phantom ground output configuration. Figure 1. Single-ended configuration
V cc
+
Cb 1 F
+
Cs 1 F
A1
Bias
I N1 P re-A mp lif ier OUT 1 Amplifier
V cc
Bypa ss
B2
I N1
Cin 1
A2
Cou t1
RL = 16/32 Ohms
IN1
OUT 1
A3
+
+
1k
33 0n F
P HG1 Amplifier
22 0 F
PHG1 M ode S elect
P HG2 Amplifier
B3
PHG2
C3
I N2 P re-A mp lif ier
OUT 2 Amplifier
I N2
Cin 2
D2
Cou t2
RL = 16/32 Ohms
IN2
OUT 2
D3
+
+
1k
33 0n F
22 0 F
Volume control
GND ADD
I2C
S CL S DA
TS4975
D1
B1
C2
ADD SCL SDA
C1
3/36
Typical Application Schematics
Figure 2. Phantom ground output configuration
V cc
TS4975
+
Cb 1F
+
Cs 1F
A1
B ypa ss
B ias
IN 1 P re-Amplifier OUT1 Amplifier
V cc
B2
RL = 16/32 Ohms
A3
I N1
Cin1
A2
IN1
OUT1
+
330 nF
P HG 1 Amplifier
PH G1 M ode Select
P HG 2 Amplifier
B3
PH G2
C3
IN 2 P re-Amplifier
OUT2 Amplifier
RL = 16/32 Ohms
D3
I N2
Cin2
D2
IN2
OUT2
330 nF
+
Volum e control
G ND A DD
I2 C
S CL SDA
TS4975
D1
B1
C2
A DD S CL S DA
4/36
C1
TS4975
Electrical Characteristics
3
Electrical Characteristics
Table 3.
S y mb o l VIL VIH FSCL Vol Ii
Electrical characteristics for the I²C interface
Parameter Maximum Low level Input Voltage on pins SDA, SCL, VADD Minimum High Level Input Voltage on pins SDA, SCL, VADD SCL Maximum clock Frequency Max Low Level Output Voltage, SDA pin, Isink = 3mA Max Input current on SDA, SCL(1) from 0.1 VCC to 0.9 VCC Value 0.3 VCC 0.7 VCC 400 0.4 10 Unit V V kHz V A
1. SCL and SDA are CMOS inputs. The nominal input current is about few pA and not 10uA. 10A refer to the I2C bus specification.
Table 4.
Output noise (all inputs grounded)
Unweighted Filter from VCC = 2.5V to 5V Weighted Filter (A) from VCC = 2.5V to 5V 23Vr ms 45Vr ms 23Vr ms 45Vr ms
SE, G = +2dB SE, G = +18dB PHG, G = +2dB PHG, G = +18dB
3 4 V r ms 67Vrms 34Vrms 6 7 V r ms
5/36
Electrical Characteristics
Table 5.
Symbol
TS4975
VCC = +2.5 V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Conditions N o input signal, no load, Single-ended, Mode 1-4 N o input signal, no load, Single-ended, Mode 5-8 N o input signal, no load, Phantom Ground, Mode 1-4 N o input signal, no load, Phantom Ground, Mode 5-8 Min. Typ. 3 2 4. 6 3. 6 0. 6 5 15 11 15 11 21 13 mW 21 13 0.3 0. 3 % 0. 3 0. 3 Ma x . 4.2 2.8 mA 6.5 5.3 2 50 A mV Uni t
ICC
Supply Current
ISTBY Voo
Standby Current Output Offset Voltage
SCL and SDA at VCC level, N o input signal N o input signal, RL = 32, Phantom Ground Single-ended, THD+N = 1% Max, F = 1kHz, RL = 16 Single-ended, THD+N = 1% Max,F = 1kHz, RL = 3 2 Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 16 Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 32 Single-ended, AV = 2dB, RL = 32, Pout = 10 mW, 20Hz < F < 20kHz, Single-ended, AV = 2dB, RL = 16, Pout = 15 mW, 20Hz < F < 20kHz Phantom Ground, AV = 2dB, RL = 32, Pout = 10 mW, 20Hz < F < 20kHz Phantom GroundAV = 2dB, RL = 16, Pout = 15 mW, 20Hz < F < 20kHz Single-ended Output referenced to Phantom Ground F = 217Hz, RL = 16, AV = 2dB Vripple = 200mV pp, Input Grounded, Cb = 1 F Single-ended Output referenced to Ground, F = 217Hz, RL = 16, AV = 2dB Vripple = 200mV pp, Input Grounded, Cb = 1 F
Pout
Output Power (per channel)
THD + N
Total Harmonic Distortion + Noise
60
PSRR
Power Supply Rejection Ratio(1)
60
dB
6/36
TS4975
Table 5.
Symbol
Electrical Characteristics
VCC = +2.5 V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Conditions RL = 32, AV = 2dB with Single-ended F = 1kHZ, Pout = 10mW RL = 32, AV = 2dB with Single-ended F = 20Hz to 20kHz, Pout = 10mW RL = 32, AV = 2dB with Phantom Ground, F = 1kHZ, Pout = 10mW RL = 32, AV = 2dB with Phantom Ground, F = 20Hz to 20kHz, Pout = 10mW AV = 2dB, RL = 32, Pout = 12m W Single-Ended AV = 2dB, RL = 32, Pout = 12m W Phantom Ground Min. Typ. 103 Ma x . Uni t
75 dB 69 69 88 dB 88 23 Vr m s 23 - 34 4 -1 +1 30 110 1 34.5 180 +18 dB dB dB k ms s
Crosstalk
Channel Separation
SNR
Signal to Noise Ratio A-Weighted
ONoise G
Output Noise Voltage, AV = 2dB, Single-ended A-Weighted AV = 2dB, Phantom Ground Digital Gain Range Digital Gain Stepsize Gain Error Tolerance In1 & In2 to Out1 & Out2
Zin twu t ws
In1 & In2 Input Impedance Wake up time Standby time
All gain settings Cb = 1 F
25.5
1. Dynamic measurements - 20*log(rms(Vout) /rms(Vripple)). Vripple is an added sinus signal to
VCC @ F = 217Hz
7/36
Electrical Characteristics
Table 6.
S y mb o l
TS4975
VCC = +3.3V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Conditions No input signal, no load, Single-ended, Mode 1-4 No input signal, no load, Single-ended, Mode 5-8 No input signal, no load, Phantom Ground, Mode 1-4 No input signal, no load, Phantom Ground, Mode 5-8 M in. Typ. 3 2 4.6 3.6 0.6 5 34 24 34 24 40 26 mW 40 26 0.3 0.3 % 0.3 0.3 M ax. 4.2 2.8 mA 6.5 5.3 2 50 A mV Uni t
I CC
Supply Current
ISTBY Voo
Standby Current Output Offset Voltage
SCL and SDA at VCC level, No input signal No input signal, RL = 32, Phantom Ground Single-ended, THD+N = 1% Max, F = 1kHz, RL = 16
Pout
Output Power (per channel)
Single-ended, THD+N = 1% Max,F = 1kHz, RL = 32 Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 16 Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 32 Single-ended, AV = 2dB, RL = 32, Pout = 20 mW, 20Hz < F < 20kHz, Single-ended, AV = 2dB, RL = 16, Pout = 30 mW, 20Hz < F < 20kHz Phantom Ground, AV = 2dB, RL = 32, Pout = 20 mW, 20Hz < F < 20kHz Phantom GroundAV = 2dB, R L = 16, Pout = 30 mW, 20Hz < F < 20kHz Single-ended Output referenced to Phantom Ground F = 217Hz, RL = 16, AV = 2dB Vripple = 200mVpp, Input Grounded, Cb = 1 F Single-ended Output referenced to Ground, F = 217Hz, RL = 16, AV = 2dB Vripple = 200mVpp, Input Grounded, Cb = 1 F
THD + N
Total Harmonic Distortion + Noise
61
PSRR
Power Supply Rejection Ratio(1)
dB
61
8/36
TS4975
Table 6.
S y mb o l
Electrical Characteristics
VCC = +3.3V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Conditions RL = 32, AV = 2dB with Single-ended F = 1kHZ, Pout = 20mW RL = 32, AV = 2dB with Single-ended F = 20Hz to 20kHz, Pout = 20m W RL = 32, AV = 2dB with Phantom Ground, F = 1kHZ, Pout = 20mW RL = 32, AV = 2dB with Phantom Ground, F = 20Hz to 20kHz, Pout = 20m W AV = 2dB, RL = 32, Pout = 25mW Single-Ended AV = 2dB, RL = 32, Pout = 25mW Phantom Ground M in. Typ. 103 75 dB 69 69 90 dB 90 23 23 -34 4 -1 All gain settings Cb=1F 25.5 30 90 1 +1 34.5 156 +18 dB dB dB k ms s M ax. Uni t
Crosstalk Channel Separation
SNR
Signal To Noise Ratio
ONoise G
Output Noise Voltage, AV = 2dB, Single-ended A-Weighted AV = 2dB, Phantom Ground Digital Gain Range Digital Gain Step size Gain Error Tolerance In1 & In2 Input Impedance Wake up time Standby time In1 & In2 to Out1 & Out2
Vr m s
Zin twu t ws
1. Dynamic measurements - 20*log(rms(Vout) /rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217Hz
9/36
Electrical Characteristics
Table 7.
S y mb o l
TS4975
VCC = +5V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Conditions No input signal, no load, Single-ended, Mode 1-4 No input signal, no load, Single-ended, Mode 5-8 No input signal, no load, Phantom Ground, Mode 1-4 No input signal, no load, Phantom Ground, Mode 5-8 Min. Typ. 3 2 4.6 3.6 0.6 5 92 59 92 59 102 64 mW 98 63 0.3 0.3 % 0.3 Max. 4.2 2.8 mA 6.5 5.3 2 50 A mV Uni t
I CC
Supply Current
ISTBY Voo
Standby Current Output Offset Voltage
SCL and SDA at VCC level, No input signal No input signal, RL = 32, Phantom Ground Single-ended, THD+N = 1% Max, F = 1kHz, RL = 16 Single-ended, THD+N = 1% Max,F = 1kHz, RL = 32 Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 16 Phantom Ground, THD+N = 1% Max, F = 1kHz, RL = 32 Single-ended, AV = 2dB, RL = 32, Pout = 50 mW, 20Hz < F < 20kHz, Single-ended, AV = 2dB, RL = 16, Pout = 80 mW, 20Hz < F < 20kHz Phantom Ground, AV = 2dB, RL = 32, Pout = 50 mW, 20Hz < F < 20kHz Phantom GroundAV = 2dB, RL = 16, Pout = 80 mW, 20Hz < F < 20kHz Single-ended Output referenced to Phantom Ground F = 217Hz, RL = 16, AV = 2dB Vripple = 200mVpp, Input Grounded, Cb = 1F Single-ended Output referenced to Ground F = 217Hz, RL = 16, AV = 2dB Vripple = 200mVpp, Input Grounded, Cb = 1F
Pout
Output Power (per channel)
Total Harmonic THD + N Distortion + Noise
0.3
63
PSRR
Power Supply Rejection Ratio(1)
dB
63
10/36
TS4975
Table 7.
S y mb o l
Electrical Characteristics
VCC = +5V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Conditions RL = 32, AV = 2dB with Single-ended F = 1kHZ, Pout = 50m W RL = 32, AV = 2dB with Single-ended F = 20Hz to 20kHz, Pout = 50m W RL = 32, AV = 2dB with Phantom Ground, F = 1kHZ, Pout = 50m W RL = 32, AV = 2dB with Phantom Ground, F = 20Hz to 20kHz, Pout = 50m W AV = 2dB, RL = 32, Pout = 62mW Single-Ended AV = 2dB, RL = 32, Pout = 62mW Phantom Ground AV = 2dB, Single-ended AV = 2dB, Phantom Ground In1 & In2 to Out1 & Out2 -34 4 -1 All gain settings Cb=1F 25.5 30 80 1 +1 34.5 144 Min. Typ. 103 Max. Uni t
75 dB 69
Crosstalk Channel Separation
69 95 dB 95 23 V r ms 23 +18 dB dB dB k ms s
SNR
Signal To Noise Ratio, A-Weighted
ONoise G
Output Noise Voltage, A-Weighted Digital Gain Range Digital Gain Step size Gain Error Tolerance
Zin twu t ws
In1 & In2 Input Impedance Wake up time Standby time
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple )). Vripple is an added sinus signal to VCC @ F = 217Hz
11/36
Electrical Characteristics
Figure 3. TH D+N vs. output power Figure 4. THD+N vs. output power
TS4975
10 R L = 8 O ut . mode 1 - 8 S E, G = +2dB B W < 125kHz T a m b = 25C V c c = 2 .5 V F = 2 0k H z
10 R L = 8 O ut . mode 1 - 8 S E, G = +18dB B W < 125kHz T a m b = 25C
V c c = 3 .3 V F = 2 0 k Hz V c c = 2 . 5V F =2 0 kH z
1
THD + N (%)
1
THD + N (%)
V c c = 2 . 5V F =1 kH z
0 .1
0 .1 V c c = 3 .3 V F =1 kH z V c c = 2 .5 V F =1 kH z Vcc =5 V F =2 0 kH z 0. 01
O u tp u t power (W)
0 . 01
V c c = 3 .3 V F =1 kH z
V c c = 3. 3 V F = 20 k H z
V c c = 5V F = 20 k H z
Vcc =5 V F =1 kH z
0 . 01
Vcc =5 V F =1 kH z
1 E- 3 1 E- 3
0. 01
O u tp u t power (W)
0. 1
1 E- 3 1 E- 3
0. 1
Figure 5.
TH D+N vs. output power
Figure 6.
THD+N vs. output power
10 R L = 16 O ut . mode 1 - 8 S E, G = +2dB B W < 125kHz T a m b = 25C V c c = 2 .5 V F = 2 0k H z
10 R L = 16 O ut . mode 1 - 8 S E, G = +18dB B W < 125kHz T a m b = 25C V c c = 3. 3 V F = 20 k H z V c c = 2 .5 V F =1 kH z
1
THD + N (%)
1
THD + N (%)
V c c = 2 .5 V F =1 kH z
0 .1
0 .1
0 . 01
V c c = 3 . 3V F =1 kH z
V c c = 3 .3 V F = 2 0k H z
V cc=5 V F =2 0 kH z
Vc c=5 V F =1 kH z
0 . 01
V c c = 2 .5 V F =2 0 kH z
V c c = 3 . 3V F =1 kH z
V cc=5 V F =2 0 kH z
Vc c=5 V F =1 kH z
1 E- 3 1 E- 3
0. 01
O u tp u t power (W)
0. 1
1 E- 3 1 E- 3
0. 01
O u tp u t power (W)
0. 1
Figure 7.
TH D+N vs. output power
Figure 8.
THD+N vs. output power
10 R L = 32 O ut . mode 1 - 8 S E, G = +2dB B W < 125kHz T a m b = 25C V c c = 2 .5 V F =2 0 kH z
10 R L = 32 O ut . mode 1 - 8 S E, G = +18dB B W < 125kHz T a m b = 25C V c c = 2 .5 V F = 2 0k H z
1
THD + N (%)
1
THD + N (%)
0 .1 V c c = 5V F = 20 k H z V c c = 3 .3 V F =2 0 kH z V c c = 3. 3V F = 1 k Hz 0. 01
O u tp u t power (W)
0 .1 V c c = 5V F = 20 k H z V c c = 2 .5 V F =1 kH z V c c = 3 .3 V F =2 0 kH z 0. 01
O u tp u t power (W)
0 . 01
V c c = 2 .5 V F =1 kH z
0 . 01
Vc c=5 V F =1 kH z 0. 1 1 E- 3 1 E- 3
V c c = 3 .3 V F= 1 kH z
Vc c=5 V F =1 kH z 0. 1
1 E- 3 1 E- 3
12/36
TS4975
Figure 9. TH D+N vs. output power
Electrical Characteristics
Figure 10. THD+N vs. output power
10 R L = 8 O ut . mode 1 - 8 P H G , G = +2dB B W < 125kHz T a m b = 25C V c c = 2 .5 V F = 2 0k H z V c c = 2 .5 V F =1 kH z
THD + N (%)
10 V c c = 2 .5 V F = 1 kH z 1 V c c = 2. 5V F = 20 k H z V c c = 3. 3 V F = 20 k H z
1
THD + N (%)
0 .1
0 .1 V c c = 3 .3 V F =1 kH z Vcc =5 V F =2 0 kH z 0. 01
O u tp u t power (W)
0 . 01
V c c = 3. 3V F = 1 k Hz
V c c = 3 .3 V F = 2 0k H z
V cc=5 V F =2 0 kH z
Vc c=5 V F =1 kH z
0 . 01
R L = 8 O ut . mode 1 - 8 S E, G = +18dB B W < 125kHz T a m b = 25C
Vcc =5 V F =1 kH z
1 E- 3 1 E- 3
0. 01
O u tp u t power (W)
0. 1
1 E- 3 1 E- 3
0. 1
Figure 11. TH D+N vs. output power
Figure 12. THD+N vs. output power
10 R L = 16 O ut . mode 1 - 8 P H G , G = +2dB 1 B W < 125kHz T a m b = 25C
THD + N (%)
10 V c c = 2 .5 V F = 2 0k H z 1
THD + N (%)
V c c = 3 .3 V F = 2 0k H z V c c = 2 .5 V F =1 kH z V c c = 2 .5 V F =2 0 kH z
V c c = 2 .5 V F =1 kH z
0 .1
0 .1 V c c = 3 .3 V F= 1 kH z Vcc =5 V F= 2 0k Hz 0. 01
O u tp u t power (W)
0 . 01
V c c = 3 . 3V F =1 kH z
V c c = 3 .3 V F = 2 0k H z
V cc=5 V F =2 0 kH z
Vc c=5 V F =1 kH z
0 . 01
R L = 16 O u t. mode 1 - 8 P H G , G = +18dB B W < 125kHz T a m b = 25C
Vc c=5 V F =1 kH z
1 E- 3 1 E- 3
0. 01
O u tp u t power (W)
0. 1
1 E- 3 1 E- 3
0. 1
Figure 13. TH D+N vs. output power
Figure 14. THD+N vs. output power
10 R L = 32 O ut . mode 1 - 8 P H G , G = +2dB B W < 125kHz T a m b = 25C V c c = 2 .5 V F = 2 0 k Hz
10 R L = 32 O u t. mode 1 - 8 PH G , G = +18dB BW < 125kHz T am b = 25C V c c = 2 .5 V F = 2 0k H z
1
THD + N (%)
1
THD + N (%)
0 .1 V c c = 5V F = 20 k H z 0 . 01 V c c = 2. 5V F = 1 k Hz V c c = 3 .3 V F =2 0 kH z 0. 01
O u tp u t power (W)
0 .1 V c c = 5V F = 20 k H z V c c = 3. 3V F = 20 k H z V c c = 3 .3 V F= 1 kH z 0. 01
O u tp u t power (W)
0 . 01 V c c = 3. 3V F = 1 k Hz Vc c=5 V F =1 kH z 0. 1
V c c = 2. 5V F = 1 k Hz
Vcc =5 V F =1 kH z 0. 1
1 E- 3 1 E- 3
1 E- 3 1 E- 3
13/36
Electrical Characteristics
Figure 15. TH D+N vs. frequency Figure 16. THD+N vs. frequency
TS4975
10 R L = 8 O u tp u t mode 1 - 8 Sin g le Ended G = +2dB 1 BW < 125kHz T am b = 25C V c c = 2 .5 V P=2 0 m W 0. 1 V c c = 3 .3 V P=4 0 m W V c c = 5V P = 1 10 m W
10 R L = 8 O u tp u t mode 1 - 8 Sin g le Ended G = +18dB BW < 125kHz T a mb = 25C V c c = 2 .5 V P=2 0 m W 0. 1 V c c = 3 .3 V P=4 0 m W V c c = 5V P = 1 10 m W
THD + N (%)
0 .0 1
THD + N (%)
1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
0 .0 1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
Figure 17. TH D+N vs. frequency
Figure 18. THD+N vs. frequency
10 R L = 16 O u tp ut mode 1 - 8 S in gle Ended G = +2dB B W < 125kHz T a m b = 25C V c c = 2 .5 V P = 15 m W 0. 1 V c c = 3 .3 V P=3 0 m W Vcc =5 V P=8 0 m W
10 R L = 16 O u tp u t mode 1 - 8 Sin g le Ended G = +18dB BW < 125kHz T am b = 25C V c c = 2 .5 V P = 15 m W 0. 1 V c c = 3 .3 V P=3 0 m W Vcc =5 V P=8 0 m W
THD + N (%)
0 .0 1
THD + N (%)
1
1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
0 .0 1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
Figure 19. TH D+N vs. frequency
Figure 20. THD+N vs. frequency
10 R L = 32 O u tp u t mode 1 - 8 Sin g le Ended G = +2dB BW < 125kHz T am b = 25C V c c = 2. 5V P =1 0 mW 0. 1 V c c = 3. 3V P =2 0 mW Vcc =5 V P=5 0 m W
10 R L = 32 O u tp u t mode 1 - 8 Sin gle Ended G = +18dB BW < 125kHz T am b = 25C V c c = 2. 5 V P =1 0 m W 0. 1 V c c = 3 .3 V P=2 0 m W Vcc =5 V P=5 0 m W
THD + N (%)
0 .0 1
THD + N (%)
1
1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
0 .0 1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
14/36
TS4975
Figure 21. TH D+N vs. frequency
Electrical Characteristics
Figure 22. THD+N vs. frequency
10 RL = 8 O u tp u t mode 1 - 8 Ph an t om Ground G = +2dB BW < 125kHz Ta m b = 25C V c c = 2 .5 V P=2 0 m W 0. 1 V c c = 3. 3 V P =4 0 m W V c c = 5V P = 1 1 0m W
10 RL = 8 O u tp u t mode 1 - 8 Ph an t om Ground G = +18dB BW < 125kHz Ta m b = 25C V c c = 2 .5 V P = 20 m W 0. 1 V c c = 3 .3 V P = 40 m W
THD + N (%)
THD + N (%)
1
1
V cc=5 V P = 1 10 m W 0 .0 1 1 00 1 0 00
F requ en cy (Hz)
1 0 0 00
0 .0 1
1 00
1 0 00
Fr equ en cy (Hz)
1 0 0 00
Figure 23. TH D+N vs. frequency
Figure 24. THD+N vs. frequency
10 R L = 16 O u tp u t mode 1 - 8 Ph a nt o m Ground G = +2dB BW < 125kHz T am b = 25C V c c = 2. 5V P =1 5 mW 0. 1 V c c = 3. 3V P =3 0 mW Vcc =5 V P=8 0 m W
10 R L = 16 O u tp u t mode 1 - 8 Ph a nt om Ground G = +18dB BW < 125kHz T am b = 25C V c c = 2. 5V P = 1 5m W 0. 1 V c c = 3 .3 V P = 3 0m W
THD + N (%)
THD + N (%)
1
1
Vcc= 5 V P=8 0 m W
0 .0 1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
0 .0 1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
Figure 25. TH D+N vs. frequency
Figure 26. THD+N vs. frequency
10 RL = 32 O u tp u t mode 1 - 8 Ph an t om Ground G = +2dB BW < 125kHz Ta m b = 25C V c c = 2 . 5V P = 1 0m W 0. 1 V c c = 3 .3 V P = 20 m W Vcc =5 V P=5 0 m W
10 R L = 32 O u tp u t mode 1 - 8 Ph a n to m Ground G = +18dB BW < 125kHz T a mb = 25C V c c = 2. 5 V P =1 0 mW V c c = 3 .3 V P=2 0 m W Vcc =5 V P=5 0 m W
THD + N (%)
THD + N (%)
1
1
0. 1
0 .0 1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
0 .0 1
1 00
1 0 00
F requ en cy (Hz)
1 0 0 00
15/36
Electrical Characteristics
Figure 27. Output power vs. power supply voltage (each channel)
TS4975
Figure 28. Output power vs. power supply voltage (each channel)
1 80
Output power at 10% THD + N (mW) Output power at 1% THD + N (mW)
2 20 F = 1kHz O u tp u t mode 1 - 8 Sin g le Ended BW < 125 kHz T am b = 25C 32 2 00 1 80 1 60 1 40 1 20 1 00 80 60 40 20 0 2. 5 3 .0 3 .5 4 .0
Vcc (V)
1 60 1 40 1 20 1 00 80 60 40 20
8 16
F = 1kHz O u tp u t mode 1 - 8 Sin g le Ended BW < 125 kHz T am b = 25C 32
8
16
64 3 .0 3 .5 4 .0
Vcc (V)
64 4 .5 5 .0 5. 5
0 2. 5
4 .5
5 .0
5. 5
Figure 29. Output power vs. power supply voltage (each channel)
Figure 30. Output power vs. power supply voltage (each channel)
1 80
Output power at 1% THD + N (mW)
Output power at 10% THD + N (mW)
1 60 1 40 1 20 1 00 80 60 40 20
F = 1kHz O u tp u t mode 1 - 8 Ph a n to m Ground BW < 125 kHz T a mb = 25C 3 2
2 20
8 16
2 00 1 80 1 60 1 40 1 20 1 00 80 60 40 20
F = 1kHz O u tp u t mode 1 - 8 Ph a nt o m Ground BW < 125 kHz T am b = 25C 32
8 16
64 3 .0 3 .5 4 .0
Vcc (V)
64 3 .0 3 .5 4 .0
Vcc (V)
0 2. 5
4 .5
5 .0
5. 5
0 2. 5
4 .5
5 .0
5. 5
16/36
TS4975
Figure 31. PSSR vs. frequency
Electrical Characteristics
Figure 32. PSSR vs. frequency
0 - 10 - 20 - 30
PSRR (dB)
0 Vcc = 2.5V RL 16 O u tp u t mode 1 - 8 SE, Inp. grounded Vr ipp le = 200mVpp G = + 1 0 dB - 10 - 20 G = + 1 8 dB
PSRR (dB)
- 30 - 40 - 50 - 60 - 70
Vc c = 2.5V R L 16 O u t pu t mode 1 - 8 PH G , Inp. grounded Vr ip p le = 200mVpp G = + 1 0d B
G = + 1 8d B G = + 2 dB
- 40 - 50 - 60 - 70 - 80 - 90 G =- 2 d B - 1 00 20 100 1000
F req uen cy (Hz)
G =+2 d B
G =- 1 0 d B
G =- 3 4 d B
- 80 - 90 G =- 2 d B 100 G = - 1 0d B 1000
F req uen cy (Hz)
G = - 34 d B 1 0 0 00
1 0 0 00
- 1 00 20
Figure 33. PSSR vs. frequency
Figure 34. PSSR vs. frequency
0 - 10 - 20 - 30
PSRR (dB)
0 Vcc = 3.3V R L 16 O u tp u t mode 1 - 8 SE, Inp. grounded Vr ip ple = 200mVpp G = + 1 0d B - 10 - 20 G = + 1 8d B
PSRR (dB)
- 30 - 40 - 50 - 60 - 70 - 80
Vc c = 3.3V R L 16 O u tp u t mode 1 - 8 PH G , Inp. grounded Vr ip p le = 200mVpp G = + 1 0d B
G = + 1 8d B G =+2 d B
- 40 - 50 - 60 - 70 - 80 G = - 1 0 dB - 90 G =- 2 d B - 1 00 20 100 1000
F req uen cy (Hz)
G = + 2d B
G =- 3 4 d B 1 0 0 00
- 90 - 1 00 20 100
G =- 2 d B
G = - 1 0d B 1000
G = - 34 d B 1 0 0 00
F req uen cy (Hz)
Figure 35. PSSR vs. frequency
Figure 36. PSSR vs. frequency
0 - 10 - 20 - 30
PSRR (dB)
0 V cc = 5V R L 16 O u tp ut mode 1 - 8 S E, Inp. grounded V r ipp le = 200mVpp G = + 1 0d B - 10 - 20 G = + 1 8d B
PSRR (dB)
- 30 - 40 - 50 - 60 - 70
Vcc = 5V R L 16 O u tp u t mode 1 - 8 PH G , Inp. grounded Vr ip ple = 200mVpp G = + 1 0d B
G = + 1 8d B G =+2 d B
- 40 - 50 - 60 - 70 - 80 - 90 G = -2 d B - 1 00 20 100 1000
F req uen cy (Hz)
G =+2 d B
G =- 1 0 d B G = -3 4 d B 1 0 0 00
- 80 - 90 - 1 00 20 100 G = - 2 dB G = - 1 0d B 1000
F req uen cy (Hz)
G =- 3 4 d B 1 0 0 00
17/36
Electrical Characteristics
Figure 37. Crosstalk vs. frequency Figure 38. Crosstalk vs. frequency
TS4975
0 V cc = 2.5V O ut pu t mode 1 - 2 0 S ing le Ended G = +2dB - 4 0 T a m b = 25C -6 0 -8 0 -1 0 0 -1 2 0 R L = 3 2 Po =1 0 m W RL = 1 6 Po =1 5 mW
0 - 10
Crosstalk Level (dB)
Crosstalk Level (dB)
- 20 - 30 - 40 - 50 - 60 - 70
Vcc = 2.5V O u tp u t mode 1 Ph a nt o m Ground G = +2dB T am b = 25C
R L =3 2 P o= 1 0m W
R L= 16 Po =1 5 m W
100
1 0 00
F requ en cy (Hz)
1 0 0 00
- 80
10 0
1 00 0
Freq u en cy (Hz)
1 0 0 00
Figure 39. Crosstalk vs. frequency
Figure 40. Crosstalk vs. frequency
0 -2 0
Crosstalk Level (dB)
0 Vc c = 3.3V O u t pu t mode 1 Sin g le Ended G = +2dB T a m b = 25C RL = 1 6 Po = 3 0 mW R L = 3 2 Po =2 0 m W - 10
Crosstalk Level (dB)
- 20 - 30 - 40 - 50 - 60 - 70
-4 0 -6 0 -8 0 -1 0 0 -1 2 0
Vcc = 3.3V O u tp u t mode 1 Ph a nt o m Ground G = +2dB T am b = 25C
R L =3 2 P o= 2 0m W
R L= 16 Po =3 0 m W
100
1 0 00
F requ en cy (Hz)
1 0 0 00
- 80
10 0
1 00 0
Freq u en cy (Hz)
1 0 0 00
Figure 41. Crosstalk vs. frequency
Figure 42. Crosstalk vs. frequency
0 V cc = 5V O ut pu t mode 1 - 2 0 S ing le Ended G = +2dB - 4 0 T a m b = 25C -6 0 -8 0 -1 0 0 -1 2 0 R L = 3 2 Po =5 0 m W RL = 1 6 Po = 8 0 mW
0 - 10
Crosstalk Level (dB)
Crosstalk Level (dB)
- 20 - 30 - 40 - 50 - 60 - 70
Vcc = 5V O u tp u t mode 1 Ph a nt o m Ground G = +2dB T am b = 25C
R L =3 2 P o= 5 0m W
R L= 16 Po =8 0 m W
100
1 0 00
F requ en cy (Hz)
1 0 0 00
- 80
10 0
1 00 0
Freq u en cy (Hz)
1 0 0 00
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TS4975
Figure 43. SNR vs. power supply voltage
Electrical Characteristics
Figure 44. SN R vs. power supply voltage
1 10 1 08 1 06 1 04 1 02 1 00 98 96 94 92 90 88 86 84 82 80
SNR (dB)
2 .5
3. 3
V cc (V)
5
SNR (dB)
RL = 32 RL = 16 O u t. mode 1 - 8 SE, G = +2dB Un w e ig ht ed filter (20Hz to 20kHz) T HD + N < 0.5% T am b = 25C
1 10 1 08 1 06 1 04 1 02 1 00 98 96 94 92 90 88 86 84 82 80
RL = 32 RL = 16 O u t. mode 1 - 8 SE, G = +2dB We ig h te d filter type A T HD + N < 0.5% T am b = 25C
2 .5
3. 3
V cc (V)
5
Figure 45. SNR vs. power supply voltage
Figure 46. SN R vs. power supply voltage
1 10 1 08 1 06 1 04 1 02 1 00 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
SNR (dB)
2 .5
3. 3
V cc (V)
5
SNR (dB)
RL = 32 RL = 16 O u t. mode 1 - 8 S E, G = +18dB U n w e igh t ed filter (20Hz to 20kHz) T H D +N < 0.5% T a m b = 25C
1 10 1 08 1 06 1 04 1 02 1 00 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
RL = 32 RL = 16 O ut . mode 1 - 8 S E, G = +18dB W e ig ht ed filter type A T H D +N < 0.5% T a m b = 25C
2 .5
3. 3
V cc (V)
5
Figure 47. SNR vs. power supply voltage
Figure 48. SN R vs. power supply voltage
1 10 1 08 1 06 1 04 1 02 1 00 98 96 94 92 90 88 86 84 82 80
SNR (dB)
2 .5
3. 3
V cc (V)
5
SNR (dB)
RL = 32 RL = 16 O u t. mode 1 - 8 PH G , G = +2dB Un w e ig ht ed filter (20Hz to 20kHz) T HD + N < 0.5% T am b = 25C
1 10 1 08 1 06 1 04 1 02 1 00 98 96 94 92 90 88 86 84 82 80
RL = 32 RL = 16 O u t. mode 1 - 8 PHG, G = +2dB W eig h te d filter type A T H D +N < 0.5% T am b = 25C
2 .5
3. 3
V cc (V)
5
19/36
Electrical Characteristics
Figure 49. SNR vs. power supply voltage
1 10 1 08 1 06 1 04 1 02 1 00 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
TS4975
Figure 50. SN R vs. power supply voltage
1 10 1 08 1 06 1 04 1 02 1 00 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
SNR (dB)
2 .5
3. 3
V cc (V)
5
SNR (dB)
RL = 32 RL = 16 O u t. mode 1 - 8 P H G , G = +18dB U n w e igh t ed filter (20Hz to 20kHz) T H D +N < 0.5% Tamb = 25C
RL = 32 RL = 16 O ut . mode 1 - 8 P H G , G = +18dB W e ig ht ed filter type A T H D +N < 0.5% T a m b = 25C
2 .5
3. 3
V cc (V)
5
Figure 51. Frequency response
Figure 52. Current consumption vs. power supply voltage
6 5
20 18 16 14
Output level (dB)
N o loads T a m b = 25C
PH G , Out. Mode 1, 2, 3, 4
Vc c = 5V, 3.3V, 2.5V G = +18dB
12 10 8 6 4 2 0 20 100 1000
Fr equ en cy (Hz)
Vc c = 5V, 3.3V, 2.5V G = +2dB
O u tp u t mode 1 - 8 R L = 32, 16 C in = 330nF SE , PHG BW < 125kHz T am b = 25C
4
Icc (mA)
P H G , Out. mode 5, 6, 7, 8
3 2 1 S E, Out. mode 5, 6, 7, 8 0 R e se t state S E, Out. mode 1, 2, 3, 4
10 0 0 0
0
1
2
3
V cc (V)
4
5
Figure 53. 3dB lower cut off frequency vs. input capacitance
Figure 54. 3dB lower cut off frequency vs. output capacitance
1 00 All gain setting T am b = 2 5 C
Low -3 dB Cut Off frequency (Hz) Low -3dB Cut Off Frequency (Hz)
1 00 A ll gain setting T a m b = 25C
M inim u m Input Im p e d a n c e
10
10
T yp ica l Input Im p e d a n c e M a xim um Input Im p e d a n c e
R L =1 6 R L =3 2
0 .1
In pu t Capacitor Cin (F)
1
1 1 00
1000
O u tp ut capacitor Cout (F)
20/36
TS4975
Electrical Characteristics
Figure 55. Power dissipation vs. output power Figure 56. Power dissipation vs. output power (one channel (one channel
70
V cc = 2.5V F = 1kHz 60 T H D +N < 1% 50 40 30 20 R L= 32 , SE 10 0
Power Dissipation (mW) Power Dissipation (mW)
1 20
V cc = 3.3V 1 10 F = 1kHz 1 00 T H D + N < 1% 90 80 70 60 50 40 30 20 10 0 R L =3 2 , SE R L= 16 , SE R L =1 6 , PHG R L= 3 2 , PHG RL = 16 , SE R L =1 6 , PHG R L= 32 , PHG
0
5
10
15
20
25
0
5
10
15
20
25
30
35
40
45
O u t pu t Power (mW)
O u tp u t Power (mW)
Figure 57. Power dissipation vs. output power Figure 58. Power derating curves (one channel
2 80 V cc = 5V 2 60 F = 1kHz 2 40 T H D +N < 1% 2 20 2 00 1 80 1 60 1 40 1 20 1 00 80 60 40 20 0 0 10 2 0 3 0
Flip-Chip Package Power Dissipation (W)
1. 4 1. 2 1. 0 0. 8 0. 6 0. 4 N o Heat sink 0. 2 0. 0 H e a t sink surface = 125mm
2
Power Dissipation (mW)
R L =1 6 , PHG RL = 32 , PHG R L= 16 , SE R L= 32 , SE
40
50
60
70
80
90 1 00 1 1 0
0
25
50
75
1 00
125
150
O u tp u t Power (mW)
A m bia nt Temperature (C)
21/36
Application Information
TS4975
4
Application Information
The TS4975 integrates 2 monolithic power amplifiers. The amplifier output can be configured as either SE (single-ended) capacitively-coupled output or PHG (phantom ground) output. Figure 1 on page 3 and Figure 2 on page 4 show schemes of these two configurations and Section 4.2: Output configuration describes these configurations. This chapter gives information on how to configure the TS4975 in application.
4.1
I²C bus interface
The TS4975 uses a serial bus, which conforms to the I²C protocol (the TS4975 must be powered when it is connected to I²C bus), to control the chip's functions with two wires: Clock and Data. The Clock line and the Data line are bi-directional (open-collector) with an external chip pull-up resistor (typically 10 kOhm). The maximum clock frequency in Fast-mode specified by the I²C standard is 400kHz, which TS4975 supports. In this application, the TS4975 is always the slave device and the controlling micro controller MCU is the master device. The ADD pin is allows one to set one of two possible 7-bit device addresses. This setting is needed for when a number of chips are connected to the same bus (for example two TS4975 devices), to avoid address conflicts. The two possible TS4975 addresses are:
$CCh when the ADD pin is connected to logic low voltage, $CEh when ADD pin is connected to logic high voltage.
Table 8 summarizes the pin descriptions for the I²C bus interface.
Table 8.
Pin SDA SCL AD D This is the serial data pin This is the clock input pin User-setable portion of device's I2C address
I²C bus interface pin descriptions
Functional Description
4.1.1
I²C bus operation
The host MCU can write into the TS4975 control register to control the TS4975, and read from the control register to get a configuration from the TS4975. The TS4975 is addressed by the byte consisting of 7-bit slave address and R/W bit. Table 9.
A6 1
The first byte after the START message for addressing the device
A5 1 A4 0 A3 0 A2 1 A1 1 A0 A0 R/W X
In order to write data into the TS4975, after the "start" message, the MCU must send the following data:
send byte with the I²C 7-bit slave address and with a low level for the R/W bit send the data (control register setting)
22/36
TS4975
Application Information
All bytes are sent with MSB bit first. The transfer of written data ends with a "stop" message. When transmitting several data, the data can be written with no need to repeat the "start" message and addressing byte with the slave address. In order to read data from the TS4975, after the "start" message, the MCU must send and receive the following data:
send byte with the I²C 7-bit slave address and with a high level for the R/W bit receive the data (control register value)
All bytes are read with MSB bit first. The transfer of read data is ended with "stop" message. When transmitting several data, the data can be read with no need to repeat the "start" message and the byte with slave address. In this case the value of control register is read repeatedly. W hen the thermo shutdown or pop and click reduction is active, specific values are read from the TS4975 (see Section 4.9: Pop and click performance on page 31 and Section 4.10: Thermo shutdown on page 32). Figure 59. I²C write/read operations
SLAVE ADDRESS CONTROL REGISTERS
SDA
S
1
1
0
0
1
1 A0
0
A
D7 D6 D5 D4 D3 D2 D1 D0 A
P
Start condition
Volume Control setting s
O utput Mode settings
Stop condition Acknowledge from Slave
R/W Acknowledge from Slave
Pha nto m Gro und setting s
Table 10.
Ouput mode selection: G from -34 dB to + 18dB (by steps of 4dB)(1)
Headphone Output 1 SD G x In1 G x In2 G x In1 G x In2 SD SD G x In1 G x In2 Headphone Output 2 SD G x In2 G x In1 G x In1 G x In2 G x In1 G x In2 SD SD
Output Mode # 0 1 2 3 4 5 6 7 8
1. SD = Shutdown Mode In1 = Audio Input 1 In2= Audio Input2 G = Gain from Audio Input 1and Input 2 to Output1 and Output2
23/36
Application Information
TS4975
4.1.2
Gain setting operation
The gain of the TS4975 ranges from -34dB to +18 dB. At Power-up, both the right and left channels are set in Standby mode. Table 11. Gain settings truth table
D7 (MSB) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 D6 0 0 0 1 1 1 1 0 0 0 0 1 1 1 D5 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D4 1 0 1 0 1 0 1 0 1 0 1 0 1 0
G: Gain (dB) # -34 -30 -26 -22 -18 -14 -10 -6 -2 +2 +6 +10 +14 +18
Table 12.
Output mode settings truth table
D2 X x 0 0 0 0 1 1 1 1 D1 X x 0 0 1 1 0 0 1 1 D0 X x 0 1 0 1 0 1 0 1 C O M ME N T S PHG off PHG on MOD E 1 MOD E 2 MOD E 3 MOD E 4 MOD E 5 MOD E 6 MOD E 7 MOD E 8
D3: PHG on / off 0 1 x X X X X X X X
Table 13.
D7 (MSB) 0
Stand-by mode I²C condition
D6 0 D5 0 D4 0 D3 X D2 X D1 X D0 X
24/36
TS4975
Table 14.
D7 (MSB) 1
Application Information
I²C control byte states
D6 1 D5 1 D4 1 D3 x D2 X D1 X D0 X Undefined State
4.1.3
Acknowledge
The number of data bytes transferred between the start and the stop conditions from the CPU master to the TS4975 slave is not limited. Each byte of eight bits is followed by one acknowledge bit. The TS4975 which is addressed, generates an acknowledge after the reception of each byte that has been clocked out.
4.2
Output configuration
W hen the device is switched to Mode 5,6,7 or 8, where one channel is in shutdown, it means that corresponding output is in a high impedance state.
4.2.1
Single-ended configuration
W hen the device is woken-up or switched via I²C interface to SE configuration, output amplifiers are biased to the VCC/2 voltage and this voltage is present on OUT1 and OUT2 pins. Pins PHG1 and PHG2 are in high impedance state. In this configuration an output capacitor, Cout, on each output is needed to block the VCC/2 voltage and couples the audio signal to the load.
4 .2 .2
Phantom ground configuration
In a PHG configuration the internal buffers are connected to PHG1 and PHG2 pins and biased to the VCC/2 voltage. Output amplifiers (pins OUT1 and OUT2) are also biased to the VCC/2 voltage. Therefore, no output capacitors are needed. The advantage of the PHG configuration is the need for fewer external components as compared with a SE configuration. However, note that the device has higher power dissipation (see Section 4.3: Power dissipation and efficiency on page 26). In this configuration, PHG1 and PHG2 pins must be shorted and the connection between these pins should be as short as possible. For best crosstalk results, in this case, each speaker should be connected with a separate PHG wire (2 speakers connected with 4 wires) as shown in Figure 2: Phantom ground output configuration on page 4. You should avoid using only one common PHG wire for both speakers (i.e. 2 speakers connected with 3 wires), which would give much poorer crosstalk results.
4.2.3
Shutdown
W hen the device goes to shutdown from SE or PHG mode, PHG1 and PHG2 outputs are in a high impedance state and OUT1 and OUT2 outputs are shorted together and connected to bias voltage. This voltage steadily decreases as the bypass capacitor Cb discharges, and reaches GND voltage when Cbypass is fully discharged. This output configuration is implemented to reach the best pop performance during chip wake-up.
25/36
Application Information
TS4975
4.3
Power dissipation and efficiency
Hypotheses:
Voltage and current in the load are sinusoidal (Vout and I out). Supply voltage is a pure DC source (VCC).
V o u t = V P E A K sin t ( V )
R egarding the load we have:
and
Vou I o u t = ----------t RL (A)
and
VP A P o u t = --------E-----K -- -2RL
2
(A )
Single-ended configuration:
The average current delivered by the supply voltage is:
Ic cA V G V PE A K 1 VP A K = ------ --------E------- sin ( t ) dt = -----------------2 RL RL
0
(A)
Figure 60. Current delivered by supply voltage in single-ended model
The power delivered by supply voltage is:
P s u p p l y = VC CI C C
A VG
(W)
So, the power dissipation by each amplifier is
Pd i s s = P s u p p l yP o u t ( W ) 2VC -P d i s s = ----------------C P o u t P o u t ( W ) RL
and the maximum value is obtained when:
P d i s s P o ut =0
26/36
TS4975
and its value is:
Pd i ss
M AX
Application Information
VC = ---------C--2 RL
2
(W)
Not e:
This maximum value depends only on power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply:
V E K Po ut -- - = ------------------ = --------P-----A--Ps up pl y 2 VC C
The maximum theoretical value is reached when VPEAK = VCC/2, so
= -- = 78.5 % 4
Phantom ground configuration:
The average current delivered by the supply voltage is:
I c cA VG 2V E K 1 VP E K = -- -----------A---- sin ( t ) d t = --------P-----A----- - RL R L
0
(A )
Figure 61. Current delivered by supply voltage in phantom ground mode
The power delivered by supply voltage is:
P s u p p l y = VC CI C C
A VG
(W)
Then, the power dissipation by each amplifier is
2 2V C P d i s s = ----------------C---- P o u t P o u t - RL (W)
and the maximum value is obtained when:
P d i s s P o ut =0
and its value is:
P d is s
MA X
2V = --------C-C ----2 RL
2
(W)
Not e:
This maximum value depends only on power supply voltage and load values.
27/36
Application Information
The efficiency is the ratio between the output power and the power supply:
Po ut V E K = ------------------ = --------P-----A---- -Ps up pl y 4 VC C
TS4975
The maximum theoretical value is reached when VPEAK = VCC/2, so
= -- = 39.25 % 8
The TS4975 is a stereo amplifier so it has two independent power amplifiers. Each amplifier produces heat due to its power dissipation. Therefore the maximum die temperature is the sum of each amplifier's maximum power dissipation. It is calculated as follows:
Pdiss 1 = Power dissipation due to the first channel power amplifier. Pdiss 2 = Power dissipation due to the second channel power amplifier. Total Pdiss = Pdiss 1 + Pdiss 2 (W)
In most cases, Pdiss 1 = Pdiss 2 , giving:
T o ta l Pd is s = 2 P d i ss 1
Single ended configuration:
2 2V C T o t a l P d i s s = ----------------C---- P o u t 2 P o u t ( W ) - RL
Phantom ground configuration:
4 2V C T o t a l Pd i s s = ----------------C---- P o u t 2 P o u t ( W ) - RL
4.4
Low frequency response
Input capacitor Cin
The input coupling capacitor blocks the DC part of the input signal at the amplifier input. In the low-frequency region, Cin starts to have an effect. Cin with Zin forms a first-order, high-pass filter with -3 dB cut-off frequency.
1 F C L = ----------------------- ( H z ) 2 Z i n Cin
Zin is the input impedance of the corresponding input (30 k for In1 & In2).
Not e:
For all inputs, the impedance value remains for all gain settings. This means that the lower cutoff frequency doesn't change with gain setting. Note also that 30 k is a typical value and there is tolerance around this value (see Chapter 3: Electrical Characteristics on page 5).
From Figure 53 you could easily establish the Cin value for a -3dB cut-off frequency required.
28/36
TS4975
Application Information
Output capacitor Cout
In single-ended mode the external output coupling capacitors Cout are needed. This coupling capacitor Cout with the output load RL also forms a first-order high-pass filter with -3 dB cut off frequency.
1 F C L = ------------------------- ( H z ) 2 R LC o ut
See Figure 54 to establish the Cout value for a -3dB cut-off frequency required. These two first-order filters form a second-order high-pass filter. The -3 dB cut-off frequency of these two filters should be the same, so the following formula should be respected:
1 1 ----------------------- ------------------------2 Z i n Cin 2 RL Co u t
4.5
Decoupling of the circuit
Two capacitors are needed to properly bypass the TS4975 -- a power supply capacitor Cs and a bias voltage bypass capacitor Cb. Cs has a strong influence on the THD+N in high frequency (above 7kHz) and indirectly on the power supply disturbances. W ith 1 F, you could expect similar THD+N performances like shown in the datasheet. If Cs is lower than 1 F, THD+N increases in high frequency and disturbances on power supply rail are less filtered. To the contrary, if Cs is higher than 1 F, those disturbances an the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with input grounded in lower frequency:
If Cb is lower than 1 F, THD+N increases at lower frequencies and the PSRR worsens upwards. If Cb is higher than 1 F, the benefit on THD+N and PSRR in the lower frequency range is small.
The value of Cb also has an influence on startup time.
4.6
Power-on reset
W hen power is applied to VCC, an internal Power On Reset holds the TS4975 in a reset state (shutdown) until the supply voltage reaches its nominal value. The Power On Reset has a typical threshold of 1.75V. During this reset state the outputs configuration is the same like in the shutdown mode (see Section 4.2: Output configuration on page 25).
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Application Information
TS4975
4.7
Notes on PSRR measurement
What is PSRR?
The PSRR is the Power Supply Rejection Ratio. The PSRR of a device is the ratio between a power supply disturbance and the result on the output. In other words, the PSRR is the ability of a device to minimize the impact of power supply disturbance to the output.
How we measure the PSRR?
The PSRR was measured according to the schematic shown in Figure 62. Figure 62. PSRR measurement schematic
Principles of operation
The DC voltage supply (VCC) is fixed The AC sinusoidal ripple voltage (Vripple) is fixed No bypasss capacitor Cs is used
The PSRR value for each frequency is calculated as:
R M S( O u t ) P S R R = 20 L o g -----------------------t-p-u--- ( d B ) ----RMS(V )
ri p p le
R MS is a rms selective measurement.
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TS4975
Application Information
4.8
Startup time
W hen the TS4975 is controlled to switch from full standby (output mode 0) to another output mode, a delay is necessary to stabilize the DC bias.This length of this delay depends on the Cb and VCC values. A typical value can be calculated by following formula:
VC C t w u = C b × ------------------------ × 50000 + 0.008 ( s ) V C C 1. 2
This formula assumes that Cb voltage is equal to 0 V. If the Cb voltage is not equal 0 V, the startup time will be always lower. In Figure 63 you could easily establish typical startup time for given supply voltage and bypass capacitor Cb. Figure 63. Typical startup time versus bypass capacitance
4 00 3 50 3 00
Startup time (ms)
2 50 2 00 1 50 1 00 50 0 0 .4 0 .8
V c c = 2 .5 V
V cc = 3. 3 V
V c c= 5 V
1 .2
1 .6
2 .0
2 .4
2 .8
3 .2
3.6
4 .0
B y p a s s capacitor Cb (F)
4.9
Pop and click performance
The TS4975 has internal pop and click reduction circuitry which eliminates the output transients, for example during switch-on or switch-off phases, during a switch from an output mode to another or during change in volume. The performance of this circuitry is closely linked to the values of the input capacitor Cin, the output capacitor Cout (for Single-Ended configuration) and the bias voltage bypass capacitor Cb. The value of Cin and Cout is determined by the lower cut-off frequency value requested. The value of Cb will affect the THD+N and PSRR values in lower frequencies. The TS4975 is optimized to have a low pop and click in the typical schematic configuration (see Figure 1 on page 3 and Figure 2 on page 4). D uring the device start-up period when the pop and click reduction is active, the value $Fxh (1111xxxx binary) can be read from the internal device registry. Once the device is fully operational and the pop and click is inactive, the last value of control register can be read.
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Application Information
TS4975
4.10
Thermo shutdown
The TS4975 device has internal protection in case of over temperature by thermal shutdown. Thermal shutdown is active when the device reaches temperature 150C. When thermo shutdown protection is active, value $Fxh (1111xxxx binary) can be read from the internal device registry. W hen thermo shutdown protection state disappears, the last value of control register can be read.
4.11
Demoboard
A demoboard for the TS4975 is available. For more information about this demoboard, please refer to Application Note AN2151, which can be found on www.st.com.
Figure 67 on page 33 shows the schematic of the demoboard. Figure 64, Figure 65 and Figure 66, show bottom layer, top layer and the component locations, respectively.
Figure 64. Bottom layer Figure 65. Top layer
Figure 66. Component location
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TS4975
Figure 67. Demoboard schematic
V cc1 Vcc1
Application Information
Cn1 + C1 1 F + C2 1 F
14
U1 Cn6 R1 1k
2
B ypa ss
B ia s
IN 1 P re -Amp lif ie r P1 IN 1 + 3 3 0n F P HG 1 Amplifier C10 1 O UT1 Amplifier
V cc
IN1
OUT1
13
2 2 0 F JP 1 1 2 3 4 HE ADER 4 P HG 2 Amplifier
1 2 3
C3 +
Cn7
P H G1 Mo de Se lect
12
1 J1 2 3 PHONE JA CK STEREO
P H G2
10
IN 2 P re -Amp lif ie r P2 IN 2 + 3 3 0n F C11 6
O UT2 Amplifier C4
IN2
OUT2
9
+ 2 2 0 F
Vo lume control
G ND A DD
I2C
S CL S DA
1 2 3
R2 1k
TS49 75
Cn8
8
5
3
Vcc1
4
JP 2 R3 10 k 4 3 2 1 Cn 4 Cn 3 HE ADE R 4 Vcc1 V cc1
Cn2
1 2 3
R4 10 k
R5 10k
I2C BUS
S DA
S CL S DA
S CL
S DA
S DA V cc2
S CL
Vcc1
Vcc2
Vcc2 R8 18 0 R U2 A 1 CON1 1 6 2 7 3 8 4 9 5 RS2 3 2 G ND2 2 KP 104 0 G ND2 15 GND2 13 8 11 10 G ND2 R1 IN R2 IN T1 IN T2 IN C1 + C1 C2 + C2 V+ V16 R7 10 K Cn5 16 Vcc2
R6 3 6 0R U2 B 3 4 V cc2
14 13
C5 1F
K P1 040
+
U3 R1O UT R2O UT T1O UT T2O UT 12 9 14 7
R9 3 6 0R U2 C 5 6 K P1 040
12 11
DTR GN D
+ C6 0 .1 F GND2 C7 0 .1 F 1 3 4 5 2 6 C9 0.1 F +
+
C8 0.1 F
+
G ND GND2 15 S T2 3 2
V cc2 GND2
Vcc
TX D
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Package Mechanical Data
TS4975
5
Package Mechanical Data
Figure 68. TS4975 footprint recommendation
500m =250m 500m 75m min. 100m max. Track
500m
=400m typ. =340m min.
150m min.
Non Solder mask opening
500m
Pad Pad in Cu 18m with Flash NiAu (2-6m, 0.2m max.)
Figure 69. Pin out (top view)
3
OU T1 PH G 1 P HG2 OU T2
2
IN 1
VC C
GND
IN 2
1
B Y P AS S
S CL
SDA
ADD
A
B
C
D
Figure 70. Marking (top view)
Logo: ST Part Number: A75 Date Code: YWW The Dot is for marking pin A1
E
E Lead Free symbol
A75 YW W
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TS4975
Figure 71. Flip-chip - 12 bumps
2300m
Package Mechanical Data
1800m 500m
Die size: 2.3mm x 1.8mm 30m Die height (including bumps): 600m Bumps diameter: 315m 50m Bump diameter before reflew: 300m 10m Bumps height: 250m 40m Die height: 350m 20m Pitch: 500m 50m Capillarity: 60m max
500m 500m
600m
Figure 72. Tape & reel specification (top view)
4
1.5
1 A A
Die size Y + 70m
1
8
Die size X + 70m
4
All dimensions are in mm
User direction of feed
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Revision History
TS4975
6
Revision History
Date Nov. 2004 July 2005 Nov. 2005 Revision 1 2 3 Initial release. Product in full production The following changes were made in this revision: Application notes updated Formatting changes throughout Chang es
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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