STG3685
LOW VOLTAGE 0.5 MAX DUAL SPDT SWITCH, SINGLE ENABLE WITH BREAK BEFORE MAKE FEATURE
PRELIMINARY DATA
I
I
I
I
I
I
I
H IGH SPEED: tPD = 0.3ns (TYP.) at VCC = 3.0V tPD = 0.4ns (TYP.) at VCC = 2.3V U LTRA LOW POWER DISSIPATION: ICC = 0.2A (MAX.) at TA = 85C LOW "ON" RESISTANCE VI = 0V: RON = 0.4 (MAX. TA = 25C) at VCC = 4.2V RON = 0.5 (MAX. TA = 25C) at VCC = 3.0V RON = 0.6 (MAX. TA = 25C) at VCC = 2.3V W IDE OPERATING VOLTAGE RANGE: VCC (OPR) = 1.4V to 4.3V SINGLE SUPPLY 4.3V TOLERANT AND 1.8V COMPATIBLE THRESHOLD ON DIGITAL CONTROL INPUT at VCC = 2.3 to 4.3V LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17) ESD PERFORM. (ANALOG CHAN. vs GND): H BM > 4KV (MIL STD 883 method 3015)
Flip-Chip
Table 1: Order Codes
PACKAGE Flip-Chip9 T&R STG3685BJR
DESCRIPTION The STG3685 is an high-speed CMOS DUAL ANALOG S.P.D.T. (Single Pole Dual Throw) SWITCH or DUAL 2:1 Multiplexer/Demultiplexer Bus Switch fabricated in silicon gate C2MOS technology. It is designed to operate from 1.4V to 4.3V, making this device ideal for portable applications. It offers very low ON-Resistance (<0.5) at VCC=3.0V. The IN input is provided to control the switches. The switches nS1 are ON (they are
connected to common Ports Dn) when the IN input is held high and OFF (high impedance state exists between the two ports) when IN is held low; the switches nS2 are ON (they are connected to common Ports Dn) when the IN input is held low and OFF (high impedance state exists between the two ports) when IN is held high. Additional key features are fast switching speed, Break Before Make Delay Time and Ultra Low Power Consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. It's available in the commercial temperature range Flip-chip package with Epoxy Protection.
Figure 1: Pin Connection (Top Through View) And Schematic Circuit
July 2005
Rev. 2
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STG3685
Figure 2: Input Equivalent Circuit Table 2: Pin Description
PIN N B2 A3, A1 C3, C1 B3, B1 C2 A2 SYMBOL IN 2S1, 1S1 2S2, 1S2 D2, D1 GND V CC NAME AND FUNCTION Control Independent Channels Common Channels Ground (0V) Positive Supply Voltage
Table 3: Truth Table
IN H L
(*) High Impedance
SWITCH S1 ON OFF(*)
SWITCH S2 OFF(*) ON
Table 4: Absolute Maximum Ratings
Symbol V CC VI VIC VO IIKC IIK IOK IO IOP PD Tstg TL Parameter Supply Voltage DC Input Voltage DC Control Input Voltage DC Output Voltage DC Input Diode Current on control pin (VIN < 0V) DC Input Diode Current (VIN < 0V) DC Output Diode Current DC Output Current DC Output Current Peak (pulse at 1ms, 10% duty cycle) Power Dissipation at Ta=70C (1) Storage Temperature Lead Temperature (10 sec) Value -0.5 to 4.6 -0.5 to VCC + 0.5 -0.5 to 4.6 -0.5 to VCC + 0.5 - 50 50 20 300 500 100 TBD -65 to 150 260 Unit V V V V mA mA mA mA mA mA mW C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. (1) Derate above 70C: by 18.5mW/C.
Table 5: Recommended Operating Conditions
Symbol VCC VI VIC VO Top dt/dv Parameter Supply Voltage (note 1) Input Voltage Control Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time Control Input VCC= 1.4V to 2.7V VCC= 3.0V to 3.6V Value 1.4 to 4.3 0 to VCC 0 to 4.3 0 to VCC -55 to 125 0 to 20 0 to 10 Unit V V V V C ns/V
1) Truth Table guaranteed: 1.2V to 4.3V.
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STG3685
Table 6: DC Specifications
Test Conditions Symbol Parameter VCC (V) TA = 25C Min. Typ. Max. Value -40 to 85C Min. 0.65VCC 1.4 1.4 1.5 1.6 1.6 0.40 0.50 0.50 0.50 0.50 0.50 400 500 500 600 2000 2500 0.40 0.50 0.50 0.50 0.50 0.50 500 600 600 800 4000 5000 Max. -55 to 125C Min. 0.65VCC 1.4 1.4 1.5 1.6 1.6 0.40 0.50 0.50 0.50 0.50 0.50 Max. Unit
VIH
VIL
RO N
RFLAT
IOFF
IIN
ICCL
ICCH
High Level 1.65-1.95 0.65VCC Input Voltage 2.3-2.5 1.4 2.7-3.0 1.4 3.3 1.5 3.6 1.6 4.3 1.6 Low Level 1.65-1.95 Input Voltage 2.3-2.5 2.7-3.6 3.3 3.6 4.3 250 Switch ON 4.3 Resistance 3.0 300 (See Fig. 12) VS=0V to VCC 2.7 300 IS=100mA 2.3 350 1.8 550 1.4 1200 ON 4.3 Resistance 3.0 VS=0 to VCC FLATNESS 2.7 0.07 IS=100mA (1) 2.3 1.65 OFF State 4.3 VS=0.3 or 4V Leakage Current (nSn), (Dn) Input 0 - 4.3 VIN=0 to 4.3V Leakage Current Quiescent 1.65-4.3 VIN=VCC or Supply GND Current Quiescent 415 4.2 VIN=1.65V Supply 360 VIN=1.8V Current 120 VIN=2.6V
V
V
m
0.15
0.15
10
100
nA
0.1 0.05
1 0.2 1
A A A
500 400 150
Note 1: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges.
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STG3685
Table 7: AC Electrical Characteristics (CL = 35pF, R L = 50, tr = tf 5ns)
Test Condition Symbol Parameter VCC (V) 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 TA = 25C Min. Typ. 0.45 0.40 0.30 0.30 VS=0.8V VS=1.5V VS=0.8V VS=1.5V 70 32 32 30 45 25 15 15 2 2 2 15 15 15 50 40 35 35 30 30 30 40 40 40 ns 50 50 50 60 60 60 ns Max. Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit
tPLH, tPHL Propagation Delay
ns
tON
TURN-ON time
tOFF
TURN-OFF time
tD
Break Before Make Time Delay
CL=35pF RL= 50 VS=1.5V CL= 100pF RL= 1M VGEN= 0V RGEN= 0
ns
Q
Charge injection
pC
Table 8: Analog Switch Characteristics (CL = 5pF, RL = 50, TA = 25C)
Test Condition Symbol Parameter VCC (V) VS= 1VRMS f= 100KHz 1.65-4.3 VS= 1VRMS f= 100KHz 2.3-4.3 RL= 600 VI= 2VPP f = 20Hz to 20kHz 1.65-4.3 RL= 50 1.65-4.3 TA = 25C Min. Typ. -64 -32 Max. Value -40 to 85C Min. Max. -55 to 125C Min. Max. dB dB Unit
OIRR Xtalk THD
Off Isolation (1) Crosstalk Total Harmonic Distortion -3dB Bandwidth Control Pin Input Capacitance Sn Port Capacitance D Port Capacitance when Switch is Enabled
0.03 50 10
% M Hz
BW CIN C Sn CD
3.3 3.3
f = 1MHz f = 1MHz
35 91
pF
Note 1: Off Isolation = 20Log10 (VD/VS), VD = output. VS = input at off switch.
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STG3685
Figure 3: On Resistance Figure 6: Bandwidth
Figure 4: Off Leakage
Figure 7: Channel To Channel Crosstalk
Figure 5: Off Isolation
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STG3685
Figure 8: Test Circuit
CL = 5/35pF or equivalent (includes jig and probe capacitance) RL = 50 or equivalent RT = ZOUT of pulse generator (typically 50)
Figure 9: Break Before Make Time Delay
Figure 10: Charge Injection (VGEN = 0V, RGEN = 0, RL = 1M, C L = 100pF)
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STG3685
Figure 11: Turn On, Turn Off Delay Time
TYPICAL CHARACTERISTICS Figure 12: Switch-On RON vs VIN
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Flip-Chip9 MECHANICAL DATA
mm. DIM. MIN. A B C D E F G H 0.061 0.35 0.295 0.32 0.5 0.40 0.25 0.0635 0.066 2.4 0.45 13.8 1.59 1.42 TYP 1.64 1.47 M AX. 1.69 1.52 0.80 0.345 11.6 12.6 19.7 15.7 9.8 2.5 2.6 17.7 MIN. 62.6 55.9 TYP. 64.6 57.9 M AX . 66.5 59.8 31.5 13.6 mils
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STG3685
Table 9: Revision History
Date 13-Jan-2005 04-Jul-2005 Revision 1 2 Description of Changes First Release. The Q Values on Table 7 has been updated.
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STG3685
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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