EMIF10-LCD01F2
IPADTM 10 line EMI filter and ESD protection
Main product characteristics:
Where EMI filtering in ESD sensitive equipment is required :
LCD for Mobile phones Computers and printers Communication systems MCU Boards F l i p - Ch i p (25 bumps)
Description
The EMIF10-LCD01F2 is a 10 line highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 Flip-Chip packaging means the package size is equal to the die size. This filter includes ESD protection circuitry, which prevents damage to the application when it is subjected to ESD surges up to 15 kV.
Order code
Part Number EMIF10-LCD01F2 Marking FL
Figure 1.
Pin Configuration (bump side)
5
I5 I10
GND
4
I4 I9
GND
3
I3 I8
GND
2
I2 I7
GND
1
I1 I6
GND
A B C D E
Benefits
EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consuming: < 6 mm2 Lead free package Very thin package: 0.69 mm High efficiency in ESD suppression on input pins (IEC 61000-4-2 level 4) High reliability offered by monolithic integration High reducing of parasitic elements through integration and wafer level packaging.
GND GND GND Input
O10 O5 O9 O4 O8 O3 O7 O2 O6 O1
Figure 2.
Basic Cell Configuration
Low-pass Filter
Output
Ri/o = 100 Cline = 35pF
Complies with following standards:
IEC 61000-4-2
level 4 input pins 15 kV 8 kV (air discharge) (contact discharge)
MIL STD 883G - Method 3015-7 Class 3
TM: IPAD is a trademark of STMicroelectronics.
January 2007
Rev 3
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www.st.com 8
Characteristics
EMIF10-LCD01F2
1
Table 1.
Symbol Tj Top Tstg
Characteristics
Absolute Maximum Ratings (Tamb = 25 C)
Parameter Junction temperature Operating temperature range Storage temperature range Value 125 -40 to + 85 -55 to +150 Unit C C C
:
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM RI/O Cline Rt / Ft
Electrical Characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic resistance Peak pulse current Series resistance between Input and Output Input capacitance per line Test conditions IR = 1 mA VRM = 3 V 90 @ 0 V bias Induced rise and fall time 10-90% at 26 MHz frequency signal V = 1.9 V (Rt / Ft input 1 ns, 50 impedance generator) 100 28 8(1) Min. 6 Typ. 8 Max. 10 500 110 35 Unit V nA pF ns
IPP VCL VBR VRM IRM IR VF V I
IF
1. guaranteed by design
Figure 3.
0 -10 -20 -30 -40
S21(dB) attenuation measurement
Figure 4.
dB
Analog cross talk measurement
dB
10 -10 -30 -50 -70
F(Hz)
F(Hz) 1.0 M 10.0 M 100.0 M 1.0 G 10.0 G
-50 0.1 M
1.0 M
10.0 M
100.0 M 1.0 G
10.0 G
-90 0.1 M
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EMIF10-LCD01F2
Characteristics
Figure 5.
ESD response to IEC 61000-4-2 Figure 6. (+15 kV air discharge) on one input and on one output
ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input and on one output
Vin
Vin
Vout
Vout
Figure 7.
Line capacitance versus applied voltage
Figure 8.
Rise time 10-90% measurements with 1.9 V signal at 26 MHz frequency (50 generator)
CLine( pF) 35 30 25 20 15 10 5 0 0.0 1.0
VLine(V) 2.0 3.0 4.0 5.0
Figure 9.
Fall time 10-90% measurements with 1.9 V signal at 26 MHz frequency (50 generator)
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Characteristics Figure 10. Aplac model
EMIF10-LCD01F2
EMIF10-LCD01F2 model
Ground return
Figure 11. Aplac parametersl
ZRZ structure aplacvar Remif10low 100 aplacvar Cemif10flow 17.5pF Bumps aplacvar Lbump 50pH aplacvar Rbump 20m aplacvar Cbump 1.5pF Bulk aplacvar Rsub 100m Gnd connections aplacvar Rgnd 100m aplacvar Lgnd 200pH aplacvar Cgnd 0.15pF
BV = 7 CJO = Cemif10low IBV = 1u IKF = 1000 IS = 10f ISR = 100p N=1 M = 0.3333 RS = 0.015 VJ = 0.6 TT = 50n
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EMIF10-LCD01F2
Ordering information scheme
2
Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip-Chip x = 1: 500m, Bump = 315m = 2: Leadfree Pitch = 500m, Bump = 315m = 3: Leadfree Pitch = 400m, Bump = 250m
yy
-
xxx zz
Fx
3
Package information
Figure 12. Flip-Chip Dimensions
500 m 50
500 m 50
315 m 50
650 m 65
2.42 mm 50m
2.42 mm 50m
250 m 40
Figure 13. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
Figure 14. Footprint recommendation
Copper pad Diameter: 250m recommended, 300 m max
E
xxz y ww
Solder stencil opening: 330 m
Solder mask opening recommendation: 340 m min for 315 m copper pad diameter
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Ordering information Figure 15. Flip-Chip tape and reel specification
Dot identifying Pin A1 location 4 +/- 0.1
EMIF10-LCD01F2
Ø 1.5 +/- 0.1
1.75 +/- 0.1 3.5 +/- 0.1
0.73 +/- 0.05
All dimensions in mm
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Note: More packing information is available in the application notes: AN1235: "Flip-Chip: Package description and recommendations for use" AN1751: "EMI Filters: Recommendations and measurements"
8 +/- 0.3
ST E
ST E
ST E
xxz yww
xxz yww
xxz yww
4 +/- 0.1
User direction of unreeling
4
Ordering information
Ordering code EMIF10-LCD01F2 Marking FL Package Flip-Chip Weight 9.3 mg Base qty 5000 Delivery mode Tape and reel (7")
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EMIF10-LCD01F2
Revision history
5
Revision history
Date 14-Feb-2005 17-Mar-2005 30-Jan-2007 Revision 1 2 3 Initial release. Capacitance Cline specification changed from 47 pF (typ) to 28 pF (typ) and 35 pF (max). Reformatted to current standards. Reduced die size and updated Figures 3 and 4. Changes
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EMIF10-LCD01F2
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