L6668
SMART PRIMARY CONTROLLER
1
General Features
MULTIPOWER BCD TECHNOLOGY LOAD-DEPENDENT CURRENT-MODE CONTROL: FIXED-FREQUENCY (HEAVY LOAD), FREQUENCY FOLDBACK (LIGHT LOAD), BURST-MODE (NO-LOAD) ON-BOARD HIGH-VOLTAGE START-UP IMPROVED STANDBY FUNCTION LOW QUIESCENT CURRENT (< 2 mA) SLOPE COMPENSATION PULSE-BY-PULSE & HICCUP-MODE OCP INTERFACE WITH PFC CONTROLLER DISABLE FUNCTION (ON/OFF CONTROL) LATCHED DISABLE FOR OVP/OTP FUNCTION PROGRAMMABLE SOFT-START 2% PRECISION REFERENCE VOLTAGE EXTERNALLY AVAILABLE 800 mA TOTEM POLE GATE DRIVER WITH INTERNAL CLAMP AND UVLO PULL-DOWN BLUE ANGEL, ENERGY STAR, EU CODE OF CONDUCT COMPLIANT
Figure 1. Package
SO-16 (Narrow)
Table 1. Order Codes
Part Number L6668 L6668TR
Package SO-16 SO-16 in Tape & Reel
SO16 PACKAGE ECOPACK
1.1 APPLICATIONS
HI-END AC-DC ADAPTERS/CHARGERS FOR NOTEBOOKS. LCD/CRT MONITORS, LCD/CRT TV DIGITAL CONSUMER
Figure 2. Block Diagram
S-COMP 15 1 HV 5 V CC
SLO PE COMP.
16 RCT CLK
25V HV generator ON/OFF and UVLO management Vcc_O K
VREG Vref 8 VREF
TIMING
DIS
+ 7 2.2V
R S Q DIS 15V 4 O UT BLANKING + PWM OCP Q + S R Q
N.C.
6
12 ISEN 1.5V
HICCUP + -
R S
Vcc _OK DIS
VREG
3 GND
HYST. CTRL 0.4mA 13 STANDBY ST-BY
PFC_STO P 14
DIS O CP
+ 2.2/2.7V 0.8V 9 SKIPADJ SS 4R 11R SOFT -START 11 10 COMP
January 2006
Rev. 4 1/23
L6668
2
Description
L6668 is a current-mode primary controller IC, designed to build single-ended converters. The IC drives the system at fixed frequency at heavy load and an improved Standby function causes a smooth frequency reduction as the load is progressively reduced. At very light load the device enters a special operating mode (burst-mode with fixed, externally programmed peak current) that, in addition to the on-board high-voltage start-up and the very low quiescent current, helps keep low the consumption from the mains and be compliant with energy saving regulations. To allow meeting compliance with these standards in power-factor-corrected systems too, an interface with the PFC controller is provided that enables to turn off the pre-regulator when the load level falls below a threshold. The IC includes also a programmable soft-start, slope compensation for stable operation at duty cycles greater then 50%, a disable function, a leading edge blanking on current sense to improve noise immunity, latched disable for OVP or OTP shutdown and an effective two-level OCP able to protect the system even in case the secondary diode fails short. Table 2. Absolute Maximum Ratings
Symbol V cc VHV IH V --IPFC_STOP VPFC_STOP Ptot Tj Tstg 14 14 Pin 5 1 1
1
Parameter IC Supply voltage (Icc = 20 mA) High-voltage start-up generator voltage range High-voltage start-up generator current Analog Inputs & Outputs, except pin 14 Max. sink current (low state) Max. voltage (open state) Power Dissipation @Tamb = 50C Junction Temperature Operating range Storage Temperature
Value Self-limited -0.3 to 700 Self-limited -0.3 to 8 2 16 0 .75 -25 to 150 -55 to 150
Unit V V A V mA V W C C
Note: 1. ESD immunity for pin 1 is guaranteed up to 900V (Human Body Model).
Table 3. Thermal Data
Symbol Rth j-amb Parameter Ther mal Resistance Junction to AmbientMax Value 120 Unit C/W
Figure 3. Pin Connection (Top view)
HV HVS GND OUT Vcc N.C. DIS VREF
RCT S-COMP PFC_STOP STBY ISEN SS COMP SKIPADJ
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L6668
Table 4. Pin Description
Pin Number 1 Pin Name HV Function High-voltage start-up. The pin is to be connected directly to the rectified mains voltage. A 0.8 mA internal current source charges the capacitor connected between pin Vcc and GND to start up the IC. When the voltage on the Vcc pin reaches the start-up threshold the generator is shut down. Normally it is re-enabled when the voltage on the Vcc pin falls below 5V, except under latched shutdown conditions, when it is re-enabled as the Vcc voltage falls 0.5V below the start-up threshold. High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and comply with safety regulations (creepage distance) on the PCB. Chip ground. Current return for both the gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. Gate-drive output. The driver is capable of 0.8A min. source/sink peak current to drive MOSFET's. The voltage delivered to the gate is clamped at about 15V so as to prevent too high values when the IC is supplied with a voltage close to or exceeding 20V. Supply Voltage of both the signal part of the IC and the gate driver. The internal high voltage generator charges an electrolytic capacitor connected between this pin and GND as long as the voltage on the pin is below the start-up threshold of the IC, after that it is disabled. Sometimes a small bypass capacitor (0.1F typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. Connect the pin to GND. Latched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 2.2V, shuts the IC down and brings its consumption to a value barely higher than before start-up. The information is latched and it is necessary to recycle the input power to restart the IC: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Connect the pin to GND if the function is not used. Voltage reference. An internal generator furnishes an accurate voltage reference (5V4%, all inclusive) that can be used to supply up to 5 mA to an external circuit. A small film capacitor (0.1F typ.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. Burst-mode control threshold. A voltage is applied to this pin, derived from the reference voltage VREF via a resistor divider. When the control voltage at pin COMP falls 50 mV below the voltage on this pin the IC is shutdown and the consumption is reduced. The chip is re-enabled as the voltage on pin COMP exceeds the voltage on the pin. The high-voltage star t-up generator is not invoked. The function is disabled during the soft-start ramp. The pin must always be biased between 0.8 and 2.5V. A voltage between 0.8 and 1.4V disables the function, if the pin is pulled below 0.8V the IC is shut down. Control input for PWM regulation. The pin is to be driven by the phototransistor (emittergrounded) of an optocoupler to modulate the voltage by modulating the current sunk from (sourced by) the pin (0.4 mA typ.). It is recommended to place a small filter capacitor between the pin and GND, as close to the IC as possible to reduce switching noise pick up, to set a pole in the output-to-control transfer function. A voltage 50 mV lower than that on pin SKIPADJ shuts down the IC and reduces its current consumption. Soft start. An internal 20A generator charges an external capacitor connected between the pin and GND generating a voltage ramp across it. This ramp clamps the voltage at pin COMP during start-up, thus the duty cycle of the power switch starts from zero. During the ramp all functions monitoring the voltage at pin COMP are disabled. The SS capacitor is quickly discharged as the chip goes into UVLO. Current sense (PWM comparator) input. The voltage on this pin is internally compared with an internal reference derived from the voltage on pin COMP and when they are equal the gate drive output (previously asserted high by the clock signal generated by the oscillator) is driven low to turn off the power MOSFET. The pin is equipped with 200 ns. min. blanking time for improved noise immunity. A second comparison level located at 1.5V shuts the device down and brings its consumption almost to a "before start-up" level.
2 3
HVS G ND
4
O UT
5
Vcc
6 7
N.C. DIS
8
VREF
9
SKIPADJ
10
CO MP
11
SS
12
ISEN
3/23
L6668
Table 4. Pin Description (continued)
P in Number 13 Pin Name STBY Function Standby function. This pin is a high-impedance one as long as the voltage on pin COMP is higher than 3V. When the voltage on pin COMP falls below 3V, the voltage on the pin tracks that on pin COMP and is capable of sinking current. A resistor connected from the pin to the oscillator allows programming frequency foldback at light load. Open-drain ON/OFF control of PFC controller. This pin is intended for driving the base of a PNP transistor in systems comprising a PFC pre-regulator, to stop the PFC controller at light load by cutting its supply. The pin, normally low, opens if the voltage on COMP is lower than 2.2V and goes back low when the voltage on pin COMP exceeds 2.7V. Whenever the IC is shutdown, either latched (DIS >2.2V, ISEN >1.5V) or not (UVLO, SKIPADJ<0.8), the pin is open as well. Voltage ramp for slope compensation. When the gate-drive output is high the pin delivers a voltage tracking the oscillator ramp (shifted down by one VBE); when the gate-drive output is low the voltage delivered is zero. The pin is to be connected to pin ISEN via a resistor to make slope compensation and allow stable operation at duty cycles close to and greater than 50%. Oscillator pin. A resistor to VREF and a capacitor to GND define the oscillator frequency (at full load). A resistor connect to STBY modifies the oscillator frequency when the voltage on pin COMP is lower than 3V.
14
PFC_STOP
15
S-COMP
16
RCT
Table 5. Electrical Characteristcs (Tj = 0 to 105C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified)
Symbol SUPPLY VOLTAGE Vcc VCCOn VCCOff Hys VZ Istart-up Iq ICC Iqdis Operating range Tur n-on threshold Tur n-off threshold Hysteresis Zener Voltage Star t-up Current Quiescent Current Operating Supply Current Shutdown quiescent current VDIS > 2.2, or VISEN > 1.5 VSKIPADJ<0.8 0.8 ( 1)
Parameter
Test Condition After turn-on
(1) ( 1)
Min. 9.4 12.5
Typ.
Max. 22
Unit V V V V
13.5 8 .7
14.5 9.4
After turn-on
8.0 4 .0
Icc = 20 mA Before turn-on, Vcc=VccON-0.5 After turn-on
22
24 150 2 180 1 1.3
28
V A
SUPPLY CURRENT
2.5 4 1 .8
mA mA A mA mA V
IHV < 100 A IVcc < 100 A VHV > VHvstar t, Vcc > 3V VHV > VHvstar t, Vcc > 3V VHV > VHvstar t, Vcc = 0 VHV = 400 V
700 60 0.55 80 0.85 105 1 1.6 0.8 40 4.4 5 13 5.6 14 12
V mA mA A V V
After DIS tripping
4/23
L6668
Table 5. Electrical Characteristcs (continued) (Tj = 0 to 105C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified)
Symbol V REF VREF IREF Parameter Output voltage Total variation Shor t circuit current Sink capability in UVLO PWM CONTROL VCOMPH ICOMP RCOMP Dmax Dmin IISEN tLEB td(H-L) VISENx VISENdis Vdrop Vth Maximum level Max. source current Dynamic resistance Maximum duty cycle Minimum duty cycle Input Bias Current Leading Edge Blanking Delay to Output Gain Maximum signal Hiccup-mode OCP level VCOMP - VSTBY Threshold on VCOMP Hysteresis LATCHED DISABLE FUNCTION IDIS Vth Input Bias Current Disable threshold VDIS = 0 to Vth
( 2) ( 2)
Test Condition
Min. 4.925 4.8 10
Typ. 5
Max. 5.075 5 .13 30
Unit V V mA V V
REFERENCE VOLTAGE Tj = 25 C; IREF = 1 mA
Vcc= 9.4 to 22 V, IREF = 1 to 5 mA VREF = 0 Vcc = 6V; Isink = 0.5 mA ICOMP =0 VCOMP = 1 V VCOMP = 2 to 4 V VCOMP = 5 V VCOMP = 1 V VISEN = 0 After gate drive low-to-high transition
0.2 5.5 320 70 400 22
0 .5
480 75 0 -1
A k % % A ns ns V /V V V mV V mV
CURRENT SENSE COMPARATOR 160 225 290 100 3.56 VCOMP = 5 V
(2)
3.75 0.8 1.5 35 3
3.94 0.875 1.65
0.725 1.35
STANDBY FUNCTION ISTBY = 0.8 mA, VCOMP<3V
( 2)
Voltage falling 50
-1 2.1 2 .2 2.3
A V
voltage rising
OSCILLATOR fsw Vpk Vvy Oscillation Frequency Oscillator peak voltage Oscillator valley voltage Tj = 25C, VCOMP = 5 V Vcc = 9.4 to 22V, VCOMP = 5 V
(2) (2)
95 93 2.85 0.8 1.6 0.15
100 100 3 0 .95 1 .75 0.35 0
105 107 3.15 1 .1 1 .9 0.55
kHz kHz V V V V
SLOPE COMPENSATION S-COMPpk Ramp peak S-COMPvy Ramp starting value Ramp voltage Source capability SOFT-START ISSC Charge current Tj = 25 C 14 20 26 A RS-COMP = 3 k to GND, OUT pin high, VCOMP = 5V RS-COMP = 3 k to GND, OUT pin high OUT pin low VS-COMP = VS-COMPpk 0.8
mA
5/23
L6668
Table 5. Electrical Characteristcs (continued) (Tj = 0 to 105C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified)
Symbol VSSsat VSSclamp Ib i a s VSKIP Hys VOFF Ileak VL Vth Vth Parameter Low saturation voltage High saturation voltage Input Bias Current Operating range Hysteresis Shutdown threshold High level leakage current Low saturation level Threshold for high level Threshold for high level Below VSKIP Voltage falling VPFC_STOP < 16V, VCOMP = 2V IPFC_STOP = 1mA, VCOMP = 4V VCOMP falling
(2)
Test Condition Duty cycle = 0
Min.
Typ. 7
Max. 0 .6
Unit V V
SKIPADJ FUNCTION VSKIP = 0 to 4.5 V 1.4 25 -1 2.5 85 0.8 1 0.1 2.1 2.55 2 .2 2.7 2.3 2.85 A V mV V A V V V
PFC_STOP FUNCTION
VCOMP rising (2) Isink = 200 mA Isource = 5 mA, Vcc = 12V
GATE DRIVER VOL VOH Isourcepk Isinkpk tf tr VOclamp
(1), (2)
Output Low Voltage Output High voltage Peak source current Peak sink current Current Fall Time Current Rise Time Output clamp voltage UVLO saturation
1.0 9.8 - 0.8 0.8 30 55 10.3
V V A A ns ns
Isource = 5mA; Vcc = 20V Vcc= 0 to Vccon, Isink= 2mA
10
12
15 1 .1
V V
Parameters in tracking each other
Figure 4. Typical System Block Diagram
PFC PRE-REGULATOR DC-DC CONVERTER
Vinac
Voutdc
PWM is turned off in case of PFC's anomalous operation, for safety
L6561/2 or L6563
L6668
PFC can be turned off at light load to ease compliance with energy saving regulations.
6/23
L6668
3
Typical Electrical Performance
Figure 8. High-voltage generator start voltage vs. Tj
HV
Figure 5. High-voltage generator ON-state sink current vs. Tj
IHV (pin 1)
1 .2
120%
Vcc 3V
[mA]
1
110%
VHV = 100 V
0 .8
100%
0 .6
90%
0 .4 Vcc = 0
H Values normalized to V V @ 25C
0 .2 -50
0
50
100
150
80% -50
0
50
100
150
Tj (C)
Tj (C)
Figure 6. High-voltage generator output (Vcc charge current) vs. Tj
Icc (pin 5)
120% VHV = 100 V 110%
Figure 9. High-voltage generator Vcc restart voltage vs. Tj
Vcc (pin 5)
14
[V]
12
while latched off
10
VHV = 100 V
100%
8
90% Values normalized to Icc @ 25C 80% -50
6
normal operation
0
50
100
150
4 -50
0
50
100
150
Tj (C)
Tj (C)
Figure 7. High-voltage pin leakage vs. Tj
IHV (pin 1)
40
Figure 10. IC consumption vs. Tj
Icc (pin 5)
5
[A]
VHV = 400 V Vcc = 15V 30
[mA]
3 2
O perating Quiescent
1
20
0.5 0.3 0.2
Vcc = 15 V Co = 1 nF f = 100 kHz
Disabled or during burst-mode
10
Latch ed off Befo re start-up (Vcc=12V)
0 -50
0
50
100
150
0.1 -50
0
50
100
150
Tj (C)
Tj (C)
7/23
L6668
Figure 11. Start-up & UVLO vs. Tj
VCC (pin 5) (V) 14 ON
Figure 14. COMP source current vs. Tj
ICOMP (pin 10) 140%
Vcc = 15 V = VCOMP 1 V
13 12 11 10
80%
OFF while latched off
120%
100%
9 8 -50
OFF
Values normalized to COMP @ 25C I
0
50
Tj (C)
100
150
60% -50
0
50 Tj (C)
100
150
Figure 12. Vcc Zener voltage vs. Tj
VccZ (pin 5) (V) 26
Figure 15. COMP dynamic resistance vs. Tj
RCOMP (k)
(pin 10)
32 30 28 26
25 24 23
24
22 21 20 -50 0 50
Tj (C)
22
Vcc = 15 V
20
100
150
18 -50
0
50
Tj (C)
100
150
Figure 13. COMP voltage upper clamp level vs. Tj
VCOMP (pin 10) 7 (V)
Vcc = 15 V
Figure 16. Max. duty-cycle vs. Tj
(%)
75
Vcc = 15 V
74
6.5
73
6
72
5.5
71 70 -50
5 -50
0
50 Tj (C)
100
150
0
50
Tj (C)
100
150
8/23
L6668
Figure 17. Oscillator frequency vs. Tj
f sw
Figure 20. Disable level on current sense vs. Tj
Vpin12 (V) 2.0
102% 101.5% 101% 100.5% 100% 99.5%
Values normalized to sw @ Tj=25C, Vcc=15V f RT = 13.3 k CT = 1 nF Vcc = 22V
Vcc = 15 V
1.8
Vcc = 15V
1.6 1.4 1.2 1.0 -50
Vcc = 9.4V
99% -5 0
0
50
Tj (C)
100
150
0
50
Tj (C)
100
150
Figure 18. Oscillator ramp vs. Tj
Vpin14 ( V)
Figure 21. Reference voltage vs. Tj
VREF (pin 8) (V) 5.1
3.5
Peak
3.0
5.05
Vcc = 15 V
2.5 2.0 1.5
Valley
Vcc = 15 V
5
4.95
1.0 0.5 -50 0 50
Tj (C)
100
150
4.9 -50
0
50
Tj ( C)
100
150
Figure 19. Current sense clamp vs. Tj
V ISENx (V) 1
(pin 12)
Figure 22. PFC_STOP open/low thresholds on VCOMP vs. Tj
VCOMP (pin 10) (V) 2.8 PFC_STOP low (voltage rising)
0.9
Vcc = 15 V VCOMP= Upper clamp
2.7 2.6 2.5
Vcc = 15 V
0.8
2.4 2.3
PFC_STOP open (voltage falling)
0.7
2.2
0.6 -50
0
50
Tj (C)
100
150
2.1 -50
0
50
Tj ( C)
100
150
9/23
L6668
Figure 23. Standby thresholds vs. Tj
VCOMP (pin 10) 3.6 (V)
Vcc = 15 V
Figure 26. SKIPADJ hysteresis vs. Tj
V p in 9 1 00 . 0 (m V ) 8 0 .0
V c c = 15 V
3.4 3.2 3
Enable (voltage falling) Disable (voltage rising)
6 0 .0
Vskipadj = 2.5 V
4 0 .0
V s k ip a dj = 1.4 V
2.8
2 0 .0
2.6 2.4 -50
0 .0 -5 0 0 50 T j (C ) 100 1 50
0
50 Tj (C)
100
150
Figure 24. Standby pin dropout vs. Tj
Vpin13 - Vpin 10
Figure 27. SKIPADJ disable threshold vs. Tj
(V) Vpin9 1.0
Vcc = 15 V
0
(mV)
-5 -10
Vcc = 15 V VCOMP 2V = ISTBY = 0.8 mA
0.9
0.8
-15
0.7
-20 -25 -30 -5 0 0 50
Tj (C)
0.6 0.5 -50
100
150
0
50
Tj ( C)
100
150
Figure 25. DIS threshold vs. Tj
V pin 7 2.5 (V)
Vcc = 15 V
Figure 28. Soft-start charge current vs. Tj
Iss ( pin11) 40.0
(A) Vcc = 15 V
2.4
30.0
2.3
20.0
2.2
2.1
10.0
2.0 -50
0
50 Tj (C)
100
150
0.0 -50
0
50
Tj ( C)
100
150
10/23
L6668
Figure 29. S-COMP ramp vs. Tj
Vpin15 (V)
Figure 32. Gate-drive output low saturation
Vpin4 [V]
5
2.0
Peak
1.5
Vcc = 15 V RS-SCOMP = 3 k
4 3
Tj = 25 C Vcc = 12 V SINK
1.0
2
0.5
Valley
1 0
0.0 -50
0
200
400
600
800
1,000 1,200
0
50
Tj (C)
100
150
IGD [mA]
Figure 30. UVLO saturation vs. Tj
Vpin4 (V)
Figure 33. Gate-drive output high saturation
Vpin4 [V]
1
Vcc = 0 V
0.9 0.8
Vcc - 2.0 Vcc - 3.0 Vcc - 4.0
Tj = 25 C Vcc = 12 V SOURC E
0.7 0.6 0.5 -50
Vcc - 5.0 Vcc - 6.0
0
200
400
600
800
1,000
0
50
Tj (C)
100
150
IGD [mA]
Figure 31. Gate-drive clamp vs. Tj
Vpin4 clamp (V)
13
Vcc = 20 V
12.8 12.6 12.4 12.2 12 -50
0
50
Tj (C)
100
150
11/23
L6668
4
Application Information
The L6668 is a versatile current-mode PWM controller specific for offline fixed-frequency, peak-currentmode-controlled flyback converters. The device is able to operate in different modes (fig. 34), depending on the converter's load conditions: 1) Fixed frequency at heavy load. In this region the IC operates exactly like a standard current mode control chip: a relaxation oscillator, externally programmable with a capacitor and a resistor, generates a sawtooth and releases a clock pulse during the falling edge of the sawtooth; the power switch is turned on by the clock pulses and is turned off by the control loop. 2) Frequency-foldback mode at medium and light load. As the load is reduced the oscillator frequency is reduced as well by slowing down the charge of the timing capacitor proportionally to the load itself. 3) Burst-mode control with no or very light load. When the load is extremely light or disconnected, the converter will enter a controlled on/off operation with constant peak current. A load decrease will be then translated into a frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequencyrelated losses and making it easier to comply with energy saving regulations. Being the peak current very low, no issue of audible noise arises.
Figure 34. Multi-mode operation of the L6668
Burst mode
Frequency foldback mode
Fixed-frequency mode
fs w
0
0
Pi n
Pinmax
4.1 High-voltage start-up generator Figure 35 shows the internal schematic of the high-voltage start-up generator (HV generator). It is made up of a high-voltage N-channel FET, whose gate is biased by a 15 M resistor, with a temperature-compensated current generator connected to its source. Figure 35. High-voltage start-up generator: internal schematic
HV
L6668
15 M
1
Vcc_OK HV_E N IHV
5 CONTROL I charge 3 GND
Vcc
The HV generator is physically located on a separate chip, made with BCD off-line technology able to withstand 700V, controlled by a low-voltage chip, where all of the control functions reside.
12/23
L6668
With reference to the timing diagram of figure 36, when power is first applied to the converter the voltage on the bulk capacitor (Vin) builds up and, as it reaches about 80V, the HV generator is enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, diminished by the IC consumption, charges the bypass capacitor connected between pin Vcc (5) and ground and makes its voltage rise almost linearly.
Figure 36. Timing diagram: normal power-up and power-down sequences
Vin V HVstart Vcc Vcc ON Vcc OFF Vcc restart t
regulation is lost here
t
OUT
HV_E N
t
Vcc_OK
t
IHV 1 mA
t
Power-u p
Normal ope ration
Power-down
t
As the Vcc voltage reaches the start-up threshold (13.5V typ.) the low-voltage chip starts operating and the HV generator is cut off by the Vcc_OK signal asserted high. The IC is powered by the energy stored in the Vcc capacitor until the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. The residual consumption of this circuit is just the one on the 15M resistor (10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared to a standard start-up circuit made with an external dropping resistor.
Figure 37. Timing diagram showing short-circuit behavior
V cc
Vcc O N Vcc OFF Vcc res t
Short circuit occurs here
OUT
t
Vcc_OK
t
IHV
1 mA
t
t
13/23
L6668
At converter power-down the system will lose regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. Vcc will then drop and stop IC activity as it falls below the UVLO threshold (8.7V typ.). The Vcc_OK signal is de-asserted as the Vcc voltage goes below a threshold Vccrestart located at about 5V. The HV generator can now restart but, if Vin < Vinstart, as shown in figure 36, HV_EN is de-asserted too and the HV generator is disabled. This prevents converter's re-start attempts and ensures monotonic output voltage decay at power-down. The low restart threshold Vccrestart ensures that, during short circuits, the restart attempts of the L6668 will have a very low repetition rate, as shown in the timing diagram of figure 37, and that the converter will work safely with extremely low power throughput.
4.2 Frequency Foldback Block and operation at medium/light load At heavy load, namely as the voltage on pin COMP (VCOMP) is higher than 3V, the device works at a fixed frequency like a standard current mode PWM controller.
As the load is reduced, and the VCOMP voltage falls below 3V (approximately corresponding to 50% of the maximum load in a fully DCM system), the oscillator frequency can be made dependent on converter's load conditions - the lower the load, the lower the frequency and vice versa.
Figure 38. Frequency foldback function: oscillator frequency is a function of COMP voltage
L6668
COMP
+ 3.0V
OSCILLATOR
fosc 13 STBY 8 Vref RT 16 RCT CT
1.4 3.0 4.4
RSTBY
RSTBY
VCOMP
This is done by adding an external resistor RSTBY between pins RCT (#16) and STBY (#13), which activates the circuit shown in figure 38. When VCOMP is below 3 V (oscillator's peak voltage) the voltage on the STBY pin, which is internally connected to a current sink, tracks VCOMP and then some of the current that charges CT is diverted to ground through the STBY pin. In this way the rate of rise of the voltage across CT is slowed down and the oscillator frequency decreased, the lower VCOMP the lower the frequency. Instead, when VCOMP is greater than 3 V the STBY pin features high impedance and the oscillator frequency fosc will be determined by RT and CT. These components can be then calculated as it is usually done with this type of oscillator:
1.4 RT C T = --------fos c
14/23
L6668
Figure 39. Standby function: frequency shift vs. timing resistors (normalized quantities)
1 0.9 0.8 0.7
f min f osc
0.6 0.5 V(SKIPADJ) = 1.6V 0.4 0.3 0.2 0. 2.5V 2.2V 2V V(SKIPADJ) = 1.5V 1.8V 1 V(SKIPADJ) = 1.4V 10
R STBY RT
The determination of RSTBY can be done assuming that the minimum switching frequency before burstmode operation takes place (fmin) is specified. This value will be above the audible range to ensure a noise-free operation. With the aid of the diagrams in figure 39, which show the relationship between the frequency shift obtained and the ratio of RSTBY to RT for different values of the burst-mode threshold, it is possible to determine RSTBY. Draw an horizontal line corresponding to the desired fmin/fosc ratio as long as it intercepts the characteristic corresponding to the voltage set at the pin SKIPADJ (#9). From there, draw a vertical line: on the horizontal axis it is possible to read the required RSTBY/RT ratio. Note that the characteristic for V(SKIPADJ)=1.4V corresponds to the burst-mode operation not used (see next section). Note also that, for a given V(SKIPADJ), there is both a lower limit to the RSTBY/RT ratio and a maximum frequency shift allowed. Not observing these limits will result in erratic behavior. In applications where the switching frequency needs not be tightly fixed for some specific reason there is no major drawback to this technique. In case this function is not desired, the STBY pin shall be left open.
4.3 Operation at no load or very light load When the PWM control voltage at pin COMP falls about 50 mV below a threshold externally programmable via pin 9 (SKIPADJ), the IC is disabled with the MOSFET kept in OFF state and its consumption reduced at a very low value to minimize Vcc capacitor discharge. The soft-start capacitor is not discharged.
The control voltage now will increase as a result of the feedback reaction to the energy delivery stop, the threshold will be exceeded and the IC will restart switching again. In this way the converter will work in burst-mode with a constant peak current defined by the disable level applied at pin 9. A load decrease will then cause a frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and maximizing efficiency. This kind of operation is noise-free provided the peak current, which is user-defined by the bias voltage at pin 9, is very low. The timing diagram of figure 40 illustrates this kind of operation along with the other ones, showing the most significant signals.
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Figure 40. Load-dependent operating modes: timing diagram
C OM P
3. 0V 50 mV hys t er .
V( SKI PADJ )
fosc
t
t O UT
Fix. Freq. Mode
Burst-mode Frequency Foldback Mode
Fix. Freq. Mode
t
The operating range of the voltage V(SKIPADJ) is practically limited upwards by the onset of audible noise: typically, with a voltage above 2-2.1V some noise can be heard under some line/load conditions. If, instead, V(SKIPADJ) is set below the low saturation value of the PWM control voltage (1.4V typ.) burstmode operation will never take place. Always bias the pin at some voltage, a floating pin will result in anomalous behavior. The SKIPADJ pin doubles its function: if the voltage is pulled below 0.8V the IC is disabled completely, except for the externally available reference voltage VREF, and its quiescent consumption reduced. The soft-start capacitor is discharged so that, when the voltage on the SKIPADJ pin is pulled above 0.8V, the chip is soft-started just like exiting from UVLO. This function is useful for some kind of remote ON/OFF control. The comparator referenced to 0.8V does not have hysteresis; hence make sure that the voltage on the pin does not linger on the threshold to prevent uncertain behavior.
4.4 PWM control Block The device is specific for secondary feedback. Typically, there is a TL431 at the secondary side and an optocoupler that transfers output voltage information to the PWM control at the primary side, crossing the isolation barrier. The PWM control input (pin #10, COMP) is driven directly by the phototransistor's collector (the emitter is grounded to GND) to modulate the duty cycle. 4.5 Current Comparator, PWM Latch and Hiccup-mode OCP The current comparator senses the voltage across the current sense resistor (Rs) on pin 12 (ISEN) and, by comparing it with the programming signal derived form the control voltage on pin 10 (COMP), determines the exact time when the external MOSFET is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the noise generated ("double-pulse suppression").
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Figure 41. Hiccup-mode OCP: timing diagram
Vcc Vcc ON Vcc OFF re
Secondary diode is shorted here
V CS
1 .5 V
t
OUT
t
OCP latch
t
Vcc_OK
t
t
A second comparator senses the voltage on the current sense input and shuts the IC down if the voltage at the pin exceeds 1.5 V. Such an anomalous condition is typically generated by either a short circuit of the secondary rectifier or a shorted secondary winding or a saturated flyback transformer. This condition is latched as long as the IC is supplied. When the IC is disabled, however, no energy is coming from the self-supply circuit, then the voltage on the Vcc capacitor will decay and cross the UVLO threshold after some time, which clears the latch. The internal start-up generator is still off, then the Vcc voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the IC restarted. Ultimately, either of the above mentioned failures will result in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. The timing diagram of figure 41 illustrates this operation.
4.6 Power Management The L6668 is specifically designed to minimize converter's losses under light or no-load conditions, and a special function has been provided to help the designer meet energy saving requirements even in powerfactor-corrected systems where a PFC pre-regulator precedes the DC-DC converter.
Actually EMC regulations require compliance with low-frequency harmonic emission limits at nominal load, no limit is envisaged when the converter operates with a light load. Then the PFC pre-regulator can be turned off, thus saving the no-load consumption of this stage (0.5 to 1W). To do so, the device provides the PFC_STOP (#14) pin: it is an open collector output, normally low, that becomes open when the voltage VCOMP falls below 2.2V. This signal will be externally used for switching off the PFC controller and the pre-regulator as shown in figure 42. To prevent intermittent operation of the PFC stage, 0.5V hysteresis is provided: the PFC_STOP pin is re-asserted low (which will re-enable the PFC pre-regulator) when VCOMP exceeds 2.7 V. A capacitor (and a limiting resistor in the hundred ohms), shown in dotted lines, may be used if one wants to delay PFC turn-off When the L6668 is in UVLO (Vcc<8.7V) the pin is kept high so as to ensure that the PFC pre-regulator will start up only after the DC-DC converter governed by the L6668 is activated.
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Figure 43 shows a timing diagram where the PFC_STOP function operation is illustrated under different operating conditions.
Figure 42. How the L6668 can switch off a PFC controller at light load
BC557 Vcc 16 10 k Vcc 8.2 V 2.2 k
L6668
14
PFC_STOP
PFC controller
Figure 43. Operation of PFC_STOP function
V cc
Vc c O N Vc c O F F
P F C_ S TOP
t
C OM P
2. 2V 2. 7V
t
OU T
t
P FC Gate D riv e
Start-up Full-load Light-load Full-load
t
t
Figure 44. Operation after DIS pin activation: timing diagram
DIS
2 .2 V
Vcc Vcc
VccON Vcc ON -0.5 Vcc OFF Vcc rest
HV generator is turned on Disable latch is reset here
t
OUT
HV generator is disabled here
t
Input source is removed here
Vin
VHVstart
t
t
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4.7 Disable function Latched OTP or OVP functions can be easily realized with the L6668: the IC is equipped with a comparator whose non-inverting input is externally available on pin #7 (DIS), and whose inverting input is internally referenced to 2.2V.
As the voltage on the pin exceeds the threshold the IC is immediately shut down and its consumption reduced at a low value. The information is latched and it is necessary to let the voltage on the Vcc pin go below the UVLO threshold to reset the latch and restart the IC. To keep the latch supplied as long as the converter is connected to the input source, the HV generator is activated periodically so that Vcc oscillates between the start-up threshold VccON and VccON - 0.5V. It is then necessary to disconnect the converter from the input source to restart the IC. This operation is shown in the timing diagram of figure 44. Activating the HV generator in this way cuts its power dissipation approximately by three and keeps peak silicon temperature close to the average value.
4.8 Slope compensation A pin of the device (#15, S-COMP) provides a voltage ramp during MOSFET's ON-time which is a repetition of the oscillator sawtooth, buffered (0.8 mA min. capability) and level shifted down by one Vbe.
This ramp is intended for implementing additive slope compensation on current sense. This is needed to avoid the sub-harmonic oscillation that arises in all peak-current-mode-controlled converters working in continuous conduction mode with a duty cycle close to or exceeding 50%.
Figure 45. Slope compensation waveforms
RCT
OUT
t
S-COMP
t
t
The compensation will be realized by connecting a programming resistor between this pin and the current sense input (pin 12, ISEN). The pin has to be connected to the sense resistor with another resistor to make a summing node on the pin. Since no ramp is delivered during MOSFET OFF-time (see figure 45), no external component other than the programming resistor is needed to ensure a clean operation at light loads. If slope compensation is not required the pin shall be left floating.
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Figure 46. Typical Application: 80W, WRM flyback; Electrical Schematic
F1 T2A250V J1
NTC1 BD1 DF04M
T1: CORE E32/16/9, N67 PRIM. IND. 430H; lgap = 1mm T1 R1 3 M R2 3 M D1 1.5KE200 D2 STTH1L06 C12 2.2 nF Y1 GND D4 STPS20150CT C8A,B,C 680 F 25 V C9 100 nF J2 18V/4.5A
88 to 264 Vac
C1 100 F 400 V
N1 56T
N2 10T
C3 100 nF R5 47k R4 330 k C2 25 V 47 F R6 9.1 k VREF S-COMP ST BY R8 4.03 k 16 R9 6.2 k RC T 6 N.C. R10 82.5 k C4 100 nF C5 3.3 nF SKIPADJ C6 56 nF R11 47 k C7 2.2 nF 9 11 SS 10 COMP 3 GND OC 1 PC817A 8 13 L6668 12 I SEN 15 7 DIS 5 VCC 1 HV 4 R12 1k R13A,B 0.56 1/2W OUT R710 N3 8T R3 10 D3 1N4148
Q1 R14 STP9N K65 4.3 k R17 8.06 k OC1 PC817A
R15 1.2 k
TL431 1 3 2
C10 100 nF R16 47 k
R18 1.3 k
Table 6. Light load measurements on the circuit of figure 46
Output power Test condition Input power
Pout = 0.5 W
Vin= 110 Vac Vin= 230 Vac
0.71 W 0.86 W 0.09 W 0.17 W
Pout = 0 W
Vin= 110 Vac Vin= 230 Vac
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5
Package information
In order to meet environmental requirements, STMicroelectronics offers this device in ECOPACK package. This package has a Lead-free second level interconnect. The category of second level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com.
Figure 47. SO16 (Narrow) Mechanical Data & Package Dimensions
mm DIM. MIN. A a1 a2 b b1 C c1 D(1) E e e3 F(1) G L M S 3.8 4.60 0.4 9.8 5.8 1.27 8.89 4.0 5.30 1.27 0.62 8 (max.) 0.150 0.181 0.150 0.35 0.19 0.5 45 10 6.2 (typ.) 0.386 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.394 0.244 0.1 TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 MIN. TYP. MAX. 0.069 0.009 0.063 0.018 0.010 inch
OUTLINE AND MECHANICAL DATA
SO16 (Narrow)
(1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.)
0016020 D
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6
Revision History
Table 7. Revision History
Dat e Revision Description of Changes
20-May-2005 15-July-2005 28-July-2005 13-Jan-2006
1 2 3 4
First Issue. Modify values in Electrical Characteristics Changed the maturity from "Preliminary Data" to "Datasheet". Absolute Maximum Rating Update (added ESD note for pin 1). Modified value "DIS >2.2V" in the table 4 pin 14.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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