w
IMPORTANT NOTICE
Dear customer, As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document.
Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of the last page " STMicroelectronics 200x - All rights reserved", shall now read: " ST-NXP Wireless 200x - All rights reserved". Web site - http://www.st.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices is found at http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless
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STw4810
Power management for multimedia processors
Features
2 Step-down converters 1 to 1.5V with 15 steps at 600mA 1.8V at 600mA for general purpose usage 3 Low-drop output regulators for different uses PLL analog supplies: 1.05V, 1.2V, 1.3V 1.8V - 10mA Processor analogue functions: 2.5V - 10mA Auxiliary device: 1.5V, 1.8V, 2.5V, 2.8V - 150 mA USB OTG module Full and low speed USB OTG transceiver Charge-pump (5V, 100mA) for USB cable Mass memory cards (SD/MMC/SDIO) 1 linear regulator: 1.8V, 2.85V, 3V - 150mA Level shifter Miscellaneous 32 kHz control for multimedia processor Processor supply monitoring Processor reset control 2 Serial I2C interfaces
STw4810CHD TFBGA 84 6x6x1.2mm 0.5mm pitch STw4810CRA VFBGA 84 4.6x4.6x1.0mm 0.4mm pitch
Description
STw4810 is a power management companion chip for multimedia processors used in portable applications. It supplies the multimedia processor including its memories and peripherals. STw4810 supports the main mass memory standard cards. SDIOTM is also supported and allows to connect multimedia peripherals like cameras.
Appl ication
ST NOMADIKTM STn88xx Multimedia processor Mobile phones, PDA, videophone
September 2007
Rev 9
1/78
www.st.com
1
Contents
STw4810
Contents
1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ball information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3. 2 Ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Digital control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 POWER OFF / VDDOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IT generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Clock switching and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3
Power management module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 Bandgap, biasing and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VCORE regulator: DC/DC step-down regulator . . . . . . . . . . . . . . . . . . . 35 VIO_VMEM regulator: DC/DC step- down regulator . . . . . . . . . . . . . . . 35 VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4
USB OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.4.1 4.4.2 4.4.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Modes and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USB enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5
SD/MMC/SDIO module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2/78
STw4810
Contents
5
Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5. 1 5. 2 5.3 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VCORE DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 51 VIO_VMEM DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . 52 LDO regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5. 4
Digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 CMOS input/output static characteristics: I2C interface . . . . . . . . . . . . . 57 CMOS input/output dynamic characteristics: I2C interface . . . . . . . . . . 58 CMOS input/output static characteristics: VIO level . . . . . . . . . . . . . . . 59 CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . 61 CMOS input/output static characteristics: VMMC level . . . . . . . . . . . . . 62
5.5 5. 6
USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SD/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1 6. 2 Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7. 1 7. 2 TFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 VFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8 9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3/78
List of tables
STw4810
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. STw4810 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STw4810 balls function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register general information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 USB register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Vendor ID and Product ID: Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 USB control register 1 (address = 04h set and 05h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 23 USB control register 2 (Address = 06h set and 07h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 24 USB Interrupt source register (address = 08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 USB interrupt latch registers (address = 0Ah set and 0Bh clearh) . . . . . . . . . . . . . . . . . . . 25 USB interrupt mask false register (address = 0Ch and 0Dh) . . . . . . . . . . . . . . . . . . . . . . . 26 USB interrupt mask true register (address = 0Eh and 0Fh) . . . . . . . . . . . . . . . . . . . . . . . . 26 USB EN register (address = 10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SD MMC control register (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power control register - General information (Address = 1Eh) . . . . . . . . . . . . . . . . . . . . . . 28 Power control register - General information (Address = 1Fh) . . . . . . . . . . . . . . . . . . . . . . 28 Power control register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power control register at address 05h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power control register at address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power control register at address 07h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power control register at address 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power control register at address 09h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power control register at address 0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Twarning register (Address = 20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0 . . . . . . . . 42 Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1 . . . . . . . . 42 Data receiver via USB control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STw4810 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Operating conditions (Temp range: -30 to +85 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VCORE DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 VIO_VMEM DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LDO regulators - VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LDO regulators - VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LDO regulators - VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CMOS input/output static characteristics: I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CMOS input/output dynamic characteristics: I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . 58 VIO level: USB and control I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 VIO level: MMC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4/78
STw4810 Table 49. Table 50. Table 51. Table 52. Table 53. Table 55. Table 56. Table 57. Table 58.
List of tables CMOS input/output static characteristics VMMC level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SD/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Recommended coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions . . . . . . . . . . . . . . . . . . 72 VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch . . . . . . . . . . . . . . . . . . . . 74 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5/78
List of figures
STw4810
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Typical mobile multimedia system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STw4810 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Switching POWER to sleep timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VDDOK block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control interface: I2C format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control interface: I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock switching between master and internal clock (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Block diagram of biasing and references of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Thermal threshold temperatures for `it_warn' bit and VDDOK ball . . . . . . . . . . . . . . . . . . . 38 USB OTG transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SD MMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Propagation and clock/data skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 STw4810 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing . . . . . . . . . . . . . . . . . . . . . 73 VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6/78
STw4810
Overview
1
Overview
The STw4810 power management device has the following features:
Power management module 1 Step-down converter for processor core (1 to 1.5 V with 15 steps at 600 mA) 1 Step-down converter (1.8 V at 600 mA) for general purpose usage such as processor input/output supply, external memory, DDR and SDRAM and peripherals 1 Low-drop output regulator for analog supplies, such as PLL (1.05 V, 1.2 V, 1.3 V, 1.8 V at 10 mA) 1 Low-drop output regulator for processor analogue functions (2.5 V at 10 mA) 1 Low-drop output regulator for auxiliary devices (1.5 V, 1.8 V, 2.5 V, 2.8 V at 150 mA) Full and low speed USB OTG transceiver 1 Linear regulators (3.1 V at 40 mA) supplying transceiver 1 Charge-pump (5 V at 100 mA) supplying VBUS line of the USB cable 1 Linear regulator (1.8 V, 2.85 V, 3 V at 150 mA) Level shifter 32 kHz control for multimedia processor Processor supply monitoring Processor reset control 2 Serial I2C interfaces Typical mobile multimedia system
USB OTG module
Mass memory cards (SD/MMC/SDIO)
Miscellaneous
Figure 1.
7/78
Functional block diagram
STw4810
2
Figure 2.
Functional block diagram
STw4810 block diagram
VMINUS_VIO_VMEM VBAT_VIO_VMEM VMINUS_VCORE 1V=>1.5V- 600mA VLX_VIO_VMEM
VBAT_VCORE
VLX_VCORE
VIO_VMEM
VBAT_DIG VMINUS_DIG Internal oscillator 1.8V- 600mA
MASTER_CLK CLK32K_IN CLK32K GPO1 GPO2 USBINTn
clock switching and control SOFT_STAEF_VIO_VMEM RT VR
VREF_VCORE VREF_VPLL VREF_VAUX
VCORE
VBAT_ANA VMINUS_ANA BG
BIAS
Buffer
VREF_18
Control registers Thermal shutdown Monitoring VPLL_LDO 1.05V,1.2V,1.3V,1.8V, 10mA VANA_LDO 2.5V, 10mA PORn_VBAT
VBAT_VPLL_ANA
TCXO_EN REQUEST_MC PON VDDOK PORn PWREN SW_RESETn SDA SCL
VPLL
General control
VANA VBAT_VAUX VAUX_LDO 1.5V,1.8V2.5V,2.8V, 150mA
I2C interface I2C Mux
VAUX VBAT_USB
USB OTG transceiver interface USBSDA USBSCL IT_WAKE_UP SD/MMC/ SDIO control USBOEn USBVP USBVM USBRCV VMINUS_USB MCCMDDIR MCDAT0DIR MCDAT2DIR MCDAT31DIR MCCLK MCFBCLK MCCMD MCDATA0 MCDATA[3:1] Driver Level shifter Pull up & down VUSB ID DP DN VBAT_MMC SD/ MMC/SDIO interface USB control Charge pump 5V - 100mA CP CN VBUS
Control
3.1V - 40mA
Level shifter
1.8/2.85/3V-150mA
VMMC LATCHCLK CLKOUT CMDOUT DATAOUT0 DATAOUT[3:1]
Driver
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STw4810
Ball information
3
3.1
Table 1.
1 A B C D E F G H J K
Ball information
Ball connections
STw4810 ball connections
2
VMINUS_ VIO_VMEM
3
VLX_VIO_ VMEM
4
5
6
VAUX
7
VANA
8
VPLL
9
VREF_18
10
VCORE
CLK32K_IN
VBAT_VIO_ VIO_VMEM VMEM VMINUS_ ANA "Reserved"
"Reserved" TCXO_EN VBAT_DIG DATAOUT0 DATAOUT <3> CLKOUT MCCMD MCDATA <2> MCDATA0
REQUEST_ VMINUS_ VBAT_VIO_ MC VIO_VMEM VMEM IT_WAKE_ UP MASTER_ CL K DATAOUT <1> CM DOUT MCCLK MCDATA <3> VDDO K MCDAT0 DIR VMINUS_ DI G "reserved" DATAOUT <2> LATCHCLK MCCMD DIR MCDATA <1> PORN CLK32K MCDATA31 DIR VBAT_ MMC SW_ RESET VLX_VIO_ VMEM
VBAT_ VAUX VBAT_ANA
"Reserved" VBAT_ VPLL_ANA
"Reserved" PON VLX_ V C O RE ID "Reserved" "Reserved"
"Reserved" VMINUS_ VCORE VBAT_ VCORE DP VBAT_USB USBSCL USBSDA VMINUS_ USB MCDAT2 DIR
VMINUS_ VCORE VLX_ VCORE VBAT_ VCORE DN VUSB VBUS CP CN "Reserved"
MCFBCLK GPO1 VMMC
PWREN SCL GPO2
SDA USBVP USBRCV
USBINTn USBVM USBOEn
3.2
Ball functions
STw4810 includes the following ball types
VDDD/VDDA: digital/analog power supply VSSD/VSSA: digital/analog ground supply DO/DI/DIO: Digital Output / Digital Input / Digital Input Output DOz: Digital Output with high impedance capability AO/AI/AIO: Analog Output / Analog Input / Analog Input-Output G: to be connected to ground O: to be left open Int-Ref: Associated to internal reference
Table 2 details the ballout.
9/78
Ball information Table 2.
Ball General supplies D1 C3 C6 B5 F9 J9 A9 VBAT_DIG VMINUS_DIG VBAT_ANA VMINUS_ANA VBAT_USB VMINUS_USB VREF_18 VDDD-VBAT VSSD VDDA-VBAT VSSA VDDA-VBAT VSSA Int-Ref Batter y supply for digital/oscillator Ground for digital and oscillator Batter y supply for analog Ground for analog Batter y supply for USB block Ground for USB block Internal reference
STw4810
STw4810 balls function
Ball name Ball type Description
Control balls C8 K4 J2 J3 H6 C1 B2 J6 H7 D2 A1 K3 PON SW_RESETn VDDOK PORn PWREN TCXO_EN REQUEST_MC SCL SDA MASTER_CLK CLK32K_IN CLK32K DI(VBAT) Pull Down 1.5M DI(VIO_VMEM) Pull Up 1.5M DO(VIO_VMEM) DO(VIO_VMEM) DI(VIO_VMEM) Pull Up 1.5M DI(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) DI(VIO_VMEM) DIO(VIO_VMEM) AI Pull Down 1.5M DI(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) Power-on and reset Software reset, reset all applications when SW_RESETn = 0 Supply monitoring for multimedia processors. Interruption for high temperature warning Multimedia processor Resetn Sleep mode from multimedia processor Request of master clock from modem part Request to master clock oscillator Clock for Main I2C interface SDA for Main I2C interface 26 MHz, 13 MHz or 19.2 MHz from modem 32 kHz input 32 kHz to multimedia processor
10/78
STw4810 Table 2.
Ball Regulator balls A4 B4 A2 B3 A3 C4 A5 D9 D10 B10 C9 C10 D8 A10 C7 A7 A8 A6 B6 USB balls C2 K8 IT_WAKE_UP USBOEn DO(VBAT-DIG) DIO(VIO_VMEM) Pull Down 1.5M DIO(VIO_VMEM) Pull Down 1.5M DIO(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) AIO(VUSB) AIO(VUSB) AI(VBAT-USB) AIO(VBUS) VBAT_VIO_VMEM VMINUS_VIO_VMEM VLX_VIO_VMEM VIO_VMEM VBAT_VCORE VMINUS_VCORE VLX_VCORE VCORE VBAT_VPLL_ANA VANA VPLL VAUX VBAT_VAUX VDDA-VBAT VSSA AIO AI VDDA-VBAT VSSA AIO AI VDDA-VBAT AO AO AO VDDA-VBAT
Ball information STw4810 balls function (continued)
Ball name Ball type Description
Batter y power supply for step down VIO_VMEM Ground for step down VIO_VMEM BUCK of step down VIO_VMEM VIO_VMEM Feed back input Batter y power supply for step down VCORE Ground for step down VCORE BUCK of step-down VCORE VCORE sense Batter y supply for VPLL, VANA VANA output VPLL output VAUX output Batter y supply for VAUX
Interrupt to modem for wake-up due to USB plug Output enable of the differential driver in the USB mode Data input in the USB transmit mode, positive data input the single-ended transmit mode, or TXD in UART mode Single-ended zero input in the USB transmit mode, negative data input in the single-ended transmit mode, or RXD in the UART mode Differential receiver output Positive data line in the USB mode, or serial data input in the UART mode Negative data line in the USB mode, or serial data output in the UART mode. ID ball of the USB detector used for protocol identification. C plus flying capacitor (VBUS level 4.4 to 5.25)
J7
USBVP
J8 K7 E9 E10 E8 H10
USBVM USBRCV DP DN ID CP
11/78
Ball information Table 2.
Ball J10 G10 F10 G9 H9 H8 CN VBUS VUSB USBSCL USBSDA USBINTn
STw4810
STw4810 balls function (continued)
Ball name Ball type AIO(VBUS) AIO(VBUS) AIO DI(VIO_VMEM) DIO(VIO_VMEM) DO(VIO_VMEM) Description C minus flying capacitor (VBUS Level) USB cable supply (VBUS Level) Decoupling capacitor for USB internal regulator Clock for dedicated USB I2C SDA for dedicated USB I2C Interrupt to multimedia processor for USB or accessory plug
SD MMC balls G3 MCCMDDIR DI(VIO_VMEM) Pull Down 1.5M DI(VIO_VMEM) Pull Down 1.5M DI(VIO_VMEM) Pull Down 1.5M CMD direction. - "high": CMD signal from processor to card - "Low": CMD signal from card to processor DATA0 direction - "high": DATA0 signal from processor to card - "Low": DATA0 signal from card to processor DATA2 direction - "high": DATA2 signal from processor to card - "Low": DATA2 signal from card to processor DATA(3,1) direction - "high": DATA(3,1) signal from processor to card - "Low": DATA(3,1) signal from card to processor Host clock, between processor and STw4810, to the card (processor clock). Host feedback clock between STw4810 and processor, to re-synchronize data in processor. Bidirectional command/response signal between processor and STw4810. Bidirectional data0 between processor and STw4810 Bidirectional data [3:1] between processor and STw4810. Host feedback clock to STw4810, to resynchronize data in processor. Host clock, between STw4810 and card (processor clock). Bidirectional command/response signal between STw4810 and processor. Bidirectional data0 between STw4810 and card
K2
MCDAT0DIR
K9
MCDAT2DIR
H4
MCDAT31DIR
DI(VIO_VMEM) Pull Down 1.5M
G2 H5 H1 K1 H2 H3 J1 F3 G1 F2 E1
MCCLK MCFBCLK MCCMD MCDATA0
DI(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) DIO(VIO_VMEM) Pull Up 1.5M DIO(VIO_VMEM) Pull Up1.5M DIO(VIO_VMEM) Pull Up 1.5M DI(VMMC) Pull Down 1.5M DO(VMMC) DIO(VMMC) Pull Up 1.5M DIO(VMMC) Pull Up 1.5M
MCDATA[3:1]
LATCHCLK CLKOUT CMDOUT DATAOUT0
12/78
STw4810 Table 2.
Ball F1 E3 E2 J4 K5 Other balls J5 K6 B9 D3 B1 B7 B8 C5 F8 G8 K10 GPO1 GPO2 "Reserved" AO AO G General purpose output General purpose output To be connected to ground
Ball information STw4810 balls function (continued)
Ball name DATAOUT[3:1] VBAT_MMC VMMC Ball type DIO(VMMC) Pull Up 1.5M VDDA-VBAT AIO Description Bidirectional data[3:1] between STw4810 and card. Batter y supply for VMMC VMMC supply output
"Reserved"
O
To be left open
13/78
Functional description
STw4810
4
4.1
Functional description
Introduction
The STw4810 integrates all the power supplies for a multimedia processor as well as memories and peripherals:
Two switched mode power supply regulators: one for the multimedia processor core, one for multimedia processor I/Os and memories Three low-drop output regulators for multimedia processor analog supplies (PLL and others) and auxiliary components USB OTG FS/LS physical interface MMC card power supplies and level shifters Multimedia processor supply monitoring / power-on reset and power supply alarms / interrupt management Two serial I2C communication interfaces; one to control the devices (SDA, SCL) and one to control the USB (USBSDA, USBSCL).
4.2
Digital control module
This module describes the interfaces used to program the device and the related registers.
4.2.1
State machine
Description of each states: (Figure 3.) Off: In this mode the STw4810 is switched off. Off is when PON=0, when battery level is under 2.4 V or when thermal shutdown is activated. There is no multimedia processor power supply. The only active cell is the USB cable detection and VBAT level detection. OSC_START: Oscillator is enabled and the power up module is waiting for the rising edge of the internal signal OSC_OK to start power up sequence. This state duration is 300 s. START_BIAS: Bias, reference and thermal shut-down are enabled, a counter is activated to wait for rising edge of internal signals PDN_regulators. This state duration has a typical value of 7.77 ms and a worst case value of 9.46 ms. START_PM: after a 1 ms wait, multimedia processor power supplies are available (VIO_VMEM, VCORE, VPLL, and VANA). The device can allow I2C communication, output power supply monitoring and application (USB,SD/MMC). OFF2: STw4810 is waiting for the 32 kHz multimedia processor signal. This state has an indeterminate duration. If 32kHz is present during the states describes above, it has no effect. The 32 kHz signal is taken into account by STw4810 only when the `VDDOK' ball is high, that is at the end of START_PM state. Reset: STw4810 forces a reset during 10*32 kHz period before setting PORn high. INT_OSC: The STw4810 can work without MASTER_CLK via its internal oscillator. The device waits for an external clock detection before switching to the external clock. When receiving a rising edge on PWREN ball (coming from multimedia processor) or on TCXO_EN ball (coming from modem), STw4810 answers by asserting to "1" the
14/78
STw4810
Functional description REQUEST_MC ball. STw4810 remains in internal oscillator mode until it receives the external clock signal on MASTER_CLK ball. EXT_CLK: When MASTER_CLK is detected, the STw4810 uses this clock as reference and switches off its internal oscillator to save quiescent. MASTERCLK should remain connected up to sleep mode. Sleep: Sleep mode is required by multimedia processor by setting a PWREN at low level. Then VDDOK is forced to 0, regulators (VCORE, VIO_VMEM) switch to sleep mode and wait for PWREN at high level (Figure 4). Wake-up: From sleep mode, the multimedia processor requests to switch back to Normal mode. Thus the device restarts its internal oscillator and then switches regulators from sleep to normal mode and informs multimedia processor with VDDOK at high level (Figure 4).
Note:
By default VAUX is in stand by mode, pdn_vaux = 0 (Table 18). It can be programmed in normal mode only by asserted pdn_vaux bit to "1".
15/78
Functional description Figure 3. Start-up timing
OFF VBAT PON ball
300s
9.38ms (11ms wc)
STw4810
PDN__OSC
START_BIAS
START_PM
1ms
PDN_regulators VDDOK ball
7.77ms (9.46ms wc)
11*(1/32kHz)
CLK32K_IN ball PORn ball PWREN ball
(*)
Reset PWREN unmasked
Internal_OSC MASTER_CLK ball TCXO_EN ball REQUEST_MC ball
OFF2 VPLL / VIO_VMEM VCORE
"or"
Reset
INT_OSC
Voutput(s) ball
CLK32K ball Delays are worst case maximum delays (*) If 32 kHz available before VDDOK signal rising edge, OFF2 state duration is null
All regulators are started with PDN_regulators but can be switched off from the beginning or during application by software (Table 27)
16/78
STw4810 Figure 4. Switching POWER to sleep timing
HPM PWREN Sleep regulators V DDOK P DN_regulat ors CLK 32K PDN_intOSC int_OSC_detect REQUEST_MC Inter nal_OSC MA ST ER _C LK SLEEP ~100s
Functional description
HP M
Registers reset
In the event of a hardware reset coming from the modem, PON ball set to "0", all registers are reset at initial value when PON ball goes back to "1" level. A software reset from multimedia processor of STw4810, through SW_RESETn ball set to "0", reset all registers except power control register (at address 1E & 1F).
Main clock oscillator control
REQUEST_MC is an OR output gate between PWREN (coming from multimedia processor) and TCXO_EN (coming from modem supply), it is synchronized on 32 kHz, except during power-up where PWREN is masked and considered as high. REQUEST_MC enabled or disabled the master clock oscillator device.
17/78
Functional description
STw4810
4.2.2
POWER OFF / VDDOK
In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM detected, or `it_twarn' bit set to "1" (Table 18), then multimedia processor is reset (PORn low during a minimum time of 312.5 s) and restarted with no time-out. (see Figure 5). In case of VDDOK falling edge because PWREN balls equals "0", there is no reset (PORn still high). In case of PON falling edge (STw4810 switched off from modem) multimedia processor is also reset with no time-out. We consider that clean switch off between modem and multimedia processor is done by software directly. VDDOK block diagram
Digital block & & VDDOK
Figure 5.
PWREN
vcore_monitor vio_monitor
it_twarn mask_twarn register reset after read operation or PON falling edge or PORN_VBAT.
Reg status
Under voltage detection VDDOK Operating voltage threshold value reached
PORn 312.5 s (10* 32 Khz)
4.2.3
Sleep mode
STw4810 goes into sleep mode by different ways. Whether VCORE, VIO_VMEM and VAUX are programmed to sleep mode or not is indicated in Table 27.
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STw4810
Functional description
4.2.4
I2C Interface
The device supports two I2C bus interfaces. One main interface (SDA,SCL) controls power management and all programmable functions, the second interface (USBSDA, USBSCL) is dedicated to USB control. STw4810 allows to work with only the main I2C interface to control all the functions, including the USB, via USB_I2C_CTRL bit of power control register (Table 27). I2C Interface is used to read status information from inside the device. Flags, interrupt and write registers are used to configure the device functions (threshold, clock division, output voltage, etc....). By default, the main I2C interface (SCL,SDA) controls the main registers and USB I2C interface (USBSCL, USBSDA) controls USB registers. Figure 6. I2C interface block diagram
SCL SDA usb_i2c_ctrl SCL MUX SDA USBSCL USBSDA
Main registers
SCL or USBSCL SDA or USBSDA USB registers
Both I2C are configured as slave serial interface compatible with I2C registered trademark of Phillips Inc. (version 2.1).
I2C interface description
STw4810 I2C is a slave serial interface with a serial data line (SDA or USBSDA) and a serial clock line (SCL or USBSCL): SCL / USBSCL: input clock used to shift data SDA / USBSDA: input/output bidirectional data transfers One filter to reject spikes on the bus data line and preserve data integrity Bidirectional data transfers up to 400kbit/s (Fast-mode) via SDA or USBSDA signal
It is composed of:
The SDA or USBSDA signal contains the input/output control and data signals that are shifted in the device, MSB first. The first bit must be high (START) followed by the Device ID (7 bits) and Read/Write bit control (1 indicates read access, a logical 0 indicates a write access). Device ID in write mode: 5Ah (01011010) Device ID in read mode: 5Bh (01011011)
Then STw4810 sends an acknowledge at the end of an 8 bits transfer. The next 8 bits correspond to the register address followed by another acknowledge. The 8 bits data field is sent last, followed by a last acknowledge.
19/78
Functional description Table 3.
b7 AdrID6
STw4810
Device ID
b6 AdrID5 b5 AdrID4 b4 AdrID3 b3 AdrID2 b2 AdrID1 b1 AdrID0 b0 R/W
Table 4.
b7 RegADR7
Register address
b6 RegADR6 b5 RegADR5 b4 RegADR4 b3 RegADR3 b2 RegADR2 b1 RegADR1 b0 RegADR0
Table 5.
b7 DATA7
Register data
b6 DATA6 b5 DATA5 b4 DATA4 b3 DATA3 b2 DATA2 b1 DATA1 b0 DATA0
I2C interface modes
Figure 7. Control interface: I2C format
DEVICE ADDRESS ACK ACK REGn ADDRESS REGn Data In ACK
WRITE SINGLE BYTE
01011010
START STOP
RANDOM ADDR READ SINGLE BYTE
DEVICE ADDRESS
ACK ACK REGn ADDRESS
DEVICE ADDRESS
ACK REGn Data Out
NO ACK
01011010
START
01011011
START
RANDOM ADDR READ MULTI BYTE DEVICE ADDRESS ACK ACK REGn ADDRESS ACK DEVICE ADDRESS ACK Reg n Data Out ACK
01011010
START
01011011
START
NO ACK Reg n + m Data Out STOP
m+1 data bytes
Figure 8.
Control interface: I2C timing
SDA USBSDA SCL USBSCL
Stop
tbuf thd_sta tf tlow tr thigh thd_dat tsu_dat
tsu_sta tsu_sto thd_sta
Start
Start repeated
Stop
20/78
STw4810
Functional description
4.2.5
Control registers
Control registers have the following functions: Select level of regulation for multimedia processor supply Control the USB interface Control the SD/MMC/SDIO interface Control the state machine
Table 6.
Register general information
Comment USB Registers (Table 9 to Table 17) SD MMC Control register (Table 18) Test registers Power control registers (Table 19 to Table 27) twarning register (Table 28) SDA / SCL SDA / SCL I2C control USBSDA / USBSCL or SDA / SCL (1) SDA / SCL
Address 00h to 10h 11h 12h to 1Dh 1Eh to 1Fh 20h
1. Controlled by USB_I2C_CTRL bit of Power control register (Table 27)
Table 7.
Register summary
Addr. 00h 7 1 0 0 0 Not used vbus_ chrg cr_int cr_int cr_int cr_int Not used monitori ng_vio_ vmem_ vcore 6 0 0 0 1 uar t_en vbus_ dischrg bdis_ acon bdis_ acon bdis_ acon bdis_ acon 5 0 0 0 0 oe_int_ en vbus_ drv id_float id_float id_float id_float 4 0 0 1 0 3 0 0 0 0 2 0 1 0 0 1 1 0 0 0 0 1 0 0 0
Register Vendor ID
01h 02h Product ID 03h USB control register 1 USB control register 2 USB interrupt source USB interrupt latch USB interrupt mask false USB interrupt mask true USB EN 04h 05h 06h 07h 08h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h
bdis_ not used dat_se0 acon_en id_gnd dn_hi dn_hi dn_hi dn_hi
suspend speed dp_ pullup
dn_ dp_ dn_ pulldown pulldown pullup id_gnd_ forced id_gnd_ forced id_gnd_ forced id_gnd_ forced dp_hi dp_hi dp_hi dp_hi
sess_vld vbus_vld sess_vld vbus_vld sess_vld vbus_vld sess_vld vbus_vld usb_en not used pdn_ vmmc mask_ twarn
SD MMC control
11h
pdn_ vaux
it_warn
gpo2
gpo1
sel_vmmc<1:0>
Twarning
20h
Not used
21/78
Functional description Table 8. Power control register
Addr. 1Fh Addr. 1 Eh 7 6 reg address 3 bits 5 15 14 13 12 11 10 9
STw4810
Register Power control Register Power control
8
Not used 4 3 2
reg address 2 bits 1 0 ena write
data din/dout 4 bits
Registers controlled by I2C USB bus
The registers described in this chapter are controlled through the USB serial I2C interface, USBSCL and USBSDA balls. These registers could also be controlled through the main I2C interface, SCL and SDA balls by setting to "1" USB-I2C_CTRL bit in Power control register (Table 23). Table 9. USB register address
Register Vendor ID Product ID USB Control Register 1 USB Control Register 1 USB Control Register 2 USB Control Register 2 USB Interrupt Source Not used USB Interrupt Latch USB Interrupt Latch USB Interrupt Mask False USB Interrupt Mask False USB Interrupt Mask True USB Interrupt Mask True USB_EN R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R Type
Address 00h - 01h 02h - 03h 04h set 05h clearh 06h set 07h clearh 08h 09h 0Ah set 0Bh clearh 0Ch set 0Dh clearh 0Eh set 0Fh clearh 10h
Note:
A bit of register 1 is set at "1" by writing a "1" at address 04h, is reset at "0" by writing a "1" at address 05h. This is also applicable for USB Control Register 2 (06h, 07h), USB Interrupt register (0Ah,0Bh), USB Interrupt Mask False register (0Ch, 0Dh) and USB Interrupt Mask True register (0Eh, 0Fh). Writing "0" at any address has not effect on the content of any register.
22/78
STw4810 Table 10. Vendor ID and Product ID: Read only
Name Vendor ID Vendor ID Product ID 03h Address 00h 01h 02h
Functional description
Register Value 83h 04h 10h 40h
USB control register 1
Table 11.
Register Bit name Type
USB control register 1 (address = 04h set and 05h clearh)
7 Not used 6 uar t_en R/W 5 4 3 2 1 0 speed R/W
oe_int_ bdis_ not used dat_se0 suspend en acon_en R/W R/W R/W R/W
Bits 6 5
Name uar t_en oe_int_en
Value 0 1 0 1 0 1 0 1 0 1
Settings Inactive UART logic buffers are enabled Inactive Allow to send interruption through USBOEn Inactive (default) Enable A-device to connect if B-device disconnect detected: VP_VM USB mode DAT_SE0 USB mode Inactive (default) Put transceiver in low power mode Set rise and fall times of transmit Low speed Full speed
Default 0 0
4
bdis_acon_en
0
2
dat_se0
0
1
suspend
0
0
speed
0 1
0
23/78
Functional description
STw4810
USB control register 2
Table 12.
Register Bit name Type
USB control register 2 (Address = 06h set and 07h clearh)
7 vbus_ chrg R/W 6 vbus_ dischrg R/W 5 vbus_ dr v R/W 4 id_gnd R/W 3 dn_ pulldown R/W 2 dp_ pulldow n R/W 1 dn_ pullup R/W 0 dp_ pullup R/W
Bits 7
Name vbus_chrg
Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Settings Inactive Charge VBUS through a resistor Inactive Discharge VBUS through a resistor to ground. Inactive Provide power to VBUS Inactive Connect ID ball to ground Inactive Connect DN pull-down Inactive Connect DP pull-down Inactive Connect DN pull-up Inactive Connect DP pull-up
Default 0
6
vbus_dischrg
0
5
vbus_drv
0
4
id_gnd
0
3
dn_pulldown
0
2
dp_pulldown
0
1
dn_pullup
0
0
dp_pullup
0
24/78
STw4810
Functional description
USB interrupt source register
Table 13.
Register Bit name Type
USB Interrupt source register (address = 08h)
7 cr_int R 6 bdis_ acon R 5 id_float R 4 dn_hi R 3 id_gnd_ forced R 2 dp_hi R 1 sess_ vld R 0 vbus_ vld R
Bits 7 cr_int
Name
Value 0 1 0 1
Settings Inactive DP ball is above the carkit interrupt threshold Inactive Set when bdis_acon_en is set, and transceiver asserts dp_pullup after detecting B-device disconnect. Inactive ID ball floating Inactive DN ball is high Inactive ID ball grounded Inactive DP asserted during SRP, Session valid comparator threshold <0.8V or >4.4V 0.8V < Session valid comparator threshold < 4.4V A-device VBUS valid comparator threshold <4.4V A-device VBUS valid comparator threshold >4.4V
Default 0
6
bdis_acon
0
5
id_float
0 1 0 1 0 1 0 1 0 1 0 1
0
4
dn_hi
0
3
id_gnd_forced
0
2
dp_hi
0
1
sess_vld
0
0
vbus_vld
0
USB latch register
Table 14.
Register Bit name Default Type
USB interrupt latch registers (address = 0Ah set and 0Bh clearh)
7 cr_int 0 R/W 6 bdis_ acon 0 R/W 5 id_float 0 R/W 4 dn_hi 0 R/W 3 id_gnd_ forced 0 R/W 2 dp_hi 0 R/W 1 sess_ vld 0 R/W 0 vbus_ vld 0 R/W
USB interrupt latch register bits indicate which sources have generate an interrupt.
25/78
Functional description
STw4810
USB interrupt mask false register
Table 15.
Register Bit name Default Type
USB interrupt mask false register (address = 0Ch and 0Dh)
7 cr_int 0 R/W 6 bdis_ acon 0 R/W 5 id_float 0 R/W 4 dn_hi 0 R/W 3 id_gnd_ forced 0 R/W 2 dp_hi 0 R/W 1 sess_vl d 0 R/W 0 vbus_vl d 0 R/W
USB interrupt mask false register bits enable transition from true to false.
USB interrupt mask true register
Table 16.
Register Bit name Type
USB interrupt mask true register (address = 0Eh and 0Fh)
7 cr_int R/W 6 bdis_ acon R/W 5 id_float R/W 4 dn_hi R/W 3 id_gnd_ forced R/W 2 dp_hi R/W 1 sess_vl d R/W 0 vbus_vl d R/W
USB interrupt mask true register bits enable interrupts on transition from false to true.
USB EN register
Table 17.
Register Bit name Type -
USB EN register (address = 10h)
7 6 5 4 Not used 3 2 1 0
usb_en not used R/W -
Bits 1
Name usb_en
Value 0 1 Inactive Enable USB PHY
Settings
Default 0
26/78
STw4810
Functional description
Registers controlled by main I2C bus
I²C controlled registers are controlled through the main serial I2C interface, SCL and SDA balls.
SD MMC control register
Table 18.
Register
SD MMC control register (11h)
7 pdn_ vaux R/W 6 5 4 3 2 1 0 pdn_ vmmc R/W
Bit name
monitori ng_vio_ it_warn vmem_ vcore R(1) R(1)
gpo2
gpo1
sel_vmmc<1:0>
Type
R/W
R/W
R/W
1. These bits are reset (0) after reading
Bits 7
Name pdn_vaux
Value 0 1 0 1 0 1 0 1 0 1 00 01 10 11 0 1 Inactive Enable LDO vaux
Settings
Default 0
6
it_warn monitoring_vio_ vmem_vcore gpo2
Below temperature threshold Above temperature threshold Outputs in the good range Outputs lower than expected on vio_vmem or vcore Output GPO2 HZ Output GPO2 Low Output GPO1 HZ Output GPO1 low 1.8V selection 1.8V selection 2.85V selection 3V selection Inactive Enable SD/MMC or SDIO function.
0
5
0
4
0
3
gpo1
0
[2:1] sel_vmmc<1:0>
00
0
pdn_vmmc
0
In Flash OTP two registers allow to program STw4810 energy management part. These two registers are at address 1E and 1F and must be programmed with 1F register first followed by 1E register.
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Functional description
STw4810
Power control register at address 1Eh
Table 19.
Register Bit name Type
Power control register - General information (Address = 1Eh)
7 6 5 4 3 2 1 0 EN R/W
reg address 3 bits LSB's R/W
data din/dout 4 bits R/W
Bits [7:5] [4:1]
0
Name reg address 3 bits data din/ dout 4 bits EN
Value
Settings See Table 21 "Address" column (LSB's). See Table 21 control register
Default 0 0 0
0 1
Read enabled Write enabled
Power control register at address 1Fh
Table 20.
Register Bit name Type
Power control register - General information (Address = 1Fh)
15 14 13 12 11 10 9 8
Not used
reg address 2 bits MSB's R/W
Bits [9:8]
Name reg address 2 bits MSB's
Value
Settings See Table 21 "Address" column (MSB's).
Default 0
Power control register mapping
Table 21. Power control register mapping
Address 1Fh reg address Not used 15 14 13 12 11 10 2 bits MSB's 9 8 7 3 bits LSB's 6 5 4 data din/dout 4 bits 3 2 1 Comments EN 0 Test purpose Setting See Table 22 to Table 27 Test purpose Address 1Eh
00h to 04h 05h to 0Ah 0Bh to 1E
Caution:
Only the latest value written in register at address 1E/1F can be read.
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STw4810
Functional description
Power control register at address 05h
Table 22. Power control register at address 05h
Address 1Fh 15 14 13 12 11 10 9 0 Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 = 1.00V = 1.05V = 1.10V = 1.15V = 1.20V (default) = 1.22V = 1.24V = 1.26V = 1.28V = 1.30V = 1.32V = 1.34V = 1.36V = 1.38V = 1.40V = 1.50V 8 0 7 1 6 0 5 1 4 Address 1Eh 3 2 1 0 EN Default
Not used Bits Name
vcore_sel [3:0] Settings
[4:1]
vcore_sel [3:0]
0100
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Functional description
STw4810
Power control register at address 06h
Table 23. Power control register at address 06h
Address 1Fh 15 14 13 12 11 10 9 0 8 0 7 1 6 1 5 0 4 vpll_sel [0] Settings = 1.05V = 1.2V = 1.3V = 1.8V = 1.5V = 1.8V = 2.5V = 2.8V USB I2C interface controls USB registers Main I2C interface controls USB registers Address 1Eh 3 2 1 usb_ i2c_ctrl 0 EN
Not used
vaux_sel <1:0>
Bits
Name vpll_sel[1:0] on 06h and 07h address
Value 00 01 10 11 00 01 10 11 0 1
Default
4
11
[3:2] vaux_sel[1:0]
00
1
usb_i2c_ctrl
0
Power control register at address 07h
Table 24. Power control register at address 07h
Address 1Fh 15 14 13 12 11 10 9 0 8 0 7 1 6 1 5 1 4 en_vpll Address 1Eh 3 not used 2 en_ vcore 1 vpll_sel [1] 0 EN
Not used
Bits 4
Name en_vpll
Value 0 1 0 1 -
Settings Disabled / VPLL = OFF Enabled / VPLL = ON(1) Disabled / VCORE = OFF Enabled / VCORE = ON(1) See Table 23
Default 1
2 1
en_vcore vpll_sel[1]
1 -
1. No soft start feature at supply enabled after a disabled/enabled sequence
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STw4810
Functional description
Power control register at address 08h
Table 25. Power control register at address 08h
Address 1Fh 15 14 13 12 11 10 9 0 8 1 7 0 6 0 5 0 4 Address 1Eh 3 2 en_ vana 1 not used 0 EN
Not used
en_clk en_mo square nitorin r g Settings
Bits 4
Name en_clock_squarer
Value 0 1 0 1 0 1
Default 0
Disabled Enabled (sine wave signal input) Disabled / MONITORING = OFF Enabled / VCORE & VIO_VMEM monitoring = ON Disabled / VANA = OFF Enabled / VANA = ON
3
en_monitoring
1
2
en_vana
1
Power control register at address 09h
Table 26. Power control register at address 09h
Address 1Fh 15 14 13 12 11 10 9 0 8 1 7 0 6 0 5 1 4 vaux_ sleep Address 1Eh 3 not used 2 not used 1 not used 0 EN
Not used
Bits
Name
Value
Settings When PWREN is low: VAUX stays in normal mode VAUX goes in sleep mode (default) Reserved Reserved
Default
4
vaux_sleep
0 1
1
2 1
Not used Not used
1 1
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Functional description
STw4810
Power control register at address 0Ah
Table 27. Power control register at address 0Ah
Address 1Fh 15 14 13 12 11 10 9 8 7 6 5 4 vaux_ force_ sleep Address 1Eh 3 not used 2 1 0
Not used
0
1
0
1
0
vio_ vcore_ vmem_ force_ force_ sleep sleep
EN
Bits 4
Name vaux_force_sleep
Value 0 1 0 1 0 1
Settings 0: VAUX in normal mode 1: VAUX goes in sleep mode (for any PWREN level) 0: VIO_VMEM in normal mode 1: VIO_VMEM goes in sleep mode (for any PWREN level) 0: VCORE stays in normal mode 1: VCORE goes in sleep mode (for any PWREN level)
Default 0
2
vio_vmem_force_ sleep
0
1
vcore_force_sleep
0
Twarning register
Table 28.
Register Bit name Type
Twarning register (Address = 20h)
7 6 5 4 Not used 3 2 1 0 mask_ twarn R/W
Bits
Name
Value 0 1
Settings Inactive Mask TWARN interruption (it_twarn bit) through VDDOK
Default
0
mask_twarn
0
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STw4810
Functional description
4.2.6
IT generation
STw4810 has three interrupt balls: IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is plugged this interrupt is activated to wake up the host or the modem, depends of application (active low). USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor VDDOK: This ball has two functions: - When high, it indicates that VIO_VMEM and VCORE output voltages are within the right range and that the device internal temperature is below the maximum allowed temperature. - When low, it indicates that output regulators (VCORE or VIO_VMEM) are not regulated properly or PWREN = "0", or that the temperature is above the allowed threshold (see Thermal shut-down section). The interruption source in the application register (address 11h) needs to be checked.
4.2.7
Clock switching and control
This block generates the clock used by the DC/DC converter (USB charge pump, step-down VIO_VMEM and step-down VCORE). STw4810 is able to sustain the master clock frequencies of 26 MHz, 19.2MHz and 13 MHz. It can also sustain dedicated MASTER_CLK signal in the frequency range of 750KHz to 1MHz. If the clock is not detected the internal oscillator is automatically selected.
Note:
Figure 9.
When present the Master clock should remain connected up to sleep mode.
Clock switching between master and internal clock (1)
internal clock transition external clock
* Phase delay is less than 90 between int and ext clock
PON INT_OSC INT_OSC_OK MASTER_CLK_OK Third rising edge after switching PDN_INT_OSC CONTROL_SWITCH
MASTER_DIV_CLK STEP_DOWN_CLK
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Functional description
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4.3
Power management module
STw4810 includes several regulators that supply the multimedia processor and its peripherals. All regulators can work in different modes depending on the processor needs. When the STw4810 is in `low current mode'", the output current is reduced to save energy via the lower quiescent current. The nominal mode is called high power mode (HPM). The mode is selected by PWREN signal according to both multimedia processor and STw4810 state. When PWREN = "0", sleep mode is selected. HPM is selected as default when PWREN = "1". Each regulator has a dedicated battery power supply. It can be powered down by a signal called PDN_regulator_name as shown in the Figure 2: STw4810 block diagram. In this mode, the regulator is switched off and only a leakage current is present (max. 1A). VCORE, VAUX and VPLL output voltages are programmable, through main I2C interface, using the "Regulator"_SEL[x:0] bits of the power control registers (Table 22 to Table 27). In addition, an output current limitation prevents high current delivery in case of output short circuit. All multimedia processor power supplies have the same soft start to prevent leakage in the multimedia processor device during the start-up phase. There is an exception with VAUX which can be started independently.
4.3.1
Bandgap, biasing and references
Figure 10. Block diagram of biasing and references of the device
BG Voltage reference control All internal references All internal biasing Bias generator VREF_18
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STw4810
Functional description
4.3.2
VCORE regulator: DC/DC step-down regulator
This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down regulator that generates the regulated power supply with very high efficiency. The 15 voltage levels enable dynamic voltage and frequency scaling suitable for any supply voltage of CMOS process, they also follow the processor process roadmap. The regulated output voltage levels are adjustable by the power control registers (Table 22), via the main I2C interface (SDA, SCL). The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to generate the switching clock of the SMPS. When this clock is not available, regulators run the internal RC oscillator. The DC/DC step-down regulator has the following main features;
Programmable output voltage, 15 levels from 1.0 V to 1.5 V (VCORE_SEL [3:0] bits of power control register - Table 22) 3 power domains: `Normal mode' when multimedia processor is in run mode, 600 mA full load `Low current mode' when multimedia processor is in sleep mode, 5 mA current capability. Fast switching from low current to normal mode. The regulator is in `low current mode' when multimedia processor is in sleep mode. PWREN signal indicates that the multimedia processor is about to switch to run mode. VDDOK signal indicates to the multimedia processor that all supplies are in the specified range.
Note:
The definition of sleep mode is given in section 4.2.3: Sleep mode. `Power down mode' or `standby mode' when regulator is switched off, no consumption (EN_VCORE bit of power control register - Table 28) Soft start circuitry at start up, from power off to normal mode, when PON ball changes from "0" to "1". Default setting defined by start-up configuration.
4.3.3
VIO_VMEM regulator: DC/DC step- down regulator
VIO_VMEM step-down regulator has the same structure than VCORE. The VIO_VMEM regulator supplies the IOs of the multimedia processor and its peripherals. This regulator can be used to supply the memories working with the multimedia processor, such as DDR-SDRAM. A switched mode power supply - voltage down converter is used to generate the 1.8 V regulated power supply with very high efficiency. The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to generate the SMPS switching clock. When this clock is not available, regulators can run the internal RC oscillator. Main features
Fixed 1.8 V output voltage Two power domains: `Normal mode' when multimedia processor is in run mode - 600 mA full load `Low current mode' when multimedia processor is in sleep mode, 5 mA current capability.
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Functional description
STw4810
Fast switching from low current to normal mode. The regulator is in `low current mode' when multimedia processor is in sleep mode. PWREN signal indicates that the multimedia processor is about to switch to run mode. VDDOK signal indicates to the multimedia processor that all supplies are in the specified range.
Note:
The definition of sleep mode is given in 4.2.3: Sleep mode section. Soft start circuitry at start up, from power off to normal mode, when PON ball changes from "0" to "1". Default setting defined by start-up configuration.
4.3.4
VPLL
This LDO is dedicated to the multimedia processor PLL (1.05 V, 1.2 V, 1.3 V, 1.8 V) power supply with 10 mA max full load (Power Control Registers - Table 27 and Table 28). Main features
Programmable output voltage, (VPLL_SEL[1:0] bits of power control register - Table 27 and Table 28) Two power domains: `Normal mode' 10 mA full load `Power down mode' or `standby mode' when regulators are switched off and there is no power consumption (EN_VPLL bit of power control register - Table 28)
Soft start circuitry at start up, from power off to normal mode, when PON ball changes from "0" to "1". Default setting defined by start-up configuration.
4.3.5
VANA
This LDO is dedicated to the multimedia processor analogue function (2.5 V) power supply with 10 mA full load. Main features:
2.5 V output voltage, Two power domains `Normal mode' 10 mA full load `Power down mode' or `standby mode' when regulators are switched off and there is no power consumption (EN_VANA bit of power control register - Table 29),
Default setting defined by start-up configuration.
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STw4810
Functional description
4.3.6
VAUX
This LDO is dedicated either to the multimedia processor input/output signals or to the auxiliar y devices. Power supply values are 1.5 V,1.8 V, 2.5 V, 2.8 V with 150 mA full load and 0.5 mA in sleep mode. In case of 1.5 V on the output, this LDO can be supplied by using VIO_VMEM DC/DC converter (1.8 V). One pad feed-back is used. Main features:
Programmable output voltage, 4 levels (VAUX_SEL[1:0] bits of Power control register - Table 27) Three power domains: `Normal mode' when multimedia processor is in run mode, 150 mA full load `Low current mode' when multimedia processor is in sleep mode, 0.5 mA current capability. Fast switching from low current to normal mode.
Note:
Definition of sleep mode is given in 4.2.3: Sleep mode section. `Power down mode' or `standby mode' when regulator is switched off, no power consumption (PDN_VAUX bit of SD MMC control register - Table 18) Default setting defined by start-up configuration
4.3.7
Power supply monitoring
This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drop below the threshold, the multimedia processor is reset. This feature can be desactivated by setting EN_MONITORING bit of Power control register (Table 29) to "0".
4.3.8
Power supply domains
Table 29 lists the register bits that control STw4810 supply domains for each supply.
Table 29.
Supply name VCORE
Power supply domains
Supply domains Description Normal STEP-DOWN 15 values VCORE_SEL[3:0] 1.8 V 4 values VPLL_SEL[1:0] 2.5 V 4 values VAUX_SEL[1:0] 3 values SEL_VMMC[1:0] VAUX_SLEEP VAUX_FORCE_SLEEP Sleep VCORE_SLEEP VCORE_FORCE_SLEEP VIO_MEM_SLEEP VIO_VMEM_FORCE_SLEEP EN_VPLL EN_VANA PDN_VAUX PDN_VMMC Power down EN_VCORE
VIO_VMEM STEP-DOWN VPLL VANA VAUX VMMC LDO LDO LDO LDO
Note:
More details on VMMC supply are given in Section 4.5
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Functional description
STw4810
4.3.9
Thermal shut-down
A thermal sensor is used to monitor the die temperature.
As soon as the die temperature exceeds the thermal warning rising threshold, VDDOK ball goes to "0" and `it_warn' bit is set to "1" (SD MMC control register - Table 18). The IC turns back VDDOK ball to "1" and `it_warn' bit to "0" when the device temperature drops below the thermal warning falling threshold of the thermal sensor. A second thermal detection level, thermal shutdown threshold, puts all STw4810 supplies OFF, the supplies goes back to goes back to ON state when the temperature is under the thermal shutdown threshold and after a new startup phase. Thermal threshold values
Description Min Typ Max Unit
Table 30.
Thermal warning threshold Rising threshold Falling threshold Thermal shutdown threshold Threshold 149 155 164 C 134 117 140 123 149 131 C C
Figure 11. Thermal threshold temperatures for `it_warn' bit and VDDOK ball
`it_warn' bit All supplies are turn "OFF"
VDDOK ball
Rising warning threshold Shutdown threshold Temperature
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STw4810
Functional description
4.4
USB OTG module
This transceiver complies with the USB specification:
Universal Serial Bus specification revision 2.0 `On the Go' supplement to the USB specification revision 1.0-a Car kit interface specification (see: OTG transceiver specification revision 0.92) Full and low speed transceiver (12 Mbit/s and 1.5 Mbit/s data rate) Suppor t data line and VBUS pulsing session request Host Negotiation Protocol (HNP) command and status register Charge pump regulator (5 V at 100 mA) to supply VBUS line of the USB cable VBUS pull-up and pull-down resistors as defined by Session Request Protocol (SRP) VBUS threshold comparators VUSB LDO internal regulator which provides power supply for the bus driver and receiver. ID line detector and interrupt generator Dedicated I²C serial control interface
The USB OTG transceiver has two modes: USB mode and UART mode. It includes:
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Functional description
STw4810
4.4.1
Block diagram
Figure 12. USB OTG transceiver block diagram
VBAT_USB VBAT_DIG CL K VMINUS_DIG CP CN
USB_INTn
vbus_vld sess_vld dn_hi Interrupt dp_hi Control bdis_acon Register id_gnd_forced id_float cr_int usb_en usb_i2c_ctrl vbus_drv bdis_acon_en dn_pullup dp_pullup Control dn_pulldown Registers dp_pulldown id_gnd vbus_chrg vbus_dischrg speed uar t_en dat_se0 oe_int_en suspend
RE F
R_VBU S_SRP
R_VBUS_PD
CHARGE PUMP 5V - 100mA
vbus_drv
100 mA
VBUS RA_BUS_IN
VBUS_MONITOR VBUS > 4.4 V vbus_vld sess_vld
2V < VBUS < 4.4 V
vbus_chrg
VBUS < 0.8V
VBAT_USB
Gnd VUSB_LDO
vbus_dischrg vbus_session_end
V US B
DP_MONITOR cr_int
DP
USBSCL
5.7 R
USBSDA
DP < [0.4 to 0.6] V
R
S CL
SDA
RXD RXD
TRANCEIVER
dn_pullup dp_pullup
RP U_DP
SW_RESETn
DAT_VP
Diff Tx
USBVM U S B OE n S E O_ V M OE _TP _ I N T
RPU_DN
USBVP
DP
out_diff_Rx Diff Rx suspend
RP D_DN US B RCV RCV DN RP D_DP
SINGLE ENDED DECODER
SE_DP VP dn_pulldown SE_DN
VM
VBAT_DIG
dp_pulldown
VBAT_USB
R
RID_PU 0. 85*I D ID
Plug detect Management
IT_WAKE_UP
id_float sess_vld id_gnd
4.7 R
OR ID Detector
R
0. 15*I D
id_gnd
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STw4810
Functional description
VBUS monitoring
These comparators monitor the VBUS voltage. They detect the current status of the VBUS line:
VBUS > 4.4 V means VBUS_VALID 2 V
These three bits generate an interrupt when active (see USB interrupt registers). VUSB LDO: Internal regulator which provides power supply for the bus driver and receiver. ID detector: This block detects the status of the ID line. It is capable of detecting three different states of line: ball is floating ID_FLOAT high, ball is tied to ground ID_GND high and ball ID is grounded via resistor. This detection generates interrupts (see USB interrupt registers). Transceiver: The driver can operate in several different modes. It can act as a classical lowspeed and full-speed differential driver, as two independent single-ended drivers or as a single-ended driver in UART mode. This block contains one differential receiver for the USB mode of operation and two single-ended receivers for USB signaling and UART mode. DP monitor: This block is used to detect car kit peripheral (0.6 V on DP). Pull up and pull down resistor: Configurable integrated pull-up and pull-down resistor of data line and VBUS.
4.4.2
Modes and operations
Power modes
The transceiver power modes are:
Active power mode Suspended power mode Power down mode
In suspended power mode the differential transmitter and receiver are turned off to save power but the USB interface is still active (pull-up and pull-down on, VBUS on). In power down mode, only the serial interface is active and the transceiver is able to detect SRP. In power down mode, ID ball sensing can be turned on/off via a control bit in the control registers.
USB modes
The two transceiver modes are:
DAT_SEO mode (dat_se0 = 1 in USB control register 1 - Table 11) VP_VM mode (dat_se0 = 0 in USB control register 1 - Table 11)
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Functional description
STw4810
Data transmission The transceiver transmits USB data in the following conditions for USB control register 1 (Table 31, Table 32): uar t_en=0; oe_int_en=0 Table 31. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0
Inputs USBVP 0 1 x 0 1 0 1 USBVM 0 0 1 0 0 1 1 DP 0 1 0 0 1 0 1 Outputs Comments DN 1 0 0 0 0 1 1 USBRCV Not used Not used Not used DIFF_RX DIFF_RX DIFF_RX DIFF_RX DAT_VP drives the level of DP SE0_VM drives the level of DN Single ended data (zero sent) Single ended data (1 sent) Force single ended zero
USB mode (DAT_SE0) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode)
Table 32.
Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1
Inputs Outputs Comments USBVP USBVM 0 0 1 0 0 1 1 DP 0 1 0 0 1 0 1 DN 1 0 0 0 0 1 1 USBRCV not used not used not used 0 (off) 0 (off) Driver are suspended 0 (off) 0 (off) Single ended data (zero sent) Single ended data (1 sent) Force single ended zero 0 1 x 0 1 0 1
USB mode (dat_se0) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode)
If oe_int_en = 1 and suspend=1 (USB control register 1 - Table 11), the USBOEn ball becomes an output used to generate an IT to multimedia processor.
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STw4810 The transceiver receives USB data in the following conditions: uar t_en = 0 (USB control register 1); oe_int_en = 1 Table 33. Data receiver via USB control register 1
Inputs USB mode (dat_se0) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) Suspend DP 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DN 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 USBVP Diff rcv 1 1 0 Diff rcv 1 0 1 0 1 0 1 0 1 0 1 0 1
Functional description
Outputs USBVM 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 USBRCV not used not used not used not used not used not used not used not used diff rcv 1 1 0 diff rcv 1 not used not used not used not used
UART mode
UART mode is entered by setting the `uart_en' bit to 1 (USB control register 1 - Table 11). The transceiver contains two digital logic level translators between the following balls:
TXD signal: from USBVM to DN RXD signal: from DP to USBVP
When not in UART mode the level translators are disabled.
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Functional description
STw4810
VBUS monitoring and control
The monitoring is made of three comparators that determine if the VBUS voltage is at a valid level for operation:
VBUS valid: It corresponds to the minimum level on VBUS. Any voltage on VBUS below the threshold is considered to be a fault. During power-up, it is expected that this comparator output is ignored. VBUS session valid: This threshold is necessary for session request protocol to detect the VBUS pulsing. VBUS session end: Session is ended. In this USB block, a B-device session end threshold is defined within the range [0.2; 0.8] V. The reason for a low 0.2 V limit is that the leakage current could charge the VBUS up to 0.2 V (maximum).
When the A-device (default master) is power supplied and does not supply VBUS, it presents an input impedance RA_BUS_IN on VBUS of no more than 100 k If the A-device . responds to the VBUS pulsing method of SRP, then the input impedance RA_BUS_IN may not be lower than 40 k . When the A-device supplies power, the rise time TA_VBUS_RISE on VBUS to go from 0 to 4.4 V is less than 100 ms when driving 100 mA and with an external load capacitance of 10 F (in addition to VBUS decoupling capacitance). If VBUS does not reach this voltage within TA_VBUS_RISE maximum time, it indicates that the B-device is drawing more current that the A-device is capable of providing and an over-current condition exists. In this case, the A-device turns VBUS off and terminates the session.
VBUS capacitance
A dual-role device must have a VBUS capacitance CDRD_VBUS value comprised between 1 F and 6.5 F (see charge pump specification). The limit on the decoupling capacitance allows a B-device to differentiate between a powered-down dual-role device and a powereddown standard host. The capacitance on a host is higher than 96 F.
Data line pull-down resistance
When an A-device is idle or acting as host, it activates the pull-down resistors RPD on both DP and DN lines. When an A-device is acting as peripheral, it disables RPD on DP, not DN. The A-device can disable both pull-down resistors during the interval of a packet transmission when acting as either host or peripheral. The two bits of USB control register, dn_pulldown and dp_pulldown (Table 12) are used to connect/disconnect the pull-down resistors. When the line is not used, the pull-down is activated and the maximum level on this ball should not exceed 0.342 V.
Data line pull-up resistance
Full-speed and low-speed devices are differentiated by the position of the pull-up resistor from the peripheral device. A pull-up resistor is connected to DP line for a full-speed device and a pull-up resistor is connected to DN line for a low-speed device. The pull-up resistor value is in the range of 900 to 1600 when the bus is idle and 1425 to 3100 when the upstream device is transmitting.
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STw4810
Functional description The two bits of USB control register dp_pullup and dn_pullup (Table 12) are used to connect/disconnect pull-up resistors.
Session Request Protocol (SRP)
To save power, the OTG supplement allows an A-device to leave the VBUS turned off when the bus is not being used. If the B-device wants to use the bus when VBUS is turned off, then it requires the A-device to supply power on VBUS using the Session Request Protocol (SRP).
Initial conditions
The B-device does not attempt to start a new session until it has determined if the A-device has detected the end of the previous session. The B-device must ensure that VBUS is below VBUS_SESSION_END before requesting a new session. Additionally, the B-device switches a pull-down resistor (R_VBUS_PD) from VBUS to ground in order to quicken the discharge process as long as the B-device does not draw more than 8 mA from VBUS. R_VBUS_PD is activated by bit `vbus_dischrg' of USB control register 2, (Table 12). When the B-device detects that VBUS is below the VBUS_SESSION_END and that both DP and DN have been low (SEO) for at least 2 ms, then any previous session on the Adevice is over and a new session can start.
Data-line pulsing
To indicate a request for a new session using the data line pulsing, the B-device turns on the DP pull-up resistor for 5 ms to 10 ms (only at full speed, no DN pulsing). The DP pull-up resistor is connected to VUSB (regulator output voltage). Timing is controlled by the USB digital control.
VBUS pulsing
To indicate a request for a new session using the VBUS pulsing method, the B-device waits for the initial conditions and then drives VBUS. VBUS is driven for a long enough period for a capacitance on VBUS that is smaller than 2x6.5 F to be charged to 2.1 V while a capacitance on VBUS higher than 97 F is not charged above 2.0 V. In this USB block, the VBUS_SESSION_VALID threshold is used to determine if an A-device is DRD (dual role device) or a standard host. The B-device VBUS pulsing block is designed so that the maximum drawn current does not exceed 8 mA. In this USB block, the pull-up is 600 +/- 30%. If a B-device is attached to a standard device, the pull-up must be disconnected after the defined timing to prevent damage of standard hosts not designed to withstand a voltage externally applied to VBUS.
Session Request Protocol (SRP)
If the B-device is in correct condition to start a new session, it first performs data line pulsing, followed by VBUS pulsing. When VBUS next crosses the SESSION VALID threshold, the B- device considers a session to be in progress and asserts the DP or DN data line within 100 ms. After SRP initialization, the B- device is set up to wait for at least 5 seconds for the A-device to respond before informing the user that the consumption attempt has failed.
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Functional description
STw4810
Host Negotiation Protocol (HNP)
At the start of a session, the A-device has the role of host as default. During a session, the host role can be transferred back and forth between the A-device and the B-device any number of times using the Host Negotiation Protocol (HNP). The process for this exchange of host role is described in the "On the Go Supplement to the USB 2.0 Specification" (rev 1.0).
ID detector
In either active or suspended power mode, the ID detector detects the condition of the ID line and differentiates between the following three conditions: ID ball floating: (e.g. with USB B-device connected) ID ball shorted to ground: (e.g. with USB A-device connected) ID ball connected to ground through resistor RACC_ID: (e.g.with an accessory).
The transceiver pulls the ID ball to VID_HI (VBAT) through a resistance of RID_PU when an accessory is plugged in. In this case, the ID ball is externally connected to ground via Racc_ID resistor. Two comparators are used to detect the ID voltage: VID_GND and VID_FLOAT. The ID detector also has a switch that can be used to ground the ID ball. This switch is controlled by id_gnd bit of USB control register 2 (Table 12); This pull-down is used for CEA_KARKIT purposes.
Car kit interrupt detector
The transceiver is able to detect when the DP line is below the Carkit Interrupt threshold `cr_int', (see USB interrupt register) (refer to OTG specifications, Rev 0.92, §2.7, p13).
Charge pump
From VBAT_USB, the charge pump supplies VBUS, `vbus_drv' bit of USB control register 2 (Table 12) is used to enable/disable the charge pump.
LDO USB
From VBAT_USB, a LDO provides VUSB supply, `usb_en' bit of USB_EN register (Table 17) is used to enable/disable the VUSB LDO.
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STw4810
Functional description
4.4.3
USB enable control
STw4810 OFF
In this state, the overall system is able to detect USB connection through IT_WAKE_UP ball and with VBUS session valid comparator and ID detection ON. IT_WAKE_UP is activated (low level) in either of the two following cases: When Mini A connector cable is connected and ID goes low When activity on VBUS, i.e. a mini B is connected and is able to communicate. This mode is used to wake-up the modem platform. In this configuration, USBINTn ball is not enabled.
STw4810 ON, USB driver not enabled
The USBINTn is now enabled. If the USB cable is already connected while STw4810 is starting, the USB driver will be enabled when power management is ready.
Wake-up USB driver conditions A plug-in on a mini A-device and active ID detector B device is connected and ready to start data transfer, VBUS is driven high (session valid high) Activity on USB registers (00h to 0Fh - Table 9 to Table 16). Multimedia processor ready to wake-up and set-up USB PHY. Possibility to force PHY high (enable) when writing usb_en = 1 in USB EN register (Table 17) External it_wake_up =0 usb_en = 1 by writing to I²C USB interface Access to any other USB register (00h to 0Fh) it_wake_up = 1, and only then Set usb_en bit of USB EN register (Table 17) to "0"
Set condition: one among the following possibilities
Power down USB driver conditions in order to set the USB driver to power down mode:
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Functional description
STw4810
4.5
SD/MMC/SDIO module
This block provides the power supply (1.8 V, 2.85 V or 3 V) and signal shifting functions required to connect any of the following peripherals to the multimedia processor: SD card MMC cards, low and 52 MHz high speed SDIO cards (except SDIO card version 1.0 / Vsupply range: [3.1; 3.6] V
Cards detection is automatically done by the multimedia processor system. Following a card detection, the multimedia processor starts the SD/MMC application by writing in the SD MMC control register (Table 18) to start LDO VMMC and then starts the protocol initialization. The module includes: 1.8 V, 2.85 V or 3 V voltage regulators (150 mA) Five bidirectional level shifter channels compatible with 1.8 V, 2.85 V or 3 V Two unidirectional lines for clock: multimedia processor to card and feedback clock to multimedia processor for synchronization. Four control signals for channel direction
Figure 13. SD MMC block diagram
SD/ MMC/SDIO INTERFACE
MCCMDDIR MCDATA0DIR MCDATA2DIR MCDATA31DIR VMMC
1.8V,2.85V,3V 150mA
VBAT_VMMC
MCCLK DRIVER
5 * RB Vsdc2 3 * RA 3 * RA
CLKOUT
EMIF
Level
RC Rs
SD, MMC SDIO OR CARDS
Dz
Shifter M CCM D MCDATA0 MCDATA[3:1] MCFBCLK CM DOUT DATAOUT0 DATAOUT[3:1] LATCHCLK
Dz
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STw4810
Electrical and timing characteristics
5
Electrical and timing characteristics
Otherwise specified parameters are defined for T = 25C. / VBAT = 3.6 V
5.1
Absolute maximum rating
Table 34.
Symbol
STw4810 absolute maximum ratings
Description Maximum power supply Values -0.5 to 7 -30 to 85 model(1) -2 to +2 -450 to +750 Units V C kV V
Ta
Maximum operating ambient temperature Human body
VESD
Electrostatic discharge model
Charge device model(2)
1. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM 2. CDM tests have been performed in compliance with CDM ANSI-ESD STM 5.3.1-1999
5.2
Package dissipation
Table 35.
Symbol
Package dissipation
Description Min. Typ. Max. Units
TFBGA 84 6x6x1.2mm 0.5mm ball pitch RTHJ-A Thermal resistance Junction to Ambient 70 C/W
VFBGA84 4.6x4.6x1.0mm 0.4mm ball pitch RTHJ-A Thermal resistance Junction to Ambient 76 C/W
5.3
Note:
Power supply
STw4810 has different ways to go in sleep mode.
The different possibilities for VCORE, VIO_VMEM and VAUX to be programmed to sleep mode are given in Table 30 and Table 27. In all the following tables: "Normal mode" is defined as "SLEEP = `0'" "Sleep mode" is defined as "SLEEP = `1'"
Use Table 27 to refer to each Vxxx supply (VCORE or VIO_VMEM or VAUX).
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Electrical and timing characteristics
STw4810
5.3.1
Operating conditions
Table 36.
Symbol VBAT IQSLEEP IQSTDBY
Operating conditions (Temp range: -30 to +85 C)
Description Power supply Sleep mode Quiescent Current Off mode 4 A Test conditions Min. 2.7 170 Typ. Max. 4.8 250 Units V A
5.3.2
VREF18
Table 37.
Symbol VBAT VREF_18 PSRR
VREF18
Description Supply voltage Output voltage Power supply rejection ratio Noise Vpp = 0.3 V f 100 kHz 100 Hz f 100 kHz Test conditions Min. 2.7 1.78 1.8 60 30 7.77 9.46 Typ. Max. 4.8 1.84 Units V V dB V ms
tS
Settling time
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STw4810
Electrical and timing characteristics
5.3.3
VCORE DC/DC step-down converter
Table 38.
Symbol
VCORE DC/DC step-down converter
Description Test conditions Min. Typ. Max. Units
VCORE regulator in normal mode (SLEEP = `0') / Otherwise specified; VCORE = 1.2 V VBAT VRIPPLE Input power supply Battery voltage Output voltage ripple VCORE_SEL[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 (default) 0011 0010 0001 0000 -3.7% 2.7 3.6 10 4.8 V mVpp
VOUT
Programmable output voltage
-4.25%
-5%
1.50 1.40 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 1.15 1.10 1.05 1.00
+3.7%
V
+4.25%
+5% 600 mA % 10 10 mV mV A A A dB
IOUT PEFF LIR LDR(1) ISHORT IQ ILKG PSRR(1) LIRT LDRT
Output current Power efficiency Line regulation Load regulation Shor t circuit current limitation(2) Quiescent current Power-down current Power supply rejection Transient line regulation Transient load regulation IOUT = 0 mA `en_vcore' = 0 Vpp = 0.3 V [0; 20] kHz VBAT = 300 mV tR = tF = 10 s IOUT = [1; 600] mA tR = tF = 100 ns 40 7 70 VBAT = 3.6 V IOUT = 200 mA VBAT: [2.7; 4.8]V IOUT: [0.1; 600] mA 0.9 1 .2 130 86
1.4 250 1
mV mV
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Electrical and timing characteristics Table 38.
Symbol
STw4810
VCORE DC/DC step-down converter (continued)
Description Test conditions Min. Typ. Max. Units
VCORE regulator in sleep mode (SLEEP= `1') VBAT VRIPPLE LIR LDR IOUT PEFF IQ LIRT Input power supply Battery voltage VCORE output voltage ripple Line regulation Load regulation VCORE output current Power efficiency Quiescent current Transient line regulation VBAT= 3.6 V IOUT: [0.1; 5] mA IOUT = 0 mA VBAT= 300 mV tR = tF = 10 s 85 20 7 30 VBAT: [2.7; 4.8]V IOUT: [0.1; 5] mA 2.7 3.6 10 10 10 5 4.8 V mVpp mV mV mA
% A mV
1. Guaranteed by design 2. Guaranteed by design
5.3.4
VIO_VMEM DC/DC step-down converter
Table 39.
Symbol
VIO_VMEM DC/DC step-down converter
Description Test conditions Min. Typ. Max. Units
VIO_VMEM regulator in normal mode (SLEEP = `0') VBAT VOUT VRIPPLE LIR LDR(2) IOUT PEFF Input power supply Battery voltage Output voltage (1) Output ripple Line regulation Load regulation Output current Power efficiency Shor t circuit current limitation(2) Quiescent current Power supply rejection Transient line regulation Transient load regulation IOUT = 0 mA Vpp = 0.3 V [0; 20] kHz VBAT = 300 mV tR = tF = 10 s IOUT= [1; 600] mA tR = tF = 100 ns 40 7 70 VBAT = 3.6 V, VIO = 1.8 V IOUT= 100 mA 0.9 VBAT: [2.7; 4.8]V IOUT: [0.1; 600] mA 2.7 -3% 3.6 1.8 10 10 10 600 4.8 +3% V V mVpp mV mV mA
90 1.2 130 1.4 250
% A A dB mV mV
ISHORT IQ PSRR(2) LIRT LDRT
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STw4810 Table 39.
Symbol
Electrical and timing characteristics VIO_VMEM DC/DC step-down converter (continued)
Description Test conditions Min. Typ. Max. Units
VIO_VMEM regulator in sleep mode (SLEEP='1') VBAT VRIPPLE LIR LDR IOUT PEFF IQ LIRT Input power supply Battery voltage Output ripple Line regulation Load regulation Output current Power efficiency Quiescent current Transient line regulation VBAT = 3.6 V IOUT = [0.1; 5] mA IOUT = 0 mA VBAT = 300 mV tR = tF = 10 s 7 85 15 VBAT: [2.7; 4.8]V IOUT: [0.1; 5] mA 2.7 3.6 10 10 10 5 4.8 V mVpp mV mV mA % A mV
1. Including output voltage temperature coefficient, DC line and load regulations, voltage reference accuracy, industrial manufacturing tolerances and ripple voltage due to switching 2. Guaranteed by design
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Electrical and timing characteristics
STw4810
5.3.5
LDO regulators
VPLL
Table 40.
Symbol
LDO regulators - VPLL
Description Test conditions Min. Typ. Max. Units
VPLL regulator in normal mode / otherwise specified, VPLL = 1.8 V VBAT Input power supply Battery voltage VPLL_SEL[1:0] 11 (default) 10 01 00 2.7 3.6 1.8 1.3 1.2 1.05 3.5 95 IOUT = 0 mA EN_VPLL = 0 Vpp = 0.3 V f < 10 kHz 10 kHz < f <100 kHz VBAT: [2.7; 4.8]V IOUT: [0.1; 10] mA VBAT = 300 mV tR = tF = 10 s IOUT = [0.1; 10] mA tR = tF = 1 s at 1 KHz BW = 100 Hz 1 1 250 130 30 4.8 V
VOUT
Output voltage
-3%
+3%
V
IOUT ISHORT IQ ILKG
Output current Shor t-circuit limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation Noise density
10 165 40 1
mA mA A A
PSRR(1)
55 45 5 10
dB dB mV mV mV mV nVrms Hz
LIR LDR LIRT LDRT En(1)
------------
1. Guaranteed by design
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STw4810
Electrical and timing characteristics
VANA
Table 41.
Symbol
LDO regulators - VANA
Description Test conditions Min. Typ. Max. Units
VANA regulator in normal mode VBAT VOUT IOUT ISHORT IQ ILKG PSRR(1) LIR LDR LIRT LDRT Input power supply Battery voltage Output voltage Output current Shor t-circuit limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation IOUT = 0 mA EN_VANA = 0 Vpp = 0.3 V f < 10 kHz VBAT: [2.7; 4.8] V IOUT: [0.1; 10] mA VBAT = 300 mV tR = tF = 10 s IOUT = [0.1; 10] mA tR = tF = 1 s 3 15 45 5 5 39 51 2.7 -5% 3.6 2.5 4.8 +5% 10 64 30 1 V V mA mA A A dB mV mV mV mV
1. Guaranteed by design
VAUX
Table 42.
Symbol
LDO regulators - VAUX
Description Test conditions Min. Typ. Max. Units
VAUX regulator in normal mode (PDN_VAUX= 1, SLEEP= `0') VOUT = 1.5V VBAT Input power supply VOUT = 1.8/2.5 V VOUT = 2.8 V VAUX_SEL[1:0] 00 (default) 01 10 11 1.7 2.7 3 -3% 3 .6 3.6 1 .5 1.8 2.5 2.8 4.8 4.8 4.8 +3% V V V
VOUT
Output voltage
IOUT ISHORT IQ ILKG
Output current Shor t-circuit limitation Quiescent current Power-down current IOUT = 0 mA PDN_VAUX = 0 350 700
150 900 30 1
mA mA A A
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Electrical and timing characteristics Table 42.
Symbol PSRR(1)
STw4810
LDO regulators - VAUX (continued)
Description Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation Settling time Test conditions VOUT=1.5 V Vpp = 0.3 V f < 10 kHz VOUT=1.5 V VBAT: [2.7; 4.8]V VOUT=1.5 V IOUT= [0.1; 150] mA VBAT = 300 mV tR = tF = 10 s IOUT = [10; 90%] mA tR = tF = 1 s 2 Min. 32 Typ. Max. Units dB
LIR LDR(1) LIRT
5 10
mV mV mV
LDRT tS
35 100
mV s
VAUX regulator in sleep mode (PDN_VAUX= 1, SLEEP='1') VOUT = 1.5V VIO_VMEM supply VBAT Input power supply VOUT = 1.8/2.5 V VOUT = 2.8 V VAUX_SEL[1:0] 00 (default) 01 10 11 1.7 2.7 3 -3% 3 .6 3.6 1 .5 1.8 2.5 2.8 4.8 4.8 4.8 +3% V V V
VOUT
Output voltage
IOUT IQ PSRR(1)
Output current Quiescent current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation IOUT = 0 mA VOUT=1.5 V Vpp = 0.3 V f < 10 kHz VOUT=1.5 V VBAT: [2.7; 4.8]V VOUT=1.5 V IOUT= [10; 90%] A VBAT = 300 mV tR = tF = 10 s IOUT = [10; 90%] A tR = tF = 1 s 2 35 38
500 15
A A dB
LIR LDR LIRT LDRT
5 10
mV mV mV mV
1. Guaranteed by design
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STw4810
Electrical and timing characteristics
5.3.6
Power supply monitoring
This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drops below the threshold, the multimedia processor is reset. Table 43.
Symbol Threshold THCORE(1) Threshold VCORE THVIO(1) Threshold VIO_VMEM -3% -3% VCORE150 1.65 +3% +3% mV V
Power supply monitoring
Description Test conditions Min. Typ. Max. Units
Comparators VBAT tRES HYFALL HYRIS Supply voltage Response time Hysteresis (input voltage falling) Hysteresis (input voltage rising) 2.7 3.6 100 26 +4 4.8 V ns mV mV
1. Guaranteed by design
5.4
5.4.1
Digital specifications
CMOS input/output static characteristics: I2C interface
Table 44.
Symbol I²C interface(1) VIL VIH II L II H Low level input voltage High level input voltage Low level input current High level input current Low level output voltage High level output voltage IOL = 3mA (with open drain or open collector) IOL = 3mA (with open drain or open collector) 0.8*VIO 0.7*VIO -1.0 -1.0 1.0 1.0 0.3*VIO V V A A
CMOS input/output static characteristics: I²C interface
Description Test conditions Min. Typ. Max. Units
VOL
0.2*VIO
V
VOH
V
1. Vio is for VIO_VMEM
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Electrical and timing characteristics
STw4810
5.4.2
CMOS input/output dynamic characteristics: I2C interface
Table 45.
Symbol I²C interface (Figure 8) Fscl thigh tlow tr tf thd_sta tsu_sta thd_dat tsu_dat tsu_sto tbuf Cb Clock frequency Clock pulse width high Clock pulse width low 600 1300
(1)
CMOS input/output dynamic characteristics: I²C interface
Description Min. Typ. Max. Units
400
Khz ns ns
SDA, SCL, USBSDA, USBSCL rise time 20+0.1*Cb SDA, SCL, USBSDA, USBSCL fall time Star t condition hold time Star t condition set up time Data input hold time Data input set up time Stop condition set up time Bus free time Capacitive load for each bus line
300 300
ns ns ns ns ns ns ns ns
20+0.1*Cb 600 600 0 250 600 1300
400
pF
1. Cb = total capacitance of one bus line in pF
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STw4810
Electrical and timing characteristics
5.4.3
CMOS input/output static characteristics: VIO level
USB and control I/Os
Table 46.
Symbol
VIO level: USB and control I/Os
Description Test conditions Min. Typ. Max. Units
SW_RESETn, VDDOK, PORN, PWREN, TCXO_EN, REQUEST_MC, CLK32K, CLK32K_IN, USBOEN, USBVP, USBVM, USBRCV, USBINTn, MASTER_CLK VIL(1) VIH II L II H CIN VOL VOH tO F tO R CI/O Low level input voltage High level input voltage Low level input current High level input current Input capacitance Low level output voltage High level output voltage Output fall time Output rise time Driving capability IOL = 4 mA IOL = 4 mA Capacitance 10pF Capacitance 10pF 0.8*Vio 10 10 100 0.7*Vio -1.0 -1.0 1.5 1.5 10 0.2*Vio 0.3*Vio V V A A pF V V ns ns pF
1. Vio for VIO_VMEM
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Electrical and timing characteristics
STw4810
MMC Interface
Table 47.
Symbol
VIO level: MMC interface
Description Test conditions Min. Typ. Max. Units
MMC interface: MCCLK, MCFBCLK, MCCMDDIR, MCCMD, MCDATA2DIR, MCDAT2, MCDATA0DIR, MCDAT0, MCDAT31DIR, MCDAT3, MCDAT1 VIL(1) VIH II L II H CIN VOL VOH CI/O Low level input voltage High level input voltage Low level input current High level input current Input capacitance Low level output voltage High level output voltage Driving capability at 52 MHz IOL = 15 mA IOL =15 mA 0.8*Vio 30 0.7*Vio -1.0 -1.0 1.5 1.5 10 0.2*Vio 0.3*Vio V V A A pF V V pF
1. Vio for VIO_VMEM
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STw4810
Electrical and timing characteristics
5.4.4
CMOS input/output static characteristics: VBAT level
Table 48.
Symbol
CMOS input/output static characteristics: VBAT level
Description Test conditions Min. Typ. Max. Units
IT_WAKE_UP, PON, GPO1, GPO2 VIL VIH II L II H CIN VOL Low level input voltage High level input voltage Low level input current High level input current Input capacitance Low level output voltage High level output voltage Output fall time Output rise time Driving capability IT_WAKE_UP, GPO1, GPO2 IOL = 2mA IT_WAKE_UP, GPO1, GPO2 IOL = 2 mA Capacitance 10pF Capacitance 10pF 0.8*Vbat 5 50 100 PON PON PON PON 0.7*Vbat -1 . 0 -1 . 0 1.5 1.5 10 0.2*Vbat 0.3*Vbat V V A A pF V
VOH tO F tO R CI/O
V ns ns pF
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Electrical and timing characteristics
STw4810
5.4.5
CMOS input/output static characteristics: VMMC level
Table 49.
Symbol
CMOS input/output static characteristics VMMC level
Description Test conditions Min. Typ. Max. Units
DATAOUT0, DATAOUT1, DATAOUT2, DATAOUT3, CMDOUT, LATCHCLK, CLKOUT VIL VIH II L II H CIN VOL VOH CI/O Low level input voltage High level input voltage Low level input current High level input current Input capacitance Low level output voltage High level output voltage Driving capability IOL = 25 mA IOL = 25 mA 0.8*VMMC 40 pF 0.7*VMMC -1.0 -1.0 1.5 1.5 10 0.2*VMMC A A pF 0.3*VMMC
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STw4810
Electrical and timing characteristics
5.5
Table 50.
Symbol UART mode tR
USB OTG transceiver
USB OTG transceiver
Description Test conditions Min. Typ. Max. Units
Rise time
CLOAD= [50;100] pF [10; 90] % of VOH-VOL CLOAD= [50;100] pF 10. . ..90% of VOH-VOL CLOAD= [50;100] pF 50% of |VOH-VOL| CLOAD= [50;100] pF 50% of |VOH-VOL|
100
ns
tF
Fall time Drive propagation delay low => high Drive propagation delay high => low
100
ns
tPLH tPHL
100 100
ns ns
USB full speed mode (DP & DN signals) tR tF DRFM OSCV PDEL Rise time Fall time Differential rise an fall time matching Output signal crossover voltage Propagation delay USBVP & USBVM : - Trise & Tfall < 1 ns - Skew < 0.66 ns 4 4 90 1.3 20 20 111 2 18 ns ns % V ns
USB low speed mode (DP & DN signals) tR tF DRFM OSCV Rise time Fall time Differential rise an fall time matching Output signal crossover voltage 75 75 80 1.3 300 300 125 2 ns ns % V
VBUS comparators VBAT tRR tFR Input power supply Rising reacting time Fall reacting time Battery voltage 3.1 3.6 1.7 2.1 4.8 V s s
Threshold VBUS monitoring VBval VBses VBUS valid VBUS session valid 4 .4 1.8 4.5 4.6 2 V V
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Electrical and timing characteristics Table 50.
Symbol VBUS RA_BUS_IN TA_VBUS_
RISE
STw4810
USB OTG transceiver (continued)
Description Test conditions Min. Typ. Max. Units
40 VBUS = [0; 4.4] V ILOAD
= 100mA
100 100
k ms
External cap 10F
Data line pull-down resistance RPD_DPDN Data line pull-up resistance RPU_DP RPU_DN Pull-down on VBUS RVBUS_PD Pull-up on VBUS RVBUS_SRP ID VID_GND VID_HI (VBAT) VID_FLOAT RPU_ID RPD_ID Carkit threshold detection cR_INT Transceiver VOH_TXD_DAT VOL_TXD_DAT VIH_RXD_DAT VIL_RXD_DAT TXD output high on DN ISOURCE = 500 A TXD output low on DN RXD input high on DP RXD input low on DP ISINK = 2mA 2 0.8 2 .4 3.6 0.4 V V V V Carkit interrupt threshold 0.4 0.6 V ID_GND comparator threshold Battery level ID_FLOAT comparator threshold 70 2.7 V < VBAT < 4.8 V 2 .7 0.15*VBAT 3.6 0.85*VBAT 100 130 10 4.8 V V V k k 420 600 780 650 925 1200 Bus idle Bus driven Bus idle Bus driven 900 1425 900 1425 1200 2300 1200 2300 1600 3100 1600 3100 14 19 25 k
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STw4810 Table 50.
Symbol Charge pump VBAT VBUS Input power supply Output voltage Battery voltage Current load up to 100 mA [0;4.8] V) Ext. load: 100 mA + External cap = 10F No Load
Electrical and timing characteristics USB OTG transceiver (continued)
Description Test conditions Min. Typ. Max. Units
VUSB+0.1 4.75
3.6 5
4.8 5.25
V V
tS IQ VRipple IOUT
Settling time Quiescent current
1.2 2.7 25 40 100
ms mA mV mV mA % %
Amplitude output ripple Current load 8 mA on VBUS Current load 100mA Output current VBAT = 3.0V IOUT =100mA VBAT= 3.6V. IOUT = 8 mA.
85 60
Eff
Efficiency
VUSB regulator VBAT(1) Input voltage Battery voltage: VBAT min = VOUT + 0.1V VBAT min= VOUT + 0.1V VUSB+0.1 3.6 5.5 V
VOUT ISHORT IQ PSRR(2) NVOUT LIRT tS tD
Output voltage Short circuit current limitation Quiescent current Power supply rejection Output noise voltage Transient line regulation Settling time OFF->ON Discharge time ON>OFF
3.0
3.1
3.2 320
V mA A dB
No load VBAT= VOUT+0.2V f < 20 kHz VBAT= VOUT+0.2V 10Hz
70
Vrms mV s s
1. From 4.8 V to 5.5 V, charge pump is "Off" and no OTG feature is provided 2. Guaranteed by design
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Electrical and timing characteristics
STw4810
5.6
SD/MMC card interface
Table 51.
Symbol
SD/MMC card interface
Description Test conditions Min. Typ. Max. Units
VMMC regulator specifications (PDN_VMMC = 1) VBAT Input voltage VOUT = 3 V VOUT = 2.85 V VOUT = 1.8 V 3.25 3.1 2.7 -3 % 3.6 3 2.85 1.8 4.8 V
VOUT IOUT ISHORT IQ ILKG PSRR(1)
Output voltage Output current Shor t circuit current limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation Settling time OFF->ON Discharge time ON>OFF IOUT = 0 mA PDN_VMMC = 0 IOUT = 150 mA Vpp = 0.3 V f < 20 kHz VOUT=2.85 V VBAT: [3.1; 4.8]V VOUT=2.85 V IOUT= [1; 150] mA VOUT=2.85 V VBAT: 3.1 to 3.4V tR = tF = 10 s. IOUT = [1; 150] mA tR = tF = 1 s IOUT = 0 mA IOUT = 0 mA
+3% 150
V mA mA A A
280
360
600 30 1
45
dB
LIR(1) LDR(1)
5 10
mV mV
LIRT
2
mV
LDRT tS tD
25 100 1
mV s ms
Bus line specifications RA(2) RB Pull-up resistor Pull-down resistor Clock frequency data transfert mode To prevent bus floating To prevent bus floating With CL = 30pF 1.5 1.5 M M
fDT
52
MHz
fI D
Clock frequency With CL = 30pF identification mode
400
KHz
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STw4810 Table 51.
Symbol TPHC TPCH
Electrical and timing characteristics SD/MMC card interface (continued)
Description Propagation time from Host to card Propagation time from card to host Clock /data skew time from host to card Clock /data skew time from card to host Rise time Fall time Between multimedia processor & STw4810 Bus line capacitance f < 52 Mhz Test conditions Min. Typ. 7 7 Max. Units ns ns
Figure 14 Figure 14 Figure 14 Reference is CLKOUT Figure 14 Reference is MMCLK
TSHC
+/- 0.5
ns
TSCH TR TF
+/- 0.5 3 3
ns ns ns
C1LINE
20(3)
pF
C2LINE
Bus line Between STw4810 capacitance & MMC card f < 52 MHz
20 + 20(4)
pF
1. Guaranteed by design 2. MMC interface pull up resistors are in EMIF06-HCM01F2 device (7 K for CMD; 75 K for Data wires) 3. 20 pF for equivalent board parasitic capacitance. 4. 20 pF for EMIF06 protection + 20 pF for board parasitic capacitance.
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Electrical and timing characteristics Figure 14. Propagation and clock/data skew times
2 ns
MCCLK MCCMD MCDATA[3:0] MCFBCLK CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK 90% 10% 90% 50% 10% 2 ns
STw4810
2 ns
90% 50%
TSHC
TPHC
t
MCCLK 10%
CLKOUT
50% MCDATA[3:0] DATAOUT[3:0]
TPHC 2 ns
CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK MCCLK MCCMD MCDATA[3:0] MCFBCLK 90% 10% 90% 50% 10% 2 ns
t
2 ns
90% 50%
TSCH
TPCH
t
CLKOUT 10%
MCCLK
50% DATAOUT[3:0] MCDATA[3:0]
TPCH
t
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STw4810
Application information
6
6.1
Table 52.
Name C1
Application information
Components list
Components list
Typical value 22F Comments Function VIO_VMEM output filter VCORE output filter VBAT_VIOVMEM decoupling 10F In the complete system application, the sum of the capacitors connected on each STw4810 ball must never be less than 30% of the value indicated in the typical value column of this table. This includes all capacitor parameters: production dispersion DC bias voltage applied temperature range of the complete system application aging VBAT_ANA decoupling VBAT_VCORE decoupling VPLL output filter VANA output filter VREF output filter VUSB output filter VAUX output filter Flying capacitor for charge pump VBUS output filter (tank charge pump capacitor) VSD_MMC output filter Vbattery input voltage decoupling capacitors Coil VIOVMEM DC/DC 4.7H See Table 53 for recommended coils Coil VCORE DC/DC
C4 C2 C3 C5 C6 C7 C8 C10 C13 C9 C11 C12 C13, C14, C15, C16, C17 L1 L2 470nF 4.7F 2.2F 1 F 1F
Table 53.
Supplier
Recommended coils
Part Number VLF3010AT-4R7MR70 DCR () 0.28 0.16 0.14 0.15 0.32 0.19 Irms(1) (A) 0.7 0.74 1.1 1.1 1.1 1.1 L x l x h (mm * mm * mm) 2.8 * 2.6 * 1.0 2.8 * 2.6 * 1.2 3.7 * 3.5 * 1.2 5.5 * 4.2 * 1.8 3.3 * 3.3 * 1.4 3.2 * 2.5 * 2.0
TDK
VLF3012AT-4R7MR74 VLF4012AT-4R7M1R1 DO1605T-472MX
Coilcraft
DO3314-472ML ME3320-472MX
1. Irms: 30% decrease of initial value
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Application information Table 54. Other ST components
Name EMIF02 EMIF06 Order code EMIF02USB05 EMIF06-HMC01F2 Function USB ESD/EMI Protection
STw4810
MMC Interface ESD/EMI Protection
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Application information
6.2
Application schematics
Figure 15. STw4810 application schematics
C1 L1 C2 Modem & system clock VBAT_DIG VMINUS_DIG PON CLK32Kin MASTER_CLK IT_WAKE_UP REQUEST_MC TCXO_EN B9 D3 VLX_VIOVMEM VMINUS_VIOVMEM VBAT_VIOVMEM VIOVMEM_FB C13(*) C3 VMINUS_ANA VBAT_ANA C4 L2
C5 VBAT_VCORE VLX_VCORE
VMINUS_VCORE
VCORE
C14(*) VBAT_VPLL_VANA C6 VPLL VANA C7 C8 VREF C15(*) VBAT_VAUX C1 3 VAUX C16(*)
PWREN VDDOK PORn CLK32K SW_RESETn SCL SDA Multimedia processor USBVP USBOEn USBVM USBRCV USBINTn USBSCL USBSDA MCCLK MCFBCLK M CCM DDIR M CCM D MCDAT0DIR MCDAT0 MCDAT31DIR MCDAT[3,1] MCDAT2DIR MCDAT2
VBAT_USB VMINUS_USB CP CN C10 C11 C9
STw4810
VUSB VBUS ID USB SD MMC EMI Filter SDIO CARD ESD DP DN EMI filter C1 7
( *)
R1 R1
EMIF02
VBAT_MMC VMMC
C12
3
DATOUT[3:1] DATAOUT0 CMDOUT CLKOUT LATCHCLK
3
GPO1 GPO2 (*) The usefulness of these capacitors depend of PCB layout
EMIF06-HMC01F2
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Package mechanical data
STw4810
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
7.1
TFBGA 84 balls
See Figure 16: TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing. Table 55. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions(1) Min. Typ. Max.
1.16 0.20 0.25 0.82 0 .2 5 5 .9 0 0.30 6.00 4.50 5 .9 0 6.00 4.50 0 .4 5 0 .6 5 0.50 0.75 0 .5 5 0 .8 5 0.08 6 .1 0 0 .3 5 6 .1 0 0.30
Drawing dimensions (mm)
A A1 A2 b D D1 E E1 e f ddd
1. These measurements conform to JEDEC standards
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STw4810
Package mechanical data Figure 16. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing
Note:
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.
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Package mechanical data
STw4810
7.2
VFBGA 84 balls
See Figure 17: VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing. Table 56. VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch(1) Min. Typ. Max.
0.864 0.15 0.19 0.615 0.18 0.435 0 .2 1 4 .5 5 0.25 4.60 3.60 4 .5 5 4.60 3.60 0.40 0.50 0.08 0.13 0.04 4 .6 5 0 .2 9 4 .6 5 0.23
Drawing dimensions (mm)
A A1 A2 A3 A4 b D D1 E E1 e f ddd eee fff
1. These measurements conform to JEDEC standards
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STw4810
Package mechanical data Figure 17. VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing
Note:
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.
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Ordering information
STw4810
8
Ordering information
Table 57. Order codes
Package TFBGA84- 6x 6 x 1.2 mm / 0.5 mm pitch TFBGA84- 6x 6 x 1.2 mm / 0.5 mm pitch VFBGA 84 - 4.6x 4.6 x 1 mm / 0.4 mm pitch VFBGA 84 - 4.6x 4.6 x 1 mm / 0.4 mm pitch Tray Tape and reel Tray Tape and reel Packing
Part number STw4810CHDR/LF STw4810CHDT/LF STw4810CRAE/LF STw4810CRAT/LF
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STw4810
Revision history
9
Revision history
Table 58.
Date 24-Jan-2006
Document revision history
Revision 1 Initial release. Modified document title. Reviewed list of applications on cover page. Replaced APE with multimedia processor. Replaced fuse with analogue function. Renamed VFUSE as VANA. Modified figure 6 - Control interface - I2C format Correction of Figure 13: SD MMC block diagram. Correction of Figure 15: STw4810 application schematics. Correction in Section 4.2.3: Sleep mode on page 18 Removed formula and some text about sleep mode. Table 26: Power control register at address 09h on page 31 Replaced bit 2 and 1 with "not used" and "reserved". Update short circuit current limit in Table 38: VCORE DC/DC stepdown converter, Table 39: VIO_VMEM DC/DC step-down converter. Updated short circuit minimum value in Table 42: LDO regulators VAUX and Table 51: SD/MMC card interface Updated the ordering information. 6 Corrected VBAT maximum value in Table 36: Operating conditions (Temp range: -30 to +85 C). Updated Figure 3: Start-up timing and replaced all TBD references with values in Table 46, Table 47, Table 48, Table 49. Replaced ESD performance with VESD in Table 34. Updated the minimum ESD CDM value and removed the maximum junction temperature and maximum power dissipation temperature in Table 34: STw4810 absolute maximum ratings. Updated Section 4.3.9: Thermal shut-down. Changes
07-Feb-2006
2
09-Feb-2006
3
10-Mar-2006
4
25-Jul-2006 5 30-Nov-2006 15-Mar-2007
23-Apr-2007
7
08-Jun-2007 03-Sep-2007
8 9
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