ESDALC6V1M3
Dual low capacitance TransilTM array for ESD protection
Features
2 unidirectional, low capacitance Transil diodes Better than IEC 61000-4-2 standard (ESD protection: 11 kV contact discharge) Breakdown Voltage VBR = 6.1 V min Low diode capacitance (11 pF typ at 0 V) Low leakage current < 0.5 A Very small PCB area: 0.6 mm² RoHS compliant Figure 1. Functional diagram
I/O2 2 1 1 22 I/O1
SOT883 (JEDEC MO-236AA compliant)
Benefits
High ESD protection level High integration Suitable for high density boards
Complies with the following standards
GND 3 GND
IEC61000-4-2 level 4: 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883G-Method 3015-7: class 3B HBM (human body model)
Underside view
Description
The ESDALC6V1M3 is a monolithic array designed to protect 1 line or 2 lines against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required.
Appl ication s
Where transient overvoltage protection in ESD sensitive equipment is required, such as:
Computers Printers Communication systems Cellular phone handsets and accessories Video equipment
TM: Transil is a trademark of STMicroelectronics
February 2008
Rev 4
1/11
www.st.com
Characteristics
ESDALC6V1M3
1
Characteristics
Table 1.
Symbol VPP PPP Ip p Tj Tstg TL TOP ESD discharge
Absolute ratings (Tamb = 25 C - limiting values)
Parameter IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Tj initial = Tamb Value 15 11 30 3 125 -55 + 150 260 -40 + 125 Unit kV W A C C C C
Peak pulse power dissipation (8/20 s)(1) Repetitive peak pulse current (8/20 s) Junction temperature Storage temperature range
Maximum lead temperature for soldering during 10 s Operating temperature range
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Table 2.
Symbol VRM VBR VCL IRM IPP T VF Parameter VBR IRM Rd T C
Electrical characteristics (Tamb = 25 C)
Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current @ VRM Peak pulse current
Slope= 1/ Rd VCL VBR VRM I RM IR VF V I
IF
Voltage temperature coefficient Forward voltage drop Test condition IR = 1 mA VRM = 5 V 1.1 IR = 1 mA VR = 0 V, F = 1 MHz, VOSC = 30 mV 11 Min 6.1 Typ
I PP
Max 7.2 0.5
Unit V A
4.2
10-4/C pF
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ESDALC6V1M3
Characteristics
Figure 2.
dB
0.00
S21 attenuation measurement results of each channel
Figure 3.
0.00
Analog crosstalk measurements between channels
- 30.00
- 10.00
- 20.00
- 60.00
- 30.00
- 90.00
F (Hz)
- 40.00 100.0k
- 120.00
F (Hz)
1.0G
100.0k 1.0M Xtalk 10.0M 100.0M 1.0G
1.0M Att 1
10.0M
100.0M
Figure 4.
ESD response to IEC61000-4-2 (+15 kV air discharge) on each channel
Figure 5.
ESD response to IEC61000-4-2 (-15 kV air discharge) on each channel.
Figure 6.
Relative variation of peak pulse power versus initial junction temperature
Figure 7.
Peak pulse power versus exponential pulse duration
PPP[Tj initial] /PPP[Tj initial=25C] 1.1
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 Tj(C)
PPP(W)
1000 Tj initial = 25 C
100
tP (s) 10 1 10 100
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Ordering information scheme
ESDALC6V1M3
Figure 8.
Clamping voltage versus peak pulse current (typical values)
Figure 9.
Forward voltage drop versus peak forward current (typical values)
IPP(A)
100.0 8/20 s Tj initial =25 C 1.E+00
IFM(A)
10.0
1.E-01
Tj =125C Tj=25C
1.0
1.E-02
VCL(V)
0.1 0 10 20 30 40 50 60 70 1.E-03 0.0 0.2 0.4 0.6 0.8
V(V)
1.0 1.2 1.4 1.6 1.8 2.0
Figure 10. Junction capacitance versus reverse voltage applied (typical values)
C(pF)
12 11 10 9 8 7 6 5 4 3 2 1 0
F=1 MHz VOSC = 30 mVRMS Tj = 25 C
Figure 11. Relative variation of leakage current versus junction temperature (typical values)
IR[Tj] / I R[T j =25 C]
100
V R = 3V
10
VLINE (V)
1
Tj(C) 25 50 75 100 125
0
1
2
3
4
5
6
2
Ordering information scheme
Figure 12. Ordering information scheme
ESDA LC 6V1 M3
ESD array Low capacitance Breakdown voltage 6V1 = 6.1 Volts min. Package M3 = SOT883
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ESDALC6V1M3
Package information
3
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. SOT883 dimensions
Dimensions
E
Ref.
D
Millimetres Min Typ Max 0.52 0.05 0.15 0.50 0.60 1.00 0.35 0.65 0.20 0.20 0.25 0.25 0.30 0.30 0.08 0.08 0.20 0.55 Min 0.18 0.00 0.04 0.18
Inches Typ Max 0.2 0.02 0.06 0.20 0.24 0.39 0.14 0.26 0.10 0.10 0.12 0.12 0.08 0.22
A A1
A A1 L b e
1 2
0.45 0.00 0.10 0.45
b b1 D E
L1
3
b1
e e1
e1
L L1
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 13. Footprint Figure 14. Marking
0.40
0.40
2
0.20 0.25 0.70
K
1
3
0.30
All dimensions in mm
5/11
Package information Figure 15. Packing information
Cathode bar
ESDALC6V1M3
2.0 0.05 0.20 0.05
4.0 0.1
Ø 1.55 0.05
1.75 0.1
1.10 0.05
K K
3.5 - 0.05
0.66 0.05 (C-PAK) 0.55 0.1 (3M)
All dimensions in mm
8.0 0.3
0.68 0.05
User direction of unreeling
K
K
K
2.0 0.1
K
K
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ESDALC6V1M3
Recommendation on PCB assembly
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 16. Stencil opening dimensions
L
T
W
b)
General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T L× W Aspect Area = --------------------------- 0.66 2T(L + W)
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for leads: Opening to footprint ratio 90%.
Figure 17. Recommended stencil window position
400 m 7 m 236 m
T=100 m
380 m 7 m
10 m
10 m
0.4
0.4
10 m
10 m 18 m
0.20 0.25
0.70
0.30 700 m 664 m
Footprint
380 m 18 m 400 m Stencil window Footprint
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Recommendation on PCB assembly
ESDALC6V1M3
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-45 m.
4.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
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ESDALC6V1M3
Recommendation on PCB assembly
4.5
Reflow profile
Figure 18. ST Ecopack recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
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Ordering information
ESDALC6V1M3
5
Ordering information
Table 4. Ordering information
Marking K(1) Package SOT883 Weight 0.96 mg Base qty 3000 Delivery mode Tape and reel
Order code ESDALC6V1M3
1. The marking can be rotated by 90 to differentiate assembly location
6
Revision history
Table 5.
Da te 04-Aug-2005 23-May-2006 16-Jun-2006
Document revision history
Revision 1 2 3 Initial release. Reformated to current standards. Added soldering reflow profile diagram. Updated tape and reel illustration (Figure 14). Reformatted to current standards. Added notes on marking rotation. Updated tape and reel illustration - Figure 15. Added Section 4: Recommendation on PCB assembly. Updated footprint in Figure 13. Cha nge s
18-Feb-2007
4
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ESDALC6V1M3
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