Datasheets | Application Specific for Computer and Peripherals | Customizable Processors for Computer & Peripherals | Customizable Application Processors

Ethernet Communication Controller with USB-Host

Datasheet

Format: (1556 kb)

Last Updated: 09/05/2006

Pages: 194

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SPEAR-07-NC03
Ethernet Communication Controller with USB-Host
Features

Based on ARM720T (8K Caches and MMU included) Support a 10/100 Mbits/s Ethernet connection (IEEE802.3) Full-Speed USB Host Controller, supports 12Mbit/s Full Speed Devices UART Interface: 115KBaud I2C interface: Fast and Slow. IEEE1284 Host Controller Real Time Clock Timers and Watchdog peripherals Integrated PLL (25MHz Input, 48MHz Output) Up to 12 GPIOs (including IEEE1284 port) 8K SRAM shared with an External Microprocessor Static Memory Controller (up to 2 Banks, Max 16M each)
LFBGA180 (12x12x1.7mm)

DRAM Controller SDRAM/EDO (up to 4 Banks, Max 32M each) External I/O Banks: 2 x 16KB. Package LFBGA 180 (12x12mm x1.7mm)

Description
SPEAR-07-NC03 is a smart Communication Controller for USB and Ethernet Communication. SPEAR-07-NC03 allows the sharing of a FullSpeed USB or IEEE1284 or a UART Peripherals inside an Ethernet System. SPEAR-07-NC03 is supported Operation Systems such as eCOS. by several

Order codes
Part number SPEAR-07-NC03 Op. Temp. range, C -40 to +105 Package LFBGA180 Packing Tray

May 2006

Rev 5

1/194
www.st.com 1

Table of Contents

SPEAR-07-NC03

Table of Contents
1 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ARM720T RISC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 IEEE802.3/Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 GPIO (Programmable I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IEEE1284 Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Shared SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 4

Top-level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 Functional Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PAD Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 5.2 Global MAP (AHB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I/O MAP (APB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6

Blocks description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 CPU SUBSYSTEM & AMBA BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6

Table of Contents

ARM720 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MMU Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Instruction and Data Cache overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Write Buffer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Coprocessor Registers Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.2

MAC Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Transfer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ethernet register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Programming the DMA MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3

Full-Speed USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Host Controller Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Initialization of the HCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Operational States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Operational Registers Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4

IEEE1284 Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Communication modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Matrix of Protocol Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Register MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 IEEE1284 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Parallel Port register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.5

UART Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.5.1 6.5.2 6.5.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.6

I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.6.1 6.6.2 6.6.3 6.6.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 I2C Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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Table of Contents

SPEAR-07-NC03 Dynamic Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Memor y Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Address Mapping Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Register MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

6.7

6.8

Static Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.8.1 6.8.2 SRAMC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Registers Map and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

6.9

Shared SRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.9.1 6.9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 External Processor Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

6.10

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.10.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.10.3 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

6.11

RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.11.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.11.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.12

Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.12.2 Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.12.3 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.13

Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.13.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.13.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

6.14

Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.14.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.14.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.14.4 Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.15

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

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Table of Contents

6.15.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.15.3 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

6.16 6.17

RESET and Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

PLL (Frequency synthesizer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 6.17.2 Global Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 6.17.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 6.17.4 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
7.1 7.2 7.3 7.4 7.5 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.3.1 POWERGOOD timing requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

AC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 External Memory Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.5.1 7.5.2 Timings for External CPU writing access . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Timings for External CPU reading access . . . . . . . . . . . . . . . . . . . . . . . . . . 190

8 9 10

Reference Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

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List of tables

SPEAR-07-NC03

List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Pin Descriptions by Functional Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Description by PAD Types (*LH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PAD Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AHB Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 APB Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MRC and MCR (CP15) bit pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TTB Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DAC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 TLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ethernet register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 USB Host Controller Operational Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 IEEE1284 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DRAM Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Memory Bank Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Bank size field and its corresponding actual size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Register MAP and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Pin mapping for IEEE1284 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Pin mapping for JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Pin mapping for nUSB_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Pin mapping for nI2C_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Core power consumption (VDD = 1.8V, TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Expected timings for external CPU writing access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Expected timings for external CPU reading access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

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List of figures

List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. SPEAr Net Top level Bock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARM720T Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ethernet Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ethernet Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 IEEE802.3 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 DMA Descriptor chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 USB Host Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 USB Focus Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 IEEE1284 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 IEEE1284 - DMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SDRAM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SDRAM Access Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 EDO Access Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Shared SRAM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SPEAr Net Write Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SPEAr Net Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Timer/Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Watch-Dog Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 GPIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 POWERGOOD requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 External CPU writing timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 External CPU reading timingss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 LFBGA180 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

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1 Product overview

SPEAR-07-NC03

1
1.1

Product overview
Overview
The SPEAR-07-NC03 is based on ARM720T RISC core, cache and MMU. It provide a bridge between four different I/F : 1. IEEE802.3/Ethernet MAC core for network interface. Its base interface with PHY (physical layer) chip is capable of 10/100 Mbps MII (Medium Independent Interface) and 7-wire interface. USB host controller with both interrupt-based and DMA-based data handling method. IEEE1284 host controller offering Compatibility mode, Nibble mode and ECP mode. Shared RAM (Mail box method) for communication with other processors. I2C master controller.

2. 3. 4. 5.

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2 Features

2
2.1

Features
Architecture

Integrated System For Ethernet Application 48MHz, 3.3V I/O and 1.8V Internal Core Voltage ARM720T RISC Processor Core AMBA Rev. 2.0 System Bus Architecture IEEE802.3/Ethernet Compliant MAC Core USB Interface Solution (Host) IEEE1284 Interface Solution (Master)

2.2

ARM720T RISC Processor

ARM7TDMI RISC Core 8KB Unified Instruction/Data Cache Enlarged Write Buffer (8 words and 4 different addresses) Vir tual Address Support with MMU

2.3

External Memory Interface

16bit/8bit Memory Bus Support ROM/SRAM/Flash Static Memory Controller SDRAM/EDO DRAM Controller External I/O Bank Controller Independent Configurable Memory and I/O Banks Replaceable Memory and I/O Bank Addresses

2.4

IEEE802.3/Ethernet MAC

10/100 MAC, MAC Host block, Station Management block, Address Compliant with IEEE 802.3 and 802.3u specifications Suppor ts 10/100 Mb/s data transfer rates IEEE 802.3 Media Independent Interface (MII) Suppor ts full and half duplex operations Check block and the Control Status Register (CSR) block

2.5

DMA Controller

Dedicated Channels for MAC core, USB Host and IEEE1284 interface 2 Channels general purpose DMA (Memory To Memory)

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2 Features

SPEAR-07-NC03
2 Channels general purpose DMA dedicated to the external requests (I/O to Memory and Memory to I/O) Increments/Decrements of Source/Destination Address In 16/8bit(external), 32/16/ 8(internal) Data Transfers Burst Transfer Mode

2.6

UART

Suppor t For 8-Bit Serial Data Tx And Rx Selectable 2/1 Stop Bits Selectable Even, Odd and No Parity Parity, Overrun And Framing Error Detection Max Transfer rate:115KBaude

2.7

Timers

Channel Programmable 16-Bit Timers with 8 bit pre-scaler

2.8

Watchdog Timer

For Recovery from Unexpected System Hang-up One Programmable 16-Bit Watchdog Timer With Reset Output Signal (more than 200 system clock period to initial peripheral devices) Programmable period 1 ~ 10 sec

2.9

GPIO (Programmable I/O)

4 Dedicated Programmable I/O Ports (Pins) 2 Multiplexed Pins with I2C Bus Signals Pins Individually Configurable To Input, Output Or I/O Mode

2.10

Interrupt Controller

2 External Interrupt Sources Support 9 Internal interrupt sources. All channels can be individually rerouted to the Fast (nFIQ) or to the Normal (nIRQ) processor lines Level and edge (rise, fall and both) selectable Software Controlled Priority

2.11

IEEE1284 Host Controller

Compatibility/Nibble/ECP/EPP Mode Host Support

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2 Features

DMA-based Data Transfer Capability for ECP Fully Software Controllable Operation Mode

2.12

USB Host Controller

Full-Speed USB compliant Suppor ts Low Speed and Full Speed Devices Configuration data stored in Port Configurable Block Single 48 MHz input clock Integrated Digital PLL

2.13

Shared SRAM

External Processor Communication Purpose Shared SRAM Bus Arbiter Same address can be accessed at the same time Separated from AHB Bus for Bus Traffic Reduce Interrupt Output Generation for Transfer Notification

2.14

Real Time Clock

Real time clock-calendar (RTC) Clocked by 32.768MHz low power clock input Separated power supply (1.8 V) 14 digits (YYYY MM DD hh mm ss) precision

2.15

Frequency Synthesizer

On-chip Frequency Synthesizer Provided F in : 25 MHz. Fout: 48 MHz

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3 Top-level Block Diagram

SPEAR-07-NC03

3
Figure 1.

Top-level Block Diagram
SPEAr Net Top level Bock Diagram

ARM720T Microprocessor Core & MMU WRAPPER FROM CPU TO AMBA

8 KByte cache (Instr & Data)

MII & 7-wire PHY Interface

MAC110 IEEE802.3/Ethernet MAC Contr. + DMA

AHB Decoder & Arbiter, APB Bridge, MUX Master to Slave, MUX Slave to Master External Memory BUS

ROM/FLASH 2 Banks

USB Interface

USB HOST HOST Contr. + DMA M1284H IEEE1284 Host Contr. + DMA DMA Controller
2 Memory to Memory 2 I/OToMem & MemToI/O

DRAMC SDRAM/EDO DRAM Controller

SRAM/EDO 4 Banks

IEEE1284 Inter face

I/O AHB & APB SRAMC ROM/FLASH/SRAM External I/O Controller 2 Banks

nDREQ[1:0] nDACK[1:0]

nIRQ[1:0]

INTC Interrupt Controller (16 ch) TIMER (2 channels)

Shared SRAM Bus Arbiter text

Ext Bus

External Processor

SPEAr Net
8KB Shared SRAM

32 KHz

RT C

XPAddr[12:0] XPData[15:0] nXPCS nXPWE nXPRE nXPWAIT nXPIRQ

GPIO (6 channels) M I2 C I2C Controller

PLL Frequency Synthesizer

25 MHz
PowerGood nResetOut

RESET CONTROLLER
WDT Watch-dog Timer

TX RX

UART (1 channel)

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4 Pin Descriptions

4
4.1
Note: Table 1.

Pin Descriptions
Functional Pin Groups
Note: symbol / means multiplexing modes Pin Descriptions by Functional Groups
Pin Name MCLKI MCLKO Function Oscillator Clock Input Oscillator Clock Output System Reset Input Peripheral Chips Driving Reset Output Test Mode Selector Output Clock (25 MHz) Address Bus Add[10]/AP is the auto pre-charge control pin. The auto pre-charge command is issued at the same time as burst read or burst write by asserting high on Add[10]/ AP External, Bi-directional, 16 bit Data Bus Row Address Strobe for EDO DRAM/ nSDCS is chip select pin for SDRAM Row Address Strobe for SDRAM Column Address Strobe for SDRAM System Clock for SDRAM Clock enable signal for SDRAM Write Enable for external devices. Chip Select for external I/O Bank Not ROM/SRAM/FLASH Chip Select Not Output Enable for memory I/O Banks size: 16KB 48 MHz Synchronous with System Clock "1" Test 25 MHz 25 MHz Remark

Group

Clocks, Reset and configuration.

PowerGood nResetOut TMODE0 PCLK

Add[22:11], Add[10]/AP, Add[9:0]

ROM Banks: 16MB Max. DRAM Banks: 32MB Max.

Data[15:0] nRAS[3:0]/ nSDCS[3:0] nSDRAS Memory Interface nSDCAS SDCLK CKE nWE nECS[1:0] nRCS[1:0] nOE

nCAS is the Column Address Strobe for nCAS[1:0]/ DQM[1:0] EDO DQM is data mask signal for SDRAM.

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4 Pin Descriptions

SPEAR-07-NC03

Table 1.
Group

Pin Descriptions by Functional Groups (continued)
Pin Name MDC MDIO COL/ COL_10M TX_CLK/ TXCLK_10M TXD[3:0]/ TXD_10M/ LOOP_10M Function Management Data Clock Management Data I/O Collision detected/collision detected for 10Mbps Transmit clock/ transmit clock for 10Mbps Remark

Transmit data/ transmit data for 10Mbps Transmit enable/transmit enable for 10Mbps Carrier sense/carrier sense for 10Mbps Receive clock/receive clock for 10Mbps Receive data/receive data for 10Mbps Receive data valid Receive error Function UART receive data UART transmit data Test Clock Input Test Data Input Test Data Output Test Mode select Input Test Reset Line General Purpose I/O #5 and #4/ I2C Bus Controller SDA, SCL Serial Clock line Serial Data line Remark

Ethernet Controller

TX_EN/ TXEN_10M CRS/ CRS_10M RX_CLK/ RXCLK_10M RXD[3:0]/ RXD_10M RX_DV/ LINK_10M RX_ERR

Group UART

Pin Name RXData TXData TCK TDI

JTAG Interface

TDO TMS TRST

GPI/O

GPI/O[5:0] SCL SDA

I2C Interface

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Table 1.
Group

4 Pin Descriptions

Pin Descriptions by Functional Groups (continued)
Pin Name XPData[15:0] XPAddr[12:0] nXPCS Function External Processor Data Bus High Byte External Processor Address Bus Shared SRAM CS from External Processor Shared SRAM Write Strobe from Ext. Proc. Shared SRAM Read Strobe from Ext. Proc. Wait Signal to External Processor Interrupt Request to External Processor USB Host differential Data signal high side USB Host differential Data signal low side Data Lines to/from peripheral Strobe Line to peripheral Ack line from peripheral Busy line from peripheral Paper Error line from peripheral Selection feedback from peripheral Auto Feed signal to peripheral Generic error line from peripheral Init (Reset) line to peripheral Select signal to peripheral Direction control for external transceiver RTC Oscillator Input line RTC Oscillator Output line External Interrupt request lines External request lines for DMA External Acknowledge lines from DMA DRAM type selection USB Transceiver Enable or Disable Pull-Up SDRAMM Pull-up Enabled 32.768 KHz 32.768 KHz Remark

External Processor Interface

nXPWE nXPRE nXPWAIT nXPIRQ

USB

UHD+ UHDPpData[7:0] nSTROBE nACK Busy PError

IEEE1284

Select nAutoFD nFault nInit nSelectIn PpDataDir

RTC

RTCXI RTCXO nXIRQ[1:0]

MISC.

nXDRQ[1:0] nXDACK[1:0] Sdram/EDO USBEnable

Configuration

IEEE1284/ XProcessor BootRomBusWidth UART/JTAG GenConf[2:0] VDD_Core

IEEE1284 or External Processor selection Pull-up IEEE1284 Bus Width Selection for Rom 0 Debug interface selection General purpose Configuration lines Internal Logic Core VDD (1.8V 5%) I/O Pad VDD (3.3V 5%) RTC VDD (1.8V 5%) Ground Pull-up 16 bits Pull-up UART

Power

VDD_I/O VDD_RTC GND

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4 Pin Descriptions

SPEAR-07-NC03

4.2
Table 2.
Ref. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

PAD Types
Pin Description by PAD Types (*LH)
Ball B1 C1 F2 E4 D1 E3 F5 G4 G2 G1 G5 H4 H5 H1 H3 J4 J5 J2 J3 K5 K2 L1 K4 L2 M1 N1 M3 N2 P1 P3 N4 P4 N5 MCLKI MCLKO PowerGood nRESETOut TMODE0 PCLK Add0 Add1 Add2 Add3 Add4 Add5 Add6 Add7 Add8 Add9 Add10_AP Add11 Add12 Add13 Add14 Add15_GenConf0 Add16_GenConf1 Add17_GenConf2 Add18_UART/JTAG Add19_BootRomBusWidth Add20_IEEE1284/XProcessor Add21_USBEnable Add22_Sdram/EDO Data0 Data1 Data2 Data3 Name ANA OSCI27B SCHMITT_TC B4TR_TC SCHMITT_TC BD4TARP_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC BD8STRP_TC BD8STRP_TC BD8STRP_TC BD8STRP_TC BD8STRP_TC BD8STRP_TC BD8STRP_TC BD8STRP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC Type Dir. I I O I O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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SPEAR-07-NC03
Table 2.
Ref. 34 35 36 37 38 39 40 41 42 Ref. 43 44 45 46 47 48 49 50 51 52 53 Ref. 54 55 56 57 58 59 60 61 62 63 64 65 66 P5 M6 N6 P6 L6 M7 N7 K7 L7 Ball M8 K8 P8 N8 M9 K9 P9 N9 M10 P2 N10 Ball P11 L10 P12 N11 P14 N12 N13 M12 M13 N14 M14 K12 L14

4 Pin Descriptions

Pin Description by PAD Types (*LH) (continued)
Ball Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Name Data13 Data14 Data15 nRAS0_nSDCS0 nRAS1_nSDCS1_TDI nRAS2_nSDCS2_TDO nRAS3_nSDCS3_nTRST nSDRAS nSDCAS SDCLK CKE Name nWE nECS0 nECS1 nRCS0 nRCS1 nOE nCAS0_DQM0 nCAS1_DQM1 MDC MDIO COL/COL10M TXClk/TXClk10M TXD0/TXD010M Name Type BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC Type BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC B4TR_TC BD4STRUQP_TC B4TR_TC BD4STRUQP_TC B4TR_TC B4TR_TC BD4TARP_TC B2TR_TC Type B8TR_TC B4TR_TC B4TR_TC B2TR_TC B2TR_TC B8TR_TC B4TR_TC B4TR_TC B4TR_TC BD4STRUQP_TC SCHMITT_TC SCHMITT_TC B4TR_TC Dir. I/O I/O I/O I/O I/O I/O I/O I/O I/O Dir. I/O I/O I/O O I/O O I/O O O O O Dir. O O O O O O O O O I/O I I O

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4 Pin Descriptions

SPEAR-07-NC03

Table 2.
Ref. 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Ref. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 K13 K14 J12 K10 J13 J14 J10 H13 H11 H14 H10 G11 G10 G14 A3 B4 A2 A1 Ball B3 C3 F10 F14 E10 F12 E14 E13 E1 E2 D14 E11 D13 B14 C13 C12

Pin Description by PAD Types (*LH) (continued)
Ball Name TXD1/TXD110M TXD2/TXD210M TXD3/TXD310M TXEN/TXEN10M CRS/CRS10M RXClk/RXClk10M RXD0/RXD010M RXD1/RXD110M RXD2/RXD210M RXD3/RXD310M RxDV/LINK10M RXERR RXData_TCK TXData_TMS GPIO0 GPIO1 GPIO2 GPIO3 Name GPIO4_SCL GPIO5_SDA nXIRQ0 nXIRQ1 nXDRQ0 nXDRQ1 nXDACK0 nXDACK1 RTCXO RTCXI XPData0_PpData0 XPData1_PpData1 XPData2_PpData2 XPData3_PpData3 XPData4_PpData4 XPData5_PpData5 B4TR_TC B4TR_TC B4TR_TC B4TR_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC BD4STRUQP_TC BD4STRUQP_TC BD4STRUQP_TC BD4STRUQP_TC BD4STRUQP_TC Type BD4STRUQP_TC BD4STRUQP_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC B4TR_TC B4TR_TC ANA OSCI32B BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC Type Dir. O O O O I I I I I I I I I I/O I/O I/O I/O I/O Dir. I/O I/O I I I I O O I I/O I/O I/O I/O I/O I/O

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Table 2.
Ref. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Ref. 128 129 130 131 B13 B12 A13 B11 C10 A11 B10 D10 B9 A9 D9 C9 A8 E8 D8 C8 E7 D7 B7 C7 A6 B6 D6 C6 D5 A5 A4 Ball C5 F11 G13 E6, A12, E12, G12, L13, P10, L8, K6, M5, M2, K1, H2, F4

4 Pin Descriptions

Pin Description by PAD Types (*LH) (continued)
Ball Name XPData6_PpData6 XPData7_PpData7 XPData8 XPData9 XPData10 XPData11 XPData12 XPData13 XPData14 XPData15 XPAddr0_nSTROBE XPAddr1_nACK XPAddr2_Busy XPAddr3_PError XPAddr4_Select XPAddr5_nAutoFd XPAddr6_nFault XPAddr7_nInit XPAddr8_SelectIn XPAddr9_PpDataDir XPAddr10 XPAddr11 XPAddr12 nXPCS nXPWE nXPRE nXPWAIT Name nXPIRQ UHD+ UHDVDD3I/O Type BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD8STRUQP_TC BD2STRUQP_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC BD2STRUQP_TC SCHMITT_TC BD2STRUQP_TC BD2STRUQP_TC BD2STRUQP_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC B4TR_TC Type B4TR_TC USB_PAD USB_PAD Power Dir. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I I/O I/O I/O I I I I I I O Dir. O I/O I/O -

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Table 2.
Ref.

Pin Description by PAD Types (*LH) (continued)
Ball Name Type Dir.

144

D2, G3, J1, K3, N3, L5, P7, L9, P13, K11, H12, C14, F13, A14, A10 F3 E5 B2 C2 F1, J11, E9 B8, A7, B5

VSS

Power

-

459 160 161 162 163 166 169

VDDRTC VSSRTC VDD3PLL VSSPLL VDD VSS

Power Power Power Power Power Power Not Connected

-

-

-

C4, C11, D3, D4, D11, D12, L3, L4, L11, L12, NC M4, M11

Table 3.

PAD Description
Description Analog PAD Buffer TTL Output Pad Buffer, 3 V capable, 2mA drive capability TTL Output Pad Buffer, 3 V capable, 4mA drive capability TTL Output Pad Buffer, 3 V capable, 8mA drive capability TTL Schmitt Trigger Bidirectional Pad Buffer, 2mA drive capability, 3 V Capable, with Pull-Up TTL Schmitt Trigger Bidirectional Pad Buffer, 4mA drive capability, 3 V Capable with Pull-Up TTL Bidirectional Pad Buffer, 3 V capable, 4mA drive capability, Active Slew Rate TTL Schmitt Trigger Bidirectional Pad Buffer, 8mA drive capability, 3 V Capable TTL Schmitt Trigger Bidirectional Pad Buffer, 8mA drive capability, 3 V Capable with Pull-Up Oscillator (Max Frequency 27 MHz) Oscillator (32 KHz) TTL Schmitt Trigger Input Pad Buffer 3 V tolerant USB Transceiver Power Pad - Internal supply for 3.3 V level Power Pad - Internal supply for 1.8 V level Power Pad - Internal ground, for Core only Power Pad - Internal ground

PAD Name ANA B2TR_TC B4TR_TC B8TR_TC BD2STRUQP_TC BD4STRUQP_TC BD4TARP_TC BD8STRP_TC BD8STRUQP_TC OSCI27B OSCI32B SCHMITT_TC USB_PAD VDD3IOCO VDDCO VSSCO VSSIOCO

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5 Memory Map

5
5.1

Memory Map
Global MAP (AHB)
Table 4. AHB Memory Map
End Address Description Two ROM/FLASH/SRAM Banks. Bank size granularity: 64 KB Max Bank size: 16 MB The two banks are adjacent. Four SDRAM/EDO Banks. Max Bank size: 32 MB Bank size granularity: 64 KB The four banks are adjacent. Two External I/O Banks Bank size: 16 KB 8 KB Shared SRAM IEEE1284 Interface & FIFOs ARM Slave Test Interface APB Bridge Starting Address

0x000.0000

0x01FF.FFFF

0x1000.0000

0x17FF.FFFF

0x2000.0000 0x2100.0000 0x2200.0000 0x2300.0000 0x3000.0000

0x2000.7FFF 0x2100.1FFF 0x2200.0BFF 0x2300.03FF 0x3000.37FF

Note:

The decoder will ignore the ADD31 lines. In this way will be possible to access all the devices trough cache in range 0x000.0000 - 0x7FFF.FFFF and without cache in range 0x8000.0000 0xFFFF.FFFF

5.2

I/O MAP (APB)
Table 5. APB Memory Map
End Address 0x3000.03FF 0x3000.07FF 0x3000.0BFF 0x3000.0FFF 0x3000.13FF 0x3000.17FF 0x3000.1BFF 0x3000.1FFF 0x3000.23FF 0x3000.27FF 0x3000.2BFF 0x3000.2FFF 0x3000.33FF 0x3000.37FF Interrupt Controller General Purpose Timers Watch Dog Timer Real Time Clock General Purpose I/O I2C Interface UART Configuration Registers DMA Controller General Purpose Static Memory Controller Dynamic Memory Controller USB Host Controller DMA MAC MAC Ethernet Controller Description Starting Address 0x3000.0000 0x3000.0400 0x3000.0800 0x3000.0C00 0x3000.1000 0x3000.1400 0x3000.1800 0x3000.1C00 0x3000.2000 0x3000.2400 0x3000.2800 0x3000.2C00 0x3000.3000 0x3000.3400

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6
6.1

Blocks description
CPU SUBSYSTEM & AMBA BUS
Figure 2. ARM720T Block Diagram

MMU

8Kb Cache

ARM7TDMI CPU Coprocessor Interface

Data and Address Buffers AMBA Interface AMBA BUS Interface

Control and clocking logic

System Control Coprocessor

6.1.1

ARM720 Processor
The ARM720T is a general purpose 32-bit RISC microprocessor with 8KB cache, enlarged write buffer and Memory Management Unit (MMU) combined in a single chip. The CPU within ARM720T is the ARM7TDMI. The on-chip mixed data and instruction cache, together with the write buffer, substantially raise the average execution speed and reduce the average amount of memory bandwidth required by the processor. The MMU supports a conventional two-level, page-table structure and the memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system.

6.1.2

MMU Overview
The Memory Management MMU performs two primary functions. It: translates virtual addresses into physical addresses controls memory access permissions The MMU hardware required to perform these functions consists of: a Translation Look-aside Buffer (TLB) access control logic translation-table-walking logic When the MMU is turned off (as happens on reset), the virtual address is output directly onto the physical address bus.

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6.1.3

Instruction and Data Cache overview
ARM720T contains an 8KB mixed instruction and data cache (IDC). The cache only operates on a write-through basis with a read-miss allocation policy and a random replacement algorithm. The IDC has 512 lines of 16 bytes (four words), arranged as a 4-way set-associative cache, and uses the virtual addresses generated by the processor core after relocation by the Process Identifier as appropriate. The IDC is always reloaded a line at a time (4 words). It may be enabled or disabled via the ARM720T Control Register and is disabled immediately after the Power-On Reset. The operation of the cache is further controlled by the Cacheable (C bit) stored in the Memory Management Page Table. For this reason, the MMU must be enabled in order to use the IDC. However, the two functions may be enabled simultaneously, with a single write to the Control Register.

6.1.4

Write Buffer Overview
The ARM720T write buffer is provided to improve system performance. It can buffer up to eight words of data, and four independent addresses and may be enabled or disabled via the W bit (bit 3) in the ARM720T Control Register. The buffer is disabled and flushed on reset. The write buffer operation is further controlled by the Bufferable (B) bit, which is stored in the Memory Management Page Tables. For this reason, the MMU must be enabled so you can use the write buffer. The two functions may however be enabled simultaneously, with a single write to the Control Register.

6.1.5

Configuration
The operation and configuration of ARM720T is controlled: directly via coprocessor instructions indirectly via the Memory Management Page tables The coprocessor instructions manipulate a number of on-chip registers which control the configuration of the following: Cache Write buffer MMU A number of other configuration options

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6.1.6

Coprocessor Registers Programming
The ARM720T instruction set allows specialized additional instruction to be implemented using coprocessor. The Memory Unit in the ARM720T core is referred as Coprocessor 15 (CP15).
Important: CP15 registers can only be accessed with MRC and MCR instructions in a Privileged mode. CDP, LDC and STC instructions, as well as unprivileged MRC and MCR instructions to CP15 cause the undefined instruction trap to be taken.

The bit fields of the instruction are shown in the following table:
Table 6. MRC and MCR (CP15) bit pattern

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRn Rd 1 1 1 1 Opcode_2 1 CRm Cond. 1 1 1 0 Opcode_1 L

Symbol

Description

Cond: L:

Condition Code Field Direction

0 Store to Coprocessor (MCR) 1 Load from Coprocessor (MRC) Rd: CRn: CRm: ARM register Coprocessor Register Should be zero except when accessing register 7, 8 and 13.

opcode_1: Should be zero opcode_2: Should be zero except when accessing register 7, 8 and 13.

Note that the CPID field, bit 11:8, is set to 15 (MMU Coprocessor). The assembler syntax is: {cond} p15, opcode_1, Rd, CRn, CRm, opcode_2

6.1.6.1 Registers
Register 0, ID (RO)

It is a read-only register. CRm and opcode_2 should be zero. Reading from this register return always 0x41807203. Last nibble is the revision number.
Register 1, Control (R/W)

CRm and opcode_2 should be zero. The control bits pattern is shown in
Table 7. Control Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNP/SBZ V UNP/SBZ R S B L D P W C A M

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M A C W P D L B S R V UNP/SBZ

MMU enable/disable bit ( 0= disable, 1 = enable) Alignment fault Enable/disable bit (0 = disable, 1 = enable) Cache enable/disable bit (0 = disable, 1 = enable) Write Buffer enable/disable bit (0 = disable, 1 = enable) When read return always 1. When written is ignored. When read return always 1. When written is ignored. When read return always 1. When written is ignored. Endianess bit ( 0 = Little Endian, 1 = Big Endian) System Protection (See Access Permission AP Bits) ROM Protection (See Access Permission Bits) Location of exception vectors (Windows CE) Unpredictable when read, Should Be Zero when written.

Example: ldr r0, =0x0F MCR p15, 0, r0, 1, 0, 0 ; Enable MMU with cache, write buffer and ; alignment fault

Register 2, Translation Table Base (R/W)

CRm and opcode_2 should be zero. This is the currently active first-level translation table. Only bit 31:14 are valid. The others are unpredictable when read, should be zero if written.
Table 8. TTB Register
TranslationTaBle UNP/SBZ

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Register 3, Domain Access Control (R/W)

CRm and opcode_2 should be zero. The Domain Access Control Register consists of 16 2-bit fields, each of which defines the access permissions for one of the 16 Domains (D15-D0). The meaning of this bit is described in the MMU translation mechanism.
Table 9.
D15

DAC Register
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Register 4 (Reserved) Register 5, Fault Status Register (FSR) Register 6, Fault Address Register (FAR) Register 7, Cache Operations (WO)

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For this operation opcode_2 must be 0x0b000 and CRm must be 0x0b0111. This operation invalidates all cache data. Use with caution. Reading from it is undefined. Example: MCR p15, 0, r0, c7, c7, 0 ; invalidate all the data inside cache
Register 8, TLB Operations

Two operation are defined as showed on the following table:
Table 10. TLB Operation
Function Invalidate entire TLB Invalidate TLB (Single entry) Opcode_2 0b000 0b001 CRm 0b0111 0b0111 (Rd) 0 Vir tual Address Assembler Syntax MCR p15, 0, Rd, C8, C7, 0 MCR p15, 0, Rd, C8, C7, 1

The Invalidate TLB invalidates all of the unlocked entries in the TLB. The invalidate TLB single entry invalidates any TLB entry corresponding to the Virtual Address in Rd.
Register 9 to 12 are Reserved Register 13, Oricess Identifier

Not Used
Register 14 to 15 are Reserved

6.2

MAC Ethernet Controller
Figure 3. Ethernet Controller Block Diagram

Local FIFO

MII I/F AHB MASTER
DMA RX & TX LOGIC

DATA MAC BLOCK Configuration M I

APB SLAVE

Configuration Registers Array

M

6.2.1

Overview
The Ethernet Media Access Controller (MAC110) core incorporates the essential protocol requirements for operation of an Ethernet/IEEE 802.3 compliant node, and provides interface between the host subsystem and the Media Independent Interface (MII). The MAC110 core can

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operate either in 100Mbps mode or the 10Mbps mode based on the clock provided on the MII interface (25/2.5 MHz). The MAC110 core operates both in half-duplex mode and full-duplex modes. When operating in the half- duplex mode, the MAC110 core is fully compliant to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard) and ANSI/IEEE 802.3. When operating in the full-duplex mode, the MAC110 core is compliant to the IEEE 802.3x standard for full-duplex operations. It is also compatible with Home PNA 1.1. The MAC110 core provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. These features include ability to disable retires after a collision, dynamic FCS generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, automatic retransmission and detection of collision frames. The MAC110 core can sustain transmission or reception of minimal-sized back -to-back packets at full line speed with an inter-packet gap (IPG) of 90.6 us for 10-Mb/s and 0.96 us for 100-Mb/s. The five primary attributes of the MAC block are: 1. Transmit and receive message data encapsulation Framing (frame boundary delimitation, frame synchronization) Error detection (physical medium transmission errors) 2. Media access management Medium allocation (collision detection, except in full-duplex operation) Contention resolution (collision handling, except in full-duplex operation) 3. Flow Control during Full Duplex mode Decoding of Control frames (PAUSE Command) and disabling the transmitter Generation of Control Frames 4. Interface to the PHY Suppor t of MII protocol to interface with a MII based PHY. 5. Management Interface support on MII Generation of PHY Management frames on the MDC/MDI/MDO. To minimize the CPU load during the data transfer is available a local DMA with FIFO capable to fetch itself the descriptors for the data blocks and to manage the data according to the instruction included on the descriptor.

6.2.2

Transfer Logic

6.2.2.1 RX LOGIC
The receive (RX) DMA block includes all the logic required to manage data transfers from the RX port of the MAC110 wrapper to an external AHB memory mapped device. It includes: RX wrapper interface RX FIFO RX DMA master SM DMA descriptor SM

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6.2.2.2 RX WRAPPER INTERFACE
The wrapper interface is a simple synchronous interface with RX_nREQ, RX_nACK, RX_DATA signals for data handshake, plus some sideband signals for the MAC protocol support (see later). The data path (RX_DATA) is 32 bit wide. When the RX DMA logic has been enabled, after a valid descriptor fetch, the RX interface control logic starts driving the RX_nACK signal, de-asserting it when the internal FIFO becomes full or the DMA transfer completes. The wrapper logic will drive the RX_nREQ signal when it has data valid to be transferred: the transfer is done, and the data can be updated, if RX_nREQ and RX_nACK are both asserted on the same clock.
RX FIFO

The FIFO depth can be 2/4/8/16/32 entries, 32 bit each. The RX FIFO is loaded by the RX wrapper interface logic and read by the RX DMA master SM. The FIFO download is done with 32 bits operations (possibly burst type to optimize the bus bandwidth). If there are some incomplete words coming from the MAC core (this con occurs only at the end of the frame) the DMA adds some dummy bytes in order to complete the word and increase the performance. Added bytes have an undefined value.
RX DMA MASTER SM

The RX DMA block has a State Machine (SM) dedicated to the DMA master operation. When enabled via the RX configuration registers, it's able to manage the RX data transfer without further processor intervention. The DMA transfer can be: DMA continuous/fixed size: the DMA can be required to run indefinitely or to stop after a configured number of data bytes has been transferred fixed/incrementing address: the DMA address can be fixed (i.e. all the data are transferred to the same AHB word aligned address) or it can be updated after each data transfer linear incrementing or wrapping address: when the address is defined as incrementing, it can be required that, once reached a programmed value, the address counter wraps back to the initial address value (the address location, pointed by the wrapping address, is not modified) with FIFO entry threshold: the DMA SM starts transferring data on the AHB bus when a programmable number of 32 bit RX FIFO entries is valid When the DMA is enabled, as soon as data appears in the FIFO, the DMA may either initiate an AHB transfer immediately, or be delayed until X data bytes are available in the FIFO (FIFO entry threshold). The DMA can be configured to wrap-round the AHB address at some point to implement a circular buffer in CPU memory. The DMA can be configured to run indefinitely or to stop after DMA_XFERCOUNT data have been transferred.

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When the DMA completes, the master DMA SM can be required to assert an interrupt request to the processor and wait for new instruction, or to wake up the DMA descriptor SM to require a new DMA descriptor fetch. To save gates, the implementation limits the maximum DMA transfer count to 4 Kbytes, hence the XFER_COUNT field in the DMA control registers is limited to 12 bits. The DMA start address (DMA_ADDRESS) must be 32 bit word aligned. The DMA wrapping address point must be 32 bit word aligned. If an AHB error condition occurs, while the DMA is running, the SM activity is suspended, until the error interrupt bit (MERR_INT) is reset. When the error condition is removed the DMA makes the same request previously interrupted by the error response.
DMA descriptor SM

A dedicated SM has been implemented that, when required by the DMA master logic, starts some AHB master read operations to load from the external memory all the information (DMA descriptors) required to start the new DMA data transfer. The DMA descriptor consists of a VALID bit plus 3 registers: the DMA control (DMA_CTL), the DMA base address (DMA_ADDR) and the DMA next descriptor address register (DMA_NXT). The Host Processor must ensure that the descriptors are up to date in memory when the DMA descriptor SM loads them. The fetch order is: DMA_CTL, DMA_ADDR, DMA_NXT and VALID bit. If a fetched descriptor is not valid (VALID=0), then the DMA engine can be programmed to stop the operation (reset the DMA_EN bit in RX_DMA_START) and raise an interrupt (RX_DONE), or to repeat the descriptor fetch operation, until a valid descriptors is found. The interrupt register bit named RX_NEXT is always set when a not valid descriptor is loaded. In the first case, the DMA will then wait for the Host Processor to re-enable the DMA operation (START_FETCH bit in the RX_DMA_START register set to 1) before attempting anew descriptor fetch. While, when in polling mode, the DMA will keep reloading the descriptor, with an access frequency determined by the DFETCH_DLY field in the RX_DMA_START register. An AHB ERROR response suspends the descriptor SM activity and reset the DMA_EN bit in RX_DMA_START register. To help the error source understanding, the RX_DMA_CADDR register value is the address at which the error occurred. After clearing the error bit, the SW needs to reprogram the DMA registers, to start again a new descriptor fetch.

6.2.2.3 TX LOGIC
The transmit (TX) DMA block includes all the logic required to manage data transfers from an external AHB memory mapped device to the TX port of the MAC110 wrapper. It includes:

TX wrapper interface TX FIFO TX DMA master SM DMA descriptor SM

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TX WRAPPER INTERFACE

The wrapper interface is a simple synchronous interface with TX_nREQ, TX_nACK, TX_DATA signals for data handshake, plus some sideband signals for the MAC protocol support (see later). The data path (TX_DATA) is 32 bit wide. When the TX DMA logic has been enabled, as soon as the internal FIFO is no more empty the TX interface control logic starts driving the TX_nACK signal, de-asserting it when the internal FIFO becomes empty again or the DMA transfer completes. The wrapper has to drive the TX_nREQ signal when it accept valid data to be transferred: the transfer is done and the data can be updated if TX_nREQ and TX_nACK are both asserted on the same clock.
TX FIFO

The FIFO depth can be 2/4/8/16/32 entries, 32 bit each. The TX FIFO is loaded by the TX DMA master SM and read by the TX wrapper interface. The FIFO load is usually done with 32 bits operations (possibly burst type to optimize the bus bandwidth), unless the DMA end has been reached and the DMA buffer size is not a multiple of 32 bits.
TX DMA MASTER SM

The TX DMA block has a State Machine (SM) dedicated to the DMA master operation. When enabled via the TX configuration registers, it's able to manage the TX data transfers without further processor intervention. The DMA transfer can be: DMA continuous/fixed size: the DMA can be required to run indefinitely or to stop after a configured number of data bytes has been transferred fixed/incrementing address: the DMA address can be fixed (i.e. all the data are transferred from the same AHB, word aligned, address) or it can be updated after each data transfer linear incrementing or wrapping address: when the address is defined as incrementing, it can be required that, once reached a programmed value, the address counter wraps back to the initial address value (the address location, pointed by the wrapping address, is not accessed) with FIFO entry threshold: the DMA SM starts transferring data on the AHB bus when a programmable number of 32 bit TX FIFO entries is empty When the DMA is enabled, as soon as one free entry is available in the FIFO, the DMA may initiate AHB transfers immediately, or can be delayed. The DMA may be delayed until X data entries are available in the FIFO (FIFO entry threshold). The DMA can be configured to wrap-round the AHB address at some point to implement a circular buffer in CPU memory. The DMA can be configured to run indefinitely or to stop after DMA_XFERCOUNT data have been transferred. When the DMA completes, the master DMA SM can be required to assert an interrupt request to the processor and wait for new instruction, or to wake up the DMA descriptor SM, to require a new DMA descriptor fetch. To save gates, the implementation limits the maximum DMA transfer count to 4Kbytes, hence the XFER_COUNT field in the DMA control registers is limited to 12 bits.
The DMA start address (DMA_ADDRESS) must be 32 bit word aligned and the DMA wrapping address point must be 32 bit word aligned.

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If an AHB error condition occurs, while the DMA is running, the SM activity is suspended, until the error interrupt bit (MERR_INT) is reset. When the error condition is removed the DMA makes the same request previously interrupted by the error response. Special care must be taken when the FIFO entry to be read has 3 valid bytes: in this case, because the AHB protocol doesn't allow to 3 byte transfers, the AHB master splits the transfer in two single transfers (byte + half or half + byte) and sends an acknowledge signal to the FIFO only when the second one has been read. If the second read receives an error response then, when the error condition is removed, the DMA repeats even the first one (because the FIFO has not yet see the acknowledge).

DMA DESCRIPTOR SM

A dedicated SM has been implemented that, when required by the DMA master logic, starts some AHB master read operations to load from the external memory all the information (DMA descriptors) required to start the DMA data transfer. The DMA descriptor consists of a VALID bit plus 3 registers: the DMA control (DMA_CTL), the DMA base address (DMA_ADDR) and the DMA next descriptor address register (DMA_NXT). The Host Processor must ensure that the descriptors are up to date in memory when the DMA descriptor SM loads them. The fetch order is: DMA_CTL, DMA_ADDR, DMA_NXT and VALID bit. If a fetched descriptor is not valid (VALID=0), then the DMA engine can be programmed to stop the operation (reset the DMA_EN bit in TX_DMA_START) and raise an interrupt (TX_DONE), or to repeat the descriptor fetch operation, until a valid descriptors is found. The interrupt register bit named TX_NEXT is always set when a not valid descriptor is loaded. In the first case, the DMA will then wait for the HP to re-enable the DMA operation (START_FETCH bit in the TX_DMA_START register set to 1) before attempting a new descriptor fetch. While, when in polling mode, the DMA will keep reloading the descriptor, with an access frequency determined by the DFETCH_DLY field in the TX_DMA_START register. An AHB ERROR response suspends the descriptor SM activity and reset the DMA_EN bit in TX_DMA_START register. To help the error source understanding, the TX_DMA_CADDR register value is the address at which the error occurred. After clearing the error bit, the SW needs to reprogram the DMA registers, to start again a new descriptor fetch.

6.2.3
Table 11.

Ethernet register map
Ethernet register map
Register Name DMA_STS_CNTL DMA_INT_EN DMA_INT_STS Reserved RX_DMA_START Description Ethernet DMA, status and control register Ethernet DMA, Interrupt sources enable register Ethernet DMA, Interrupt status register Ethernet DMA, RX start register

Address 0x3000_3000 0x3000_3004 0x3000_3008 0x3000_300C 0x3000_3010

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Table 11.

Ethernet register map (continued)
Register Name RX_DMA_CNTL RX_DMA_ADDR RX_DMA_NXT RX_DMA_CADDR RX_DMA_CXFER RX_DMA_TO RX_DMA_FIFO TX_DMA_START TX_DMA_CNTL TX_DMA_ADDR TX_DMA_NXT TX_DMA_CADDR TX_DMA_CXFER TX_DMA_TO TX_DMA_FIFO reserved RX_FIFO Reserved TX_FIFO Reserved MAC_CNTL MAC_ADDH MAC_ADDL MAC_MCHTH MAC_MCHTL MII_ADDR MII_DATA FCR VLAN1 VLAN2 Reserved Description Ethernet DMA, RX control register Ethernet DMA, RX base address register Ethernet DMA, RX next descriptor address register Ethernet DMA, RX current address register Ethernet DMA, RX current transfer count register Ethernet DMA, RX time out register Ethernet DMA, RX FIFO status register Ethernet DMA, TX start register Ethernet DMA, TX control register Ethernet DMA, TX base address register Ethernet DMA, TX next descriptor address register Ethernet DMA, TX current address register Ethernet DMA, TX current transfer count register Ethernet DMA, TX time out register Ethernet DMA, TX FIFO status register RX local FIFO (32 double word = 128 byte) TX local FIFO (32 double word = 128 byte) MAC control register MAC address high register MAC address low register MAC, multi cast hash table high register MAC, multi cast hash table low register MII, address register MII, data register Flow control register VLAN1 tag register VLAN2 tag register -

Address 0x3000_3014 0x3000_3018 0x3000_301C 0x3000_3020 0x3000_3024 0x3000_3028 0x3000_302C 0x3000_3030 0x3000_3034 0x3000_3038 0x3000_303C 0x3000_3040 0x3000_3044 0x3000_3048 0x300_304C 0x3000_3050 0x3000_30FC 0x3000_3100 0x3000_317C 0x3000_3180 0x3000_31FC 0x3000_3200 0x3000_327C 0x3000_3280 0x3000_33FC 0x3000_3400 0x3000_3404 0x3000_3408 0x3000_340C 0x3000_3410 0x3000_3414 0x3000_3418 0x3000_341C 0x3000_3420 0x3000_3424 0x3000_3428 0x3000_34FC

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Table 11. Ethernet register map (continued)
Register Name MMC_CTRL_REG MMC_INT_HI_REG MMC_INT_LO_REG MMC_INT_MSK_HI_RE G Description MMC Statistic Control Register MMC Statistic Interrupt High Register MMC Statistic Interrupt Low Register MMC Statistic Interrupt Mask High Register

6 Blocks description

Address 0x3000_3500 0x3000_3504 0x3000_3508 0x3000_350C 0x3000_3510

MMC_INT_MSK_LO_RE MMC Statistic Interrupt Mask Low Register G RxNumFrmsAllCntr All frames received counter. This includes good and bad frames. Counter is incremented each time a frame is received. Good frame received counter. This includes good frames only, which are free from runt frame error, frame too long error, collision error, MII error, dribble bit error, CRC error, invalid length error and FIFO overflow error. Control frames received counter. This includes control frames, which are free from runt frame error, frame too long error, collision error, MII error, dribble bit error, CRC error, invalid length error and FIFO overflow error. Unsuppor ted control frames received counter. This includes control frames, which are free from runt frame error, frame too long error, collision error, MII error, dribble bit error, CRC error, invalid length error and FIFO overflow error but whose length/ type field is not supported. No of bytes received counter. This includes all frames frame length added. Excludes preamble. No of bytes received counter. This includes all frames frame length added which are free from runt frame error, frame too long error, collision error, MII error, dribble bit error, CRC error, invalid length error and FIFO overflow error. Frame with length equal to 64 bytes counter. Includes good and bad frames. Frame with length from 65 to 127 bytes counter. Includes good and bad frames. Frame with length from 128 to 255 bytes counter. Includes good and bad frames. Frame with length from 256 to 511 bytes counter. Includes good and bad frames. Frame with length from 512 to 1023 bytes counter. Includes good and bad frames. Frame with length from 1024 to MaxPktSize bytes counter. Includes good and bad frames.

0x3000_3600

0x3000_3604

RxNumFrmsOkCntr

0x3000_3608

RxCntrlFrmsCntr

0x3000_360C

RxUnsupCntrlCntr

0x3000_3610

RxNumBytsAllCntr

0x3000_3614

RxNumBytsOkCntr

0x3000_3618 0x3000_361C 0x3000_3620 0x3000_3624 0x3000_3628 0x3000_362C

RxLenEqual64Cntr RxLen65_127Cntr RxLen128_255Cntr RxLen256_511Cntr RxLen512_1023Cntr RxLen1024_MaxCntr

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Table 11.

Ethernet register map (continued)
Register Name RxUnicastCntr RxMulticastCntr RxBroadcastCntr Description Unicast frames received counter. This includes good frames only. Multicast frames received counter. This includes good frames only. Broadcast frames received counter. This includes good frames only. Frames with FIFO error counter. Counter with Rx FIFO overflow error. This counter is incremented if the missed frame bit in receive status is set. Runt frame counter. Counter for frames with a minimum frame length violation. This counter is incremented if the runt frame bit in receive status is set. Long frames counter. Counter for frames with a maximum frame length violation. This counter is incremented if the Frame Too Long bit in receive status is set. Frame with a CRC error counter. This counter is incremented if the CRC error bit in receive status is set. Frames with a dribble bit counter. This counter is incremented if the dribble bit in receive status is set. Length error frames counter. This counter is incremented if the length error bit in receive status is set. Ethernet frames counter. This counter is incremented when the frame type bit in receive status is set.

Address 0x3000_3630 0x3000_3634 0x3000_3638

0x3000_363C

RxFifoOverflowCntr

0x3000_3640

RxMinLenCntr

0x3000_3644

RxMaxLenCntr

0x3000_3648

RxCrcErrorCntr

0x3000_364C

RxAlignErrorCntr

0x3000_3650

RxLenghtErrCntr

0x3000_3654 0x3000_3658 0x3000_36FF 0x3000_3700

RxEthrTypFrmCntr

Reserved No of frames transmitted counter. This includes good and bad frames but no retries. Counter is incremented each time the transmit status is received. No of control frames transmitted counter. Counter for good control frames only. Counter is incremented each time transmit status is received and if the frame transmitted is a control frame. Does not include retries. Total number of transmitted bytes counter. Counter is incremented each time transmit status is received. Includes good and bad frames but no retries. Total number of (well) transmitted bytes counter. Counter for bytes of a good frame transmitted. Does not include retries. The good frames are the ones for which the frame abort and packet retry bits in transmit status are reset.

TxNumFrmsAllCntr

0x3000_3704

TxCntrlFrmsCntr

0x3000_3708

TxNumBytsAllCntr

0x3000_370C

TxNumBytsOkCntr

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Table 11. Ethernet register map (continued)
Register Name Description

6 Blocks description

Address

0x3000_3710

TxLenEqual64Cntr

Frames with length equal to 64 counter. Counter for frames with length equal to 64. Includes good and bad frames but no retries. Frames with length from 65 to 127 counter. Counter for frames with length between 65 and 127 bytes. Includes good and bad frames but no retries. Frames with length from 128 to 255 counter. Counter for frames with length between 128 and 255 bytes. Includes good and bad frames but no retries. Frames with length from 256 to 511 counter. Counter for frames with length between 256 and 511 bytes. Includes good and bad frames but no retries. Frames with length from 512 to 1023 counter. Counter for frames with length between 512 and 1023 bytes. Includes good and bad frames but no retries. Frames with length from 1024 to MaxPktSize counter. Counter for frames with length between 1024 and maximum frame lenght bytes. Includes good and bad frames but no retries. No of Unicast frames transmitted counter. Includes good frames only, no retries. No of multicast frames transmitted counter. Includes good frames only, no retries. No of broadcast frames transmitted counter. Includes good frames only, no retries. No of frames aborted due to FIFO error counter. This counter is incremented when the under run bit in transmit status is set. No of frames aborted counter. This counter is incremented if either the frame aborted or the heart bit fail are set in transmit status. No of frames with single collision counter. The counter is incremented when the collisions count = 1 and packet retry set in transmit status. No of frames with multiple collisions counter. The counter is incremented when the collisions count > 1 and packet retry set in transmit status. No of frames deferred counter. This counter is incremented when the deferred bit in transmit status is set. No of frames with late collision counter. This counter is incremented when the late collision bit in transmit status is set.

0x3000_3714

TxLen65_127Cntr

0x3000_3718

TxLen128_255Cntr

0x3000_371C

TxLen256_511Cntr

0x3000_3720

TxLen512_1023Cntr

0x3000_3724

TxLen1024_MaxCntr

0x3000_3728 0x3000_272C 0x3000_3730

TxUnicastCntr TxMulticastCntr TxBroadcastCntr

0x3000_3734

TxFifoUndFloCntr

0x3000_3738

TxNumBadFrmsCntr

0x3000_373C

TxSingleColCntr

0x3000_3740

TxMultiColCntr

0x3000_3744

TxNumDeffredCntr

0x3000_3748

TxLateColCntr

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Table 11.

Ethernet register map (continued)
Register Name Description No of frames aborted counter. This counter is incremented when the frame aborted bit in transmit status is set. Number of frames with no carrier counter. This counter is incremented when either the no carrier or the loss of carrier bit in transmit status is set. No of frames with excessive deferral counter. This counter is incremented when the excessive deferral bit in transmit status is set.

Address

0x3000_374C

TxAbor tedFrmsCntr

0x3000_3750

TxNoCrsCntr

0x3000_3754 0x3000_3758 0x3000_37FC

TxXsDeferalCntr

Reserved

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6 Blocks description

6.2.4

Register description
All the registers are 32 bit wide.

6.2.4.1 Ethernet DMA, Status and Control Register
Mnemonic: DMA_STS_CNTL Address: 0x3000_3000 Default value: 4A4A0101
Bit 31 - 28 27 - 26 25 - 24 23 - 20 19 - 18 17 - 16 15 - 08 Bit 07 - 06 05 - 04 03 - 02 01 00 Field name TX_FIFO_SIZE TX_IO_DATA_WIDTH TX_CHANNEL_STATUS RX_FIFO_SIZE RX_IO_DATA_WIDTH RX_CHANNEL_STATUS REVISION Field name TX_MAX_BURST_SIZE RX_MAX_BURST_SIZE Reser ved LOOPB SRESET Access RO RO RO RO RO RO RO Access RW RW RO RW RW

TX_FIFO_SIZE: Size of transmitter data path FIFO.

Value: 04 16 * 32 bit words.

TX_IO_DATA_WIDTH: Width of the I/O bus transmit data path.

Value: 2'b10 32 bit.

TX_IO_CHANNEL_STATUS: TX channel status structure.

Value: 2'b10 High End TX channel capable of DMA descriptor fetch.

RX_FIFO_SIZE: Size of receiver data path FIFO.

Value: 04 16 * 32 bit words.

RX_IO_DATA_WIDTH: Width of the I/O bus receiver data path.

Value: 2'b10 32 bit.

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RX_IO_CHANNEL_STATUS: RX channel status structure.

Value: 2'b10 High End RX channel capable of DMA descriptor fetch.

REVISION: Revision of the DMA block.

Value: 0x01

TX_MAX_BURST_SIZE: Maximum value of defined length burst that the TX DMA_MAC logic will perform on the AHB bus to read data from the main memory.

2'b00 2'b01 2'b10 2'b11

16 beat incrementing burst (INCR16) 8 beat incrementing burst (INCR8) 4 beat incrementing burst (INCR4) Single transfer only (SINGLE)

Descriptor fetch operation isn't affected by this field.
RX_MAX_BURST_SIZE: Maximum value of defined length burst that the RX DMA_MAC logic will perform on the AHB bus to write data to the main memory.

2'b00 2'b01 2'b10 2'b11

16 beat incrementing burst (INCR16) 8 beat incrementing burst (INCR8) 4 beat incrementing burst (INCR4) Single transfer only (SINGLE)

Descriptor fetch operation isn't affected by this field.

LOOPB: Set to '1' to enable the DMA block loop_back mode. When set the RX DMA data are extracted by the TX FIFO and pushed in the RX one. SRESET: DMA soft reset. Set to '1' to hold the whole DMA_MAC and MAC110 logic in reset condition. Write '0' to exit from the reset phase. Note: After a HW reset, the DMA logic wakes up with the SRESET bit asserted ('1'), to keep all the DMA and MAC110 logic in the reset condition, until the SW is sure that clocks and the other MII signals, inputs to the MAC110 core, are stable. When this condition is met, the SW is allowed to clear the SRESET bit (write '0') to start the normal operation. Until the SRESET bit is set to '1', no operation is allowed on the DMA_MAC or MAC110 registers, except the SRESET bit clear. This signal has no effect on the AHB interface so, when asserted runtime, the whole DMA will be reset only when the last AHB transfer, in the AHB master queue, has been completed.

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6.2.4.2 Ethernet DMA, Interrupt Sources Enable Register
Mnemonic: DMA_INT_EN Address: 0x3000_3004 Default value: 0x0000_0000
Bit 31 30 - 29 28 27 - 26 25 24 23 22 21 - 20 19 18 17 16 15 14 - 10 09 08 07 06 05 04 03 02 01 00 Field name TX_CURR_DONE_EN Reser ved MAC110_INT_EN Reser ved TX_MERR_INT_EN Reser ved TX_DONE_EN TX_NEXT_EN Reser ved TX_TO_EN TX_ENTRY_EN TX_FULL_EN TX_EMPTY_EN RX_CURR_DONE_EN Reser ved RX_MERR_INT_EN Reser ved RX_DONE_EN RX_NEXT_EN PACKET_LOST_EN Reser ved RX_TO_EN RX_ENTRY_EN RX_FULL_EN RX_EMPTY_EN Access RW RO RW RO RW RO RW RW RO RW RW RW RW RW RO RW RO RW RW RW RO RW RW RW RW

The DMA Interrupt enable register allows the various sources of interrupt to be individually enabled.
All the enabled sources will then be OR-ed to generate the global DMA interrupt.

Setting a bit in DMA_INT_EN allows the corresponding interrupt described in DMA_INT_STAT to influence the global DMA Interrupt. If any bit position is set to '1' in BOTH DMA_INT_STAT and DMA_INT_EN, then the DMA Interrupt will be asserted. Refer to the DMA_INT_STAT for a description of interrupt sources.
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6.2.4.3 Ethernet DMA, Interrupt Status Register
Mnemonic: DMA_INT_STS Address: 0x3000_3008 Default value: 0x0000_0000
Bit 31 30 - 29 28 27 - 26 25 24 23 22 21 - 20 19 18 17 16 15 14 - 10 09 08 07 06 05 04 03 02 01 00 Field name TX_CURR_DONE Reser ved MAC110_INT Reser ved TX_MERR_INT Reser ved TX_DONE TX_NEXT Reser ved TX_TO TX_ENTRY TX_FULL TX_EMPTY RX_CURR_DONE Reser ved RX_MERR_INT Reser ved RX_DONE RX_NEXT PACKET_LOST Reser ved RX_TO RX_ENTRY RX_FULL RX_EMPTY Access RC RO RC RO RC RO RC RC RO RC RC RC RC RC RO RC RO RC RC RC RO RC RC RC RC

DMA Interrupt Status Register reports the interrupt status of interrupts from the following sources: DMA RX, DMA TX, MAC110. All the register locations are read/clear (RC): they can be read, a write with '0' has no effect, while writing '1' reset the bit.
TX_CURR_DONE: Set when the TX master DMA has completed the CURRENT DMA transfers.

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This bit differs from the TX_DONE because the TX_CURRENT_DONE will be set after a single DMA descriptor execution has been completed, the status register updated and the descriptor valid bit cleared, while the TX_DONE will be set only after all the descriptors in the descriptor chain have been fully executed. Write '1' to clear flag.
MAC110_INT: Set when the external MAC110 device sets an interrupt request.

Write '1' to clear flag.
TX_MERR_INT: Set when the AHB master receives an error response from the selected slave and the internal arbiter is granting the TX FIFO.

Write '1' to clear flag.
TX_DONE: Set when the TX master DMA completes.

Write '1' to clear flag.
TX_NEXT: Set when a descriptor fetch operation loads an invalid entry.

Write '1' to clear flag.
TX_TO: Set when some data are stalled in the TX FIFO for too long.

Write '1' to clear flag.
TX_ENTRY: Set when the TX DMA is triggered by a number of empty TX FIFO entries bigger than the value set in the DMA_CNTL register.

Write '1' to clear flag.
TX_FULL: Set when the TX FIFO becomes full (< 4 byte entries available).

Write '1' to clear flag.
TX_EMPTY: Set when the TX FIFO becomes empty.

Write '1' to clear flag.
RX_CURR_DONE: Set when the RX master DMA has completed the CURRENT DMA transfers.

This bit differs from the RX_DONE because the RX_CURRENT_DONE will be set after a single DMA descriptor execution has been completed, the status register updated and the descriptor valid bit cleared, while the RX_DONE will be set only after all the descriptors in the descriptor chain have been fully executed. Write '1' to clear flag.
RX_MERR_INT: Set when the AHB master receives an error response from the selected slave and the internal arbiter is granting the RX FIFO.

Write '1' to clear flag.
RX_DONE: Set when the RX master DMA completes.

Write '1' to clear flag.
RX_NEXT: Set when the descriptor fetch operation loads an invalid entry.

Write '1' to clear flag.

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PACKET_LOST: Set by the RX wrapper when there is an incoming frame but the RX DMA logic cannot service it because:

the RX FIFO is not empty yet or the next descriptor fetch is still running Write '1' to clear flag.
RX_TO: Set when some data are stalled in the RX FIFO for too long.

Write '1' to clear flag.
RX_ENTRY: Set when the RX DMA is triggered by a number of valid RX FIFO entries bigger than the value set in the DMA_CNTL register.

Write '1' to clear flag.
RX_FULL: Set when the RX FIFO becomes full and no more data can be accepted.

Write '1' to clear flag.
RX_EMPTY: Set when the RX FIFO becomes empty.

Write '1' to clear flag.

6.2.4.4 Ethernet DMA, RX Start Register
Mnemonic: RX_DMA_START Address: 0x3000_3010 Default value: 0x0000_0000
Bit 31 - 24 23 - 08 07 06 05 04 - 03 02 01 00 Field name Reser ved DFETCH_DLY CALL_SEEN RUNT_FRAME FILTER_FAIL Reser ved START_FETCH Reser ved DMA_EN Access RO RW RW RW RW RO RS RO RC

DFETCH_DLY: Descriptor fetch delay. This field specifies, in a bus clock periods, the delay between two descriptor fetches, in the event that the descriptor in main memory is not valid.

When set to '0' it forces the DMA_MAC logic, in case of invalid descriptor, to wait for 2**16 system bus clocks before attempting a new fetch.

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COLL_SEEN: When '1' the Late Collision seen condition, reported by the MAC110 in the RX packet status word, will make the received frame to be discharged by the DMA_MAC, without any report to the CPU.

When '0' no action will be taken by the DMA_MAC.
RUNT_FRAME: When '1' the Damaged Frame condition (e.g. normal collision, frame too short, etc.), reported by the MAC110 in the RX packet status word, will make the received frame to be discharged by the DMA_MAC, without any report to the CPU.

When '0' no action will be taken by the DMA_MAC.
FILTER_FAIL: When '1' the Address Filtering Failed condition, reported by the MAC110 during the RX packet transmission, will make the received frame to be discharged by the DMA_MAC, without any report to the CPU.

When '0' no action will be taken by the DMA_MAC. If this bit is set the data of packets that don't match the address filtering process (inside the MAC core) are not moved to the memory reducing the AHB bus utilization.
START_FETCH: This bit is a Read/Set bit, that means it can be both read and written, but writing a '0' has no effect.

The SW has to set this bit to '1' when the RX DMA has to start fetching the first descriptor. The DMA logic will reset to '0' this bit and set the DMA_EN to '1' as soon as the first fetch has been completed.
Note: Before starting the DMA, the DMA_NXT register has to be loaded with the starting address of the descriptor to be fetched. DMA_EN: Read/Clear bit: a write with '1' reset to '0' the bit value, while a write with '0' has no effect.

This bit, set to '1' by the DMA after the first descriptor fetch, can be reset to '0' by the SW to force a DMA abort and stop as soon as possible the data transfer, before the DMA completion. When all the DMA sequences complete normally, this bit is reset by the DMA_MAC logic and a new SW intervention is required to restart the DMA engine.
Note:

The DMA_EN 0->1 transition resets the FIFO content and the RX interrupts (DMA_INT_STAT(15:0)). The DMA_EN 1->0 transition forces the DMA to close immediately the transfers toward AHB bus and MAC core. When the AHB transfer completes the DMA_INT_STAT.RX_DONE interrupt is set and the processor can reprogram and reactivate the RX logic.

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6.2.4.5 Ethernet DMA, RX Control Register
Mnemonic: RX_DMA_CNTL Address: 0x3000_3014 Default value: 0x0000_0000
Bit 32 - 22 21-17 16 15 14 13 12 11 - 00 Field name ADDR_WRAP ENTRY_TRIG Reser ved DLY_EN NXT_EN Reser ved CONT_EN DMA_XFERCOUNT Access RW RW RO RW RW RO RW RW

ADDR_WRAP: Determines where the DMA address counter wraps by forcing the DMA address counter to retain the data originally written by the host in DMA_ADDR. As soon as the DMA has written the memory location prior to the value specified in ADD_WRAP the wrapping condition occurs.

This can be used to restrict the address counter within an address window (e.g. circular buffer). The wrapping point MUST be 32 bit aligned, so the 10 bits of ADDR_WRAP are used to compare DMA address bits 11 to 2; if ADD_WRAP=DMA_ADDR(11:2) then a 4Kbyte buffer is defined. ADDRWRAP is ignored unless WRAP_EN is set.
ENTRY_TRIG: Determines the amount of valid entries (in 32 BIT WORDs) required in the receive FIFO before the DMA is re-triggered.

If the value is set to 0, as soon as one valid entry is present, the DMA logic starts the data transfer.
DLY_EN: This bit enables (when '1') the DMA trigger delay feature: if a FIFO valid data resides in the FIFO more than a programmed period (DMA_TO), a time-out condition occurs that requires the DMA SM to empty the

FIFO even if the number of valid words doesn't exceed the threshold value.
NXT_EN: Next Descriptor Fetch Mode enable. Set to '1', this bit enables the next descriptor fetch mechanism.

Whenever a DMA transfer is completed, if this field is set, a new DMA descriptor is fetched. If this field is '0' then no descriptor is fetched and an interrupt is raised as normal. Note when a descriptor is fetched RX_DMA_CTL is one of the registers updated
CONT_EN: Continuos Mode Enable. This bit enables the DMA to run in continuo mode. If set the DMA runs indefinitely ignoring DMA_ XFERCOUNT. Note: "continuos mode" supersedes "next descriptor mode".

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DMA_XFERCOUNT: Block size (in bytes) of DMA data transfer, up to 4 Kbytes.

If DMA_XFERCOUNT is set to '0', the DMA will transfer 4 Kbyte data.
Note: RX_DMA_CNTL.XFERCOUNT is used to provide an upper limit to the number of bytes the system can accept for each frame (it's usually equal to the dedicated frame buffer size in main memory). When this limit is not exceeded, all the data received from the line, via the MAC110 core, are copied to the memory frame buffer, and the effective length of the transfer it's the real frame size. On the other side, if the packet exceeds the XFERCOUNT value it will be truncated. The XFERCOUNT value must be approximated to the next word aligned block size (i.e. if the desired transfer size is 123 bytes, then the programmed value should be 124).

6.2.4.6 Ethernet DMA, RX Base address Register
Mnemonic: RX_DMA_ADDR Address: 0x3000_3018 Default value: 0x0000_0000
Bit 31 - 02 01 00 Field name DMA_ADDR FIX_ADDR WRAP_EN Access RW RW RW

DMA_ADDR: Start address, 32 bit WORD ALIGNED, for master DMA transfer.

This register is read by the DMA SM only before starting the DMA operation and when the wrap condition is met, so further updates of this register will have unpredictable effects on the running DMA.
FIX_ADDR: Disables incrementing of DMA_ADDR: this means that all the DMA data transfer operation will be performed at the same AHB address, i.e. the DMA base address. WRAP_EN: Enables wrap of the DMA transfer address to DMA_ADDR when the memory location, specified in ADDR_WRAP, is reached.

6.2.4.7 Ethernet DMA, RX Next Descriptor Address Register
Mnemonic: RX_DMA_NXT Address: 0x3000_301C Default value: 0x0000_0000
Bit 31 - 02 01 00 Field name DMA_DESCR_ADDR Reser ved NPOL_EN Access RW RO RW

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DMA_DESCR_ADDR: When the DMA next descriptor fetch is enabled, this register points to the next descriptor starting address. The DMA descriptors are 32 bits, so the DMA_DESCR_ADDR MUST be 32 bit aligned.

This register allows different DMA descriptors to be located in different memory area, because part of the current DMA descriptors, provides information to point to the next one (descriptor chaining). If the DMA descriptor fetch is not enabled, this register doesn't need to be updated.
NPOL_EN: Next Descriptor Polling Enable. When in 'Next Descriptor Fetch Mode', the descriptor fetch logic can load a not jet valid descriptor: if the NPOL is enabled ('1'), the logic is required to keep polling the DMA descriptor in main memory, until it's found to be valid. Note: In case of not valid descriptor, DMA_MAC behavior will be different depending on the NPOL bit; we can have:

NPOL=1 (polling enabled) -> the RX_NEXT bit will be set and a new descriptor fetch will be attempt after DFETCH_DLY clocks NPOL=0 (polling disabled) -> the RX_DONE bit will be set and the DMA_EN bit, in DMA_START register, will be cleared.

6.2.4.8 Ethernet DMA, RX Current Address Register
Mnemonic: RX_DMA_CADDR Address: 0x3000_3020 Default value: 0x0000_0000
Bit 31 - 00 Field name DMA_CADDR Access RO

DMA_CADDR: Current DMA address value, byte aligned.

The value of this register will change while the DMA is running, reflecting the value driven by the core on the AHB bus.

6.2.4.9 Ethernet DMA, RX Current Transfer Count Register
Mnemonic: RX_DMA_CXFER Address: 0x3000_3024 Default value: 0x0000_0000
Bit 31 - 12 11 - 00 Field name Reser ved DMA_CXFER Access RO RO

DMA_CXFER: Current DMA transfer count value.

It's updated while the DMA is running, when one word data is moved from the MAC core to the DMA FIFO, reporting the number of bytes that can still be accepted.

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6.2.4.10 Ethernet DMA, RX Time Out register
Mnemonic: RX_DMA_TO Address: 0x3000_3028 Default value: 0x0000_0000
Bit 31 - 16 15 - 00 Field name Reser ved TIME_OUT Access RO RW

TIME_OUT: This value is used as initial value for the FIFO entry time_out counter (it's recommended not to use too low value, to avoid too frequent interrupts).

The time-out counter starts as soon as one valid entry is present in the FIFO and is reset every time a data is pop out of the FIFO. The counter expires (FIFO time_out condition) if no FIFO data are pop for a period longer than the TIME_OUT register value; when this happens, depending on the control registers settings, an interrupt can be set.

6.2.4.11 Ethernet DMA, RX FIFO Status Register
Mnemonic: RX_DMA_FIFO Address: 0x3000_342C Default value: 0x0000_0000
Bit 31-30 29-24 23-21 20-16 15-13 12-08 07-04 03 02 01 00 Field name Reser ved ENTRIES Reser ved DMA_POINTER Reser ved IO_POINTER Reser ved DELAY_T ENTRY_T FULL EMPTY Access RO RO RO RO RO RO RO RO RO RO RO

ENTRIES: full entries (in 32 bit words) in FIFO. DMA_POINTER: FIFO DMA SM side pointer value. IO_POINTER: FIFO IO side pointer value. DELAY_T: Set to '1' when the DMA FIFO delay time_out is expired. ENTRY_T: Set to '1' when the DMA FIFO entry trigger threshold has been reached.

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FULL: Set to '1' when DMA FIFO is full. EMPTY: Set to '1' when the DMA FIFO is empty.

6.2.4.12 Ethernet DMA, TX Start Register
Mnemonic: TX_DMA_START Address: 0x3000_3030 Default value: 0x0000_0000
Bit 31-24 23-08 07 06 05 04-03 02 01 00 Field name Reser ved DFETCH_DELAY ADD_CRC_DIS PADDING_DIS UNDERRUN Reser ved START_FETCH Reser ved DMA_EN Access RO RW RW RW RW RO RS RO RC

DFETCH_DLY: Descriptor fetch delay. This field specifies, in a bus clock periods, the delay between two descriptor fetches, in the event that the descriptor in main memory is not valid.

When set to '0' it forces the DMA_MAC logic, in case of invalid descriptor, to wait for 2**16 system bus clocks before attempting a new fetch.
ADD_CRC_DIS: This bit drives the MAC110 input pin ADD_CRC_DISABLE to tell the MAC110 core not to add the CRC field at the end of the frame.

If its value is modified while the DMA is enabled, the results will be unpredictable.
PADDING_DIS: This bit drives the MAC110 input pin DISABLE_PADDING, to avoid the MAC110 add the padding bits for frames too short.

If its value is modified while the DMA is enabled, the results will be unpredictable.
UNDERRUN: When '1', the Under Run condition, reported by the MAC in the TX packet status word, will enable the DMA logic to retransmit the same packet to the MAC110 core, without reporting any error condition to the CPU. START_FETCH: This bit is a Read/Set bit, that means it can be both read and written, but writing a '0' has no effect.

The SW has to set this bit to '1' when the TX DMA has to start fetching the first descriptor. The DMA logic will reset to '0' this bit and set the DMA_EN to '1' as soon as the first fetch has been completed.
Note: Before starting the DMA, the DMA_NXT register has to be loaded with the starting address of the descriptor to be fetched. DMA_EN: Read/Clear bit: a write with '1' reset to '0' the bit value, while a write with '0' has no effect.

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This bit, set to '1' by the DMA after the first descriptor fetch, can be reset to '0' by the SW to force a DMA abort and stop as soon as possible the data transfer, before the DMA completion. When all the DMA sequences complete normally, this bit is reset by the DMA_MAC logic and a new SW intervention is required to restart the DMA engine.
Note:

The DMA_EN 0->1 transition resets the FIFO content and the TX interrupts (DMA_INT_STAT (31:16)). The DMA_EN 1->0 transition forces the DMA to close immediately the transfers toward AHB bus and MAC core. When the AHB transfer completes the DMA_INT_STAT.TX_DONE interrupt is set and the processor can reprogram and reactivate the TX logic.

6.2.4.13 Ethernet DMA, TX Control register
Mnemonic: TX_DMA_CNTL Address: 0x3000_3034 Default value: 0x0000_0000
Bit 31-22 21-17 16 15 14 13 12 11-00 Field name ADDR_WRAP ENTRY_TRIG Reser ved DLY_EN NXT_EN Reser ved CONT_EN DMA_XFER_COUNT Access RW RW RO RW RW RO RW RW

ADDR_WRAP: Determines where the DMA address counter wraps by forcing the DMA address counter to retain the data originally written by the host in DMA_ADDR. As soon as the DMA has read the memory location prior to the value specified in ADD_WRAP the wrapping condition occurs.

This can be used to restrict the address counter within an address window (e.g. circular buffer). The wrapping point MUST be 32 bit aligned, so the 10 bits of ADDR_WRAP are used to compare DMA address bits 11 to 2; if ADD_WRAP=DMA_ADDR(11:2) then a 4Kbyte buffer is defined. ADDRWRAP is ignored unless WRAP_EN is set.
ENTRY_TRIG: Determines the amount of empty entries (in 32 BIT WORDs) required in the TX FIFO before the DMA is re-triggered.

If the value is set to 0, as soon as one empty entry is present, the DMA logic starts the data request.
DLY_EN: This bit enables (when '1') the DMA trigger delay feature: if a FIFO valid data resides in the FIFO more than a programmed period (DMA_TO), a time-out condition occurs and the related (TX_TO) interrupt will be set.

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NXT_EN: Next Descriptor Fetch Mode enable. Set to '1', this bit enables the next descriptor fetch mechanism.

Whenever a DMA transfer is completed, if this field is set, a new DMA descriptor is fetched. If this field is '0' then no descriptor is fetched and an interrupt is raised as normal.
Note: when a descriptor is fetched TX_DMA_CTL is one of the registers updated. CONT_EN: Continuos Mode Enable. This bit enables the DMA to run in continuos mode. If set the DMA runs indefinitely ignoring DMA_ XFERCOUNT.

Note "continuos mode" supersedes "next descriptor mode".
DMA_XFERCOUNT: Block size (in bytes) of DMA, maximum 4 Kbytes. If DMA_XFERCOUNT is set to '0', the DMA will transfer 4 Kbyte data.

6.2.4.14 Ethernet DMA, TX Base Address Register
Mnemonic: TX_DMA_ADDR Address: 0x3000_3038 Default value: 0x0000_0000
Bit 31-02 01 00 Field name DMA_ADDR FIX_ADDR WRAP_EN Access RW RW RW

DMA_ADDR: Start address, 32 bit WORD ALIGNED, for master DMA transfer.

This register is read by the DMA SM only before starting the DMA operation and when the wrap condition is met, so further updates of this register will have unpredictable effects on the running DMA.
FIX_ADDR: Disables incrementing of DMA_ADDR: this means that all the DMA data transfer operation will be performed at the same AHB address, i.e. the DMA base address. WRAP_EN: Enables wrap of the DMA transfer address to DMA_ADDR when the memory location, specified in ADDR_WRAP, is reached.

6.2.4.15 Ethernet DMA, TX Next Descriptor Address Register
Mnemonic: TX_DMA_NXT Address: 0x3000_303C Default value: 0x0000_0000
Bit 31-02 01 00 Field name DMA_DESCR_ADDR Reser ved NPOL_EN Access RW RO RW

DMA_DESCR_ADDR: When the DMA next descriptor fetch is enabled, this register points to the next descriptor starting address. The DMA descriptors are 32 bits, so the DMA_DESCR_ADDR MUST be 32 bit aligned.

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This register allows different DMA descriptors to be located in different memory area, because part of the current DMA descriptors, provides information to point to the next one (descriptor chaining). If the DMA descriptor fetch is not enabled, this register doesn't need to be updated.
NPOL_EN: Next Descriptor Polling Enable. When in 'Next Descriptor Fetch Mode', the descriptor fetch logic can load a not jet valid descriptor: if the NPOL is enabled ('1'), the logic is required to keep polling the DMA descriptor in main memory, until it's found to be valid. Note: In case of not valid descriptor, DMA_MAC behavior will be different depending on the NPOL bit; we can have: NPOL=1 (polling enabled) -> the TX_NEXT bit will be set and a new descriptor fetch will be attempt after DFETCH_DLY clocks NPOL=0 (polling disabled) -> the TX_DONE bit will be set and the DMA_EN bit, in DMA_START register, will be cleared.

6.2.4.16 Ethernet DMA, TX Current Address Register
Mnemonic: TX_DMA_CADDR Address: 0x3000_3040 Default value: 0x0000_0000
Bit 31-02 Field name DMA_CADDR Access RO

DMA_CADDR: Current DMA address value, byte aligned. The value of this register will change while the DMA is running, reflecting the value driven by the core on the AHB bus.

6.2.4.17 Ethernet DMA, TX Current Transfer Count Register
Mnemonic: TX_DMA_CXFER Address: 0x3000_3044 Default value: 0x0000_0000
Bit 31-12 11-00 Field name Reser ved DMA_CXFER Access RO RO

DMA_CXFER: Current DMA transfer count value. It's updated while the DMA is running, when one data is moved from the main memory to the DMA FIFO, reflecting the number of bytes that must be still read.

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6.2.4.18 Ethernet DMA, TX Time Out Register
Mnemonic: TX_DMA_TO Address: 0x3000_3048 Default value: 0x0000_0000
Bit 31-16 15-00 Field name Reser ved TIME_OUT Access RO RW

TIME_OUT: This value is used as initial value for the FIFO entry time_out counter (it's recommended not to use too low value, to avoid too frequent interrupts).

This counter starts as soon as one valid entry is present in the FIFO and is reset every time a FIFO data is pop out of the FIFO. The counter expires (FIFO time_out condition) if no FIFO data are pop for a period longer than the TIME_OUT register value; when this happens, depending on the control registers settings, an interrupt can be set.

6.2.4.19 Ethernet DMA, TX FIFO Status Register
Mnemonic: TX_DMA_FIFO Address: 0x3000_304C Default value: 0x0000_0000
Bit 31-30 29-24 23-21 20-16 15-13 12-08 07-04 03 02 01 00 Field name Reser ved ENTRIES Reser ved DMA_POINTER Reser ved IO_POINTER Reser ved DELAY_T ENTRY_T FULL EMPTY Access RO RO RO RO RO RO RO RO RO RO RO

ENTRIES: free entries (in 32 bit words) in FIFO. DMA_POINTER: FIFO DMA SM side pointer value. IO_POINTER: FIFO IO side pointer value. DELAY_T: Set to '1' when the DMA FIFO delay time_out is expired. ENTRY_T: Set to '1' when the DMA FIFO entry trigger threshold has been reached.

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FULL: Set to '1' when DMA FIFO is full. EMPTY: Set to '1' when the DMA FIFO is empty.

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6.2.4.20 MAC Control Register
Mnemonic: MAC_CNTL Address: 0x3000_3400 Default value: 32'b0 0 0000_0 0 0100_0 0 0000_0 0 0000
Bit 31 30 29 28 27 26 - 24 23 22 - 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 - 06 05 04 03 02 01 - 00 Field name RA BLE Reser ved HBD PS Reser ved DRO OM FDM PAM PRM IF PBF HOFM Reser ved HPFM LCC DBF DRT Reser ved ASTP BOLMT DC Reser ved TXE RXE Reser ved Access RW RW RO RW RW RO RW RW RW RW RW RW RW RW RO RW RW RW RW RO RW RW RW RO RW RW RO

The MAC Control Register establishes the RX and TX operating modes and controls for address filtering and packet filtering. Table 5 describes the bit fields of the register.

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RA: Receive All. When set, all incoming packets will be received, regardless of the destination address. The address match checked according to Table 22, and is reported in Transmit Status. BLE: Endian mode. When BLE is set, the MAC operates in the big Endian mode. When BLE is reset, the MAC operates in the little Endian mode. The Endian mode is only for the data buffers. HBD: Heart Beat Disable. When set, the heartbeat signal quality (SQE) generator function is disabled. This bit should be set in the MII Mode. PS: Port Select. When reset, the MII port is selected and when set, the SRL (ENDEC) port is selected for transmit/receive operations on the Ethernet side. DRO: DRO-Disable Receive Own. When DRO is set, the MAC110 disables the reception of frames when the TXEN is asserted. The MAC110 will block the transmitted frame on the receive path. When DSO is reset, the MAC110 receives all the packets that are given by the PHY including those transmitted by the MAC100. This bit should be reset when the Full Duplex Mode bit is set or the Operating Mode is not set to 'Normal Mode'. OM: OM-Loop-Back Operating Mode. This bit selects the Loop-Back operation modes for the MAC110. This setting is only for Full Duplex Mode.
OM Type 2'b00 2'b01 2'b10 2'b11 Normal. No feedback Internal. Through MII External. Through PHY Reser ved.

In the Internal Loop-Back mode, the TX frame is received by the MII, and turned around back to the MAC110. In the External mode however, the TX frame is sent up to the PHY. The PHY will then turn that TX frame back to be received by the MAC110.
Note: that in the External mode the application has to set the PHY in Loop-Back mode by setting bit14 in the register space of the PHY. (IEEE802.3 sec.22.2.4.1) FDM: Full Duplex Mode. When Set, the MAC operates in a full-duplex mode where it can transmit and receive simultaneously. While in full-duplex mode: heartbeat check is disabled, heartbeat fail status should be ignored, and internal loop back is not allowed. PAM: Pass All Multicast. When set, indicates that all the incoming frames with a multicast destination address (first bit in the destination address field is '1' are received. Incoming frames with physical address destinations are filtered only if the address matches with the MAC Address. PRM: Promiscuous Mode. When set, indicates that any incoming valid frame is received regardless of its destination address. IF: IF-Inverse filtering. When IF is set, Address Check block operates in the inverse filtering mode. This is valid only during perfect filtering mode. PBF: Pass Bad Frames. When set, all incoming frames that passed the address filtering are received, including runt frames, collided frames, or truncated frames caused by Buffer underflow. HPFM: Hash/Perfect Filtering Mode. When reset, the Address Check block does a perfect address filter of incoming frames according the address specified in the MAC Address register. When set, the Address Check block does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast Hash Table Register. If the Hash

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Only (HO) is set, then physical addresses are imperfect filtered too. If Hash Only bit(HO) is reset, then physical addresses are perfect address filtered according to the MAC Address Register.
LCC: Late Collision Control. When set, enables the retransmission of the collided frame even after the collision period (late collision). When LC is reset, the MAC110 core disables the frame transmission on a late collision. In any case the Late Collision Status is appropriately updated in the Transmit Packet Status. DBF: Disable Broadcast frames. When set, disables the reception of broadcast frames. When reset, forwards all the broadcast frames to the memory. DRTY: Disable Retry. When set, the MAC will attempt only one transmission. When a collision is seen on the bus, the MAC will ignore the current frame and goes to the next frame and a retry error is reported in the Transmit Status. When DRTY is reset, the MAC will attempt 16 transmissions before signaling a retry error. ASTP: Automatic Pad Stripping. When set the MAC will strip the pad field on all the incoming frames if the length field is less than 46 bytes. The FCS field will also be stripped since it is computed at the transmitting station based on the data and pad field characters, and will be invalid for a received frame that has had the pad characters stripped. Receive frames which have a length field of 46 bytes or greater will be passed to the host unmodified (FCS is not stripped). When reset, the MAC will pass all the incoming frames to the host unmodified. BOLMT: BackOff Limit. The BOLMT bits allow the user to set its Back Off limit in a relaxed or aggressive mode. According to IEEE 802.3, the MAC110 has to wait for a random number [r] of Slot-Times** after it detects a collision, where:

0 < r < 2K The number K is dependent on how many times the current Frame to be transmitted have been retried, as follows: K= min(n,10) where n is the current number of retries. If a frame has been retried for 3 times, then K = 3 and r= 8 Slot-Times maximum If it has been retried for 12 times, then K = 10, and r = 1024 Slot-Times maximum. A LFSR (linear feedback shift register) 20-bit counter is used to emulate a 20bit random number generator from which r is obtained. Once a collision is detected, the number of the current retry of the current frame is used to obtain K (eq.2). This value of K translates into the number of bits to use from the LFSR counter. If the value of k is 3, the MAC100 will take the value in the first 3 bits of the LFSR counter, and use it to count down till Zero on every SlotTime. This will effectively causes the MAC110 to wait 8 Slot-Times. To add more flexibility to the user the Value of the BOLMT will force the number of bits to be used from the LFSR counter to a predetermined value as in the table below. Eq. 1

BOLMT Value 2'b00 2'b01 2'b10 2'b11

# Bits Used from LFSR counter 10 8 4 1

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Thus if the value of k = 10, then the MAC110 will look at the BOLMT if it is 00 then it will use the lower 10bits of the LFSR counter for the wait countdown. If BOLMT is 10 then it will only use the value in the first 4bits for the wait countdown, and so on... **Slot-Time = 512 bit times.
DC: Deferral Check. When DC is set, the deferral check is enabled in the MAC. The MAC will abort the transmission attempt if it has deferred for more than 24,288 bit times. Deferring starts when the transmitter is ready to transmit, but is prevented from doing so because CRS is active. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of BackOff, the deferral timer resets to 0 and restarts.

When reset, the deferral check is disabled in the MAC and the MAC defers indefinitely.
TE: Transmitter Enable. When set, the MAC's transmitter is enabled and it will transmit frames from the buffer on to the cable.

When reset, the MAC's transmitter is disabled and will not transmit any frames.
RE: Receiver Enable. When set, the MAC's receiver is enabled and will receive frames from the MII interface.

When reset, the MAC's receiver is disabled and will not receive any frames from the MII interface.

6.2.4.21 MAC Address High Register
Mnemonic: MAC_ADDH Address: 0x3000_3404 Default value: 0x0000_FFFF
Bit 31 - 16 15 - 00 Field name Reser ved PADDR[47:32] Access RO RW

The MAC Address Hi Register contains the upper 16 bits of the physical address of the MAC. The contents of this register are normally loaded from the EEPROM at power on through the EEPROM Controller.
PADDR[47:32]: Upper 16 bits (47:32) of the Physical Address of this MAC device.

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6.2.4.22 MAC Address Low Register
Mnemonic: MAC_ADDL Address: 0x3000_3408 Default value: 0xFFFF_FFFF
Bit 31 - 00 Field name PADDR[31:00] Access RW

The MAC Address Low Register contains the lower 32 bits of the physical address of the MAC. The contents of this register are normally loaded from the EEPROM at power on through the EEPROM Controller.
PADDR[31:00]: Lower 32 bits (31:00) of the Physical Address of this MAC device.

6.2.4.23 MAC Multi Cast Hash Table High Register
Mnemonic: MAC_MCHTH Address: 0x3000_340C Default value: 0x0000_0000
Bit 31 - 00 Field name HTABLE[63:32] Access RW

6.2.4.24 MAC Multi Cast Hash Table Low Register
Mnemonic: MAC_MCHTL Address: 0x3000_3410 Default value: 0x0000_0000
Bit 31 - 00 Field name HTABLE[31:00] Access RW

The 64-bit multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is passed through the CRC logic and the upper 6 bits of the CRC register are used to index the contents of the Hash table. The most significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit with in the register. A value of '0 0 0' selects the bit 0 of the selected register and a value of '11111' selects the bit 31 of the selected register. If the corresponding bit is '1', then the multicast frame is accepted else it is rejected. If the Pass All Multicast is set, then all multi-cast frames are accepted regardless of the multi-cast hash values.

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6.2.4.25 MII Address Register
Mnemonic: MAC_ADDR Address: 0x3000_3414 Default value: 0x0000_0000
Bit 31 - 16 15 11 10 - 06 05 - 02 01 00 Field name Reser ved PHY_ADD MII_REG Reser ved MII_WR MII_BUSY Access RO RW RW RO RW RW

The MII Address Register is used to control the Management cycles to the External PHY Controller chip.
PHY_ADD: Phy Address. These bits tell which of the 32 possible PHY devices are being accessed MII_REG: MII Register. These bits select the desired MII register in the selected PHY device. MII_WR: MII Write. Setting this bit tells the PHY that this will be a write operation using the MII data register. If this bit is not set, this will be a read operation, placing the data in the MII data register. MII_BUSY: MII Busy. This bit should read a logic 0 before writing to the MII address and MII data registers. This bit must also be set to 0 during write to the MII address register. During a MII register access, this bit will be then set to signify that a read or write access is in progress. The MII data register should be kept valid until the MAC clears this bit during a PHY write operation. The MII data register is invalid until the MAC has cleared it during a PHY read operation. The MII address register should not be written to until this bit is cleared.

6.2.4.26 MII Data Register
Mnemonic: MAC_DATA Address: 0x3000_3418 Default value: 0x0000_0000
Bit 31 - 16 15 00 Field name Reser ved MII_DATA Access RO RW

The MII Data Register contains the data to be written to the PHY register specified in the MII address register, or it contains the read data from the PHY register whose address is specified in the MII address register.
MII_DATA: This contains the 16-bit value read from the PHY after a MII read operation or the 16-bit data value to be written to the PHY before a MII write operation.

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6.2.4.27 Flow Control register
Mnemonic: FCR Address: 0x3000_341C Default value: 0x0000_0000
Bit 31 - 16 15 - 03 02 01 00 Field name PTIME Reser ved PCF FCE FCB Access RW RO RW RW RW

This register is used to control the generation and reception of the Control (PAUSE Command) frames by the MAC's Flow control block. A write to register with busy bit set to '1' triggers the Flow Control block to generate a Control frame. The fields of the control frame are selected as specified in the 802.3x specification and PauseTime value from this register is used in the "Pause Time" field of the control frame. The Busy bit is set until the control frame is transferred onto the cable. The Host has to make sure that the Busy bit is cleared before writing the register. The Pass Control Frames bit indicates the MAC whether to pass the control frame to the Host or not and Flow Control Enable bit enables the receive portion of the Flow Control block.
PTIME: Pause Time. This field tells the value that is to be used in the PAUSE TIME field in the control frame. PCF: Pass Control Frames. When set, the control frames are passed to the Host. The MAC110 core will decode the control frame (PAUSE), disables the transmitter for the specified amount of time. The Control Frame bit in the Receive Status (bit 25) is set and Transmitter Pause Mode signal indicates the current state of the MAC Transmitter.

When reset, the MAC110 core will decode the control frames but will not pass the frames to the Host. The Control Frame bit in the Receive Status (bit 25) will be set and the Transmitter Pause Mode signal gives the current status of the Transmitter, but the Packet Filter bit in the Receive Status is reset indication the application to flush the frame.
FCE: Flow Control Enable. When set, the MAC is enabled for operation and it will decode all the incoming frames for control frames. When the MAC receives a valid control frame (PAUSE command), it will disable the transmitter for the specified time.

When reset, the operation in the MAC is disabled and the MAC does not decode the frames for control frames.
Note: Flow Control is applicable when the MAC110 is set in Full Duplex Mode. In Half Duplex mode, this bit will enable using Backpressure to control flow of transmitted frames to the MAC110. FCB: Flow Control Busy. This bit should read a logic 0 before writing to the Flow Control register. To initiate a PAUSE control frame the host must set this bit to '1'. During a transfer of Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of the transmission of the PAUSE control frame, the MAC will reset to '0'.

The Flow Control register should not be written to until this bit is cleared.

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6.2.4.28 VLAN1 Tag Register
Mnemonic: VLAN1 Address: 0x3000_3420 Default value: 0x0000_FFFF
Bit 31 - 16 15 - 00 Field name Reser ved VLAN1_TAG Access RO RW

This register contains the VLAN Tag field to identify the VLAN1 frames. The MAC compares the 13th and 14th bytes of the incoming frame field and if a match is found, it sets the VLAN1 bit in the Rx-Status (bit 22) register. The legal length of the frame is increased from 1518 bytes to 1522 bytes.
VLAN1_TAG: This contains the VLAN Tag field to identify the VLAN1 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN1 frame detection.

6.2.4.29 VLAN2 Tag Register
Mnemonic: VLAN2 Address: 0x3000_3424 Default value: 0xFFFF_FFFF
Bit 31 - 16 15 - 00 Field name Reser ved VLAN2_TAG Access RO RW

This register contains the VLAN Tag field to identify the VLAN2 frames. The MAC compares the 13th and 14th bytes of the incoming frame field and if a match is found, it sets the VLAN2 bit in the Rx-Status register (bit 23). The legal length of the frame is increased from 1518 bytes to 1522 bytes.
VLAN2_TAG: This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared to the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.

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6.2.4.30 MMC Control Register
Mnemonic: MMC_CTRL_REG Address: 0x3000_3500 Default value: 0x0000_2F72
Bit 31 14 13 03 02 01 00 Reser ved MAX_FRM_SIZE RESET_ON_READ CNTR_ROLL_OVER CNTR_RESET Field name Access RO RW RW RW WO

This register establishes the operating mode of the management counters.
MAX_FRM_SIZE: These bits indicate the value of the Maximum Packet Size for the transmitted frames to be counted as long frames. RESET_ON_READ: When set the counter will be reset to 0 after read. CNTR_ROLL_OVER: When set, counters after reaching the maximum value start again from 0. CNTR_RESET: When set, all counters will be reset to 0.

6.2.4.31 MMC Interrupt High Register
Mnemonic: MMC_INT_HI_REG Address: 0x3000_33504 Default value: 0x0000_0000
Bit 31 12 11 10 09 08 07 06 05 04 03 02 01 00 Field name Reser ved TX_EXC_DEFER_FRMS TX_CRS_ERROR_FRMS TX_ABORTED_FRMS TX_LATE_COL_FRMS TX_DEFERRED_FRMS TX_MUL_COL_FRMS TX_SINGLE_COL_FRMS TX_BAD_FRMS TX_FIFO_UND_FRMS TX_BROADCAST_