STK850
N-channel 30V - 0.0024 - 30A - PolarPAK STripFETTM Power MOSFET
Features
Type STK850
VDSS 30V
RDS(on) <0.0029
RDS(on)*Qg 71nC*m
PTOT 5.2W
Ultra low top and bottom junction to case thermal resistance Very low capacitances 100% Rg tested Fully encapsulated die 100% Matte tin finish (in compliance with the 2002/95/EC european directive) PolarPAK is a trademark of VISHAY Figure 1. Internal schematic diagram
PolarPAK
Application
Switching applications
Description
This Power MOSFET is the latest development of STMicroelectronics unique "single feature size" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, moreover the double sides cooling package with ultra low junction to case thermal resistance allows to handle higher levels of current.
Bottom View
Top View
Table 1.
Device summary
Order code STK850 Marking K850 Package PolarPAK Packaging Tape & reel
October 2007
Rev 9
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www.st.com 16
Contents
STK850
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . .. . .. . .. . .. . ..... 6
3 4 5
Test circuits
. . .. . .. . .. . .. . .. . .. . .. . .. . .. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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STK850
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS (1) VGS(2) ID (4) ID IDM (3) PTOT (4)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor Value 30 16 18 30 18.75 120 5.2 0.0416 1.4 -55 to 150 Unit V V V A A A W W/C J C
EAS
(5)
Single pulse avalanche energy Operating junction temperature Storage temperature
TJ Tstg
1. Continuous mode 2. Guaranteed for test time < 15ms 3. Pulse width limited by package 4. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and 10sec 5. Starting TJ = 25C, ID = 15A, VDD = 25V
Table 3.
Symbol
Thermal data
Parameter Typ. 20 0.8 2.2 Max. 24 1 2.7 Unit C/W C/W C/W
Rthj-amb(1) Thermal resistance junction-amb Rthj-c(2) Rthj-c(3) Thermal resistance junction-case (top drain) Thermal resistance junction-case (source)
1. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and 10sec 2. Steady State 3. Measured at Source pin when the device is mounted on FR-4 board in steady state
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Electrical characteristics
ST K 8 5 0
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250A, VGS= 0 VDS = Max rating, VDS = Max rating,Tc=125C VGS = 16V VDS= VGS, ID = 250A VGS= 10V, ID= 15A VGS= 4.5V, ID= 15A 1 Min. 30 1 10
100
Typ.
Max.
Unit V A A nA V
2.5 0.0024 0.0029 0.0029 0.0035
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd Qgs1 Qgs2
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Pre Vth gate-to-source charge Post Vth gate-to-source charge Gate input resistance Test conditions Min. Typ. 3150 940 90 24.5 8 8.2 0.6 7.2 32.5 Max. Unit pF pF pF nC nC nC nC nC
VDS =25V, f=1 MHz, VGS=0
VDD=15V, ID = 30A VGS =4.5V (see Figure 16) VDD=15V, ID = 12A VGS =4.5V (see Figure 21) f=1 MHz Gate DC Bias = 0 Test signal level = 20mV open drain
RG
1.1
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STK850
Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Test conditions VDD= 15V, ID= 15A, RG=4.7, VGS=4.5V (see Figure 15) VDD=15V, ID= 15A, RG=4.7, VGS=4.5V (see Figure 15) Min. Typ. 20 57 Max. Unit ns ns
Turn-off delay time Fall time
31 13
ns ns
Table 7.
Symbol ISD ISDM (1) VSD (2) trr Q rr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 15A, VGS=0 ISD= 30A, di/dt = 100A/s, VDD=20V, TJ=150C (see Figure 20) 39 39.8 2 Test conditions Min. Typ. Max. 30 120 1.2 Unit A A V ns nC A
1. Pulse width limited by package 2. Pulsed: pulse duration = 300s, duty cycle 1.5%
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Electrical characteristics
ST K 8 5 0
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area Figure 3. Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Transconductance
Figure 7.
Static drain-source on resistance
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STK850 Figure 8. Gate charge vs gate-source voltage Figure 9.
Electrical characteristics Capacitance variations
Figure 10. Normalized gate threshold voltage vs temperature
Figure 11. Normalized on resistance vs temperature
Figure 12. Source-drain diode forward characteristics
Figure 13. Normalized BVDSS vs temperature
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Electrical characteristics Figure 14. Allowable IAV vs time in avalanche
ST K 8 5 0
The previous curve gives the single pulse safe operating area for unclamped inductive loads, under the following conditions: PD(AVE) =0.5*(1.3*BVDSS *IAV) EAS(AR) =PD(AVE) *tAV Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalanche (single pulse) tAV is the time in avalanche
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STK850
Test circuits
3
Test circuits
Figure 16. Gate charge test circuit
Figure 15. Switching times test circuit for resistive load
Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test switching and diode recovery times circuit
Figure 19. Unclamped inductive waveform
Figure 20. Switching time waveform
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Test circuits Figure 21. Gate charge waveform
Id Vds Vgs
STK850
Vgs(th)
Qgs1 Qgs2
Qgd
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STK850
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STK850
Table 8.
Ref.
PolarPAK (option "L") mechanical data
mm Min. Typ. 0.80 Max. 0.85 0.05 0.48 0.41 2.19 0.89 0.23 0.20 6 5.74 5.01 4.75 0.23 0.45 0.31 0.45 4.22 1.08 1.37 0.24 4.30 3.43 0.22 0.05 0.15 3.48 0.56 1.20 3.90 0.18 0 10 0.36 12 0 0.20 3.64 0.76 0.25 4.10 0.95 4.50 3.58 4.70 3.73 4.37 1.13 0.41 0.56 0.51 0.56 4.52 1.18 0.58 0.51 2.29 1.04 0.33 0.25 6.15 5.89 5.16 4.90 0.68 0.61 2.39 1.19 0.43 0.30 6.30 6.04 5.31 5.05 0.019 0.016 0.086 0.035 0.009 0.008 0.236 0.226 0.197 0.187 0.009 0.018 0.012 0.018 0.166 0.043 0.054 0.009 0.169 0.135 0.009 0.002 0.006 0.137 0.022 0.047 0.154 0.007 10 0.014 12 0.008 0.143 0.030 0.010 0.161 0.037 0.177 0.141 0.185 0.147 0.172 0.044 0.016 0.022 0.020 0.022 0.178 0.046 0.023 0.020 0.090 0.041 0.013 0.010 0.242 0.232 0.203 0.193 Min. 0.030 inch Typ. 0.031 Max. 0.033 0.002 0.027 0.024 0.094 0.047 0.017 0.012 0.248 0.238 0.209 0.199
A A1 b1 b2 b3 b4 b5 c D D1 E E1 H1 H2 H3 H4 K1 K2 K3 K4 M1 M2 M3 M4 P1 T1 T2 T3 T4 T5 <
0.75
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STK850
Package mechanical data
Figure 22. PolarPAK (option "L") drawings
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Package mechanical data Figure 23. Recommended PAD layout
STK850
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STK850
Revision history
5
Revision history
Table 9.
Date 10-Nov-2005 19-Dec-2005 30-Jan-2006 21-Mar-2006 25-May-2006 10-Oct-2006 08-May-2007 03-Sep-2007 01-Oct-2007
Document
Document revision history
Revision 1 2 3 4 5 6 7 8 9 First version Complete version Modified description on first page The document has been reformatted New note on Table 2 Modified general features New data on Table 5 and new Figure 21 Updated mechanical data Inser ted new Figure 23: Recommended PAD layout Changes
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STK850
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