PCLT-2A
Dual current limited over-voltage protected digital termination
Appl ication s
Type 1, 2 and 3 logic input termination for industrial automation AS-Interface bus input termination I/O termination in programmable logic controller Proximity detector interface Decentralized Input / Output modules
TSSO P14 Exposed pad
IEC61000-4-5 voltage surge, Level 3 500 V with 42 series resistor in differential mode Criteria B: temporary disruption IEC61000-4-4 transient burst immunity 4 kV peak voltage; 5 kHz repetitive rate Criteria A: fully functional IEC61000-4-6 conducted Radio Frequency Interference immunity 10 VRMS voltage Criteria A: fully functional Input protection against -30 V reverse polarity Ambient temperature: -25 to 85 C
Features
2 channel topology Low side input with common ground Wide range input DC Voltage: VI = - 0.3 to 30 V with RI = 0 VI = - 30 to 35 V with RI = 750 Current limiter: 3 to 7.5 mA programmable reference ILIM = 6.1 mA to 8.8 mA with RREF = 10 k ILIM = 2.8 mA to 4.3 mA with RREF = 22 k Narrow limiter spread: < 17 % Temperature compensated operation Output drive: No output activation below 2 mA input current 1.5 mA minimum output activating current in opto-coupler mode Programmable CMOS output mode option (VMOD > 2.9 V) LED drive for sensor status: 4.4 mA typical with RREF = 10 k Input protection (RI = 750 CIN = 22 nF) IEC61000-4-2 electrostatic discharge ESD, Level 4 In contact, 8 kV; in air, 15 kV Criteria B: temporary disruption
Benefits
Enable input to meet type1, 2 and 3 characteristics of IEC61131-2 standard Compatible operation with 2 & 3 wires proximity sensor according EN60947-5-2 standard Flexible configuration driving either opto coupler, or CMOS bus controller input, or 12 V AS-interface network Reduced overall dissipation Enhanced functional reliability Compact with high integration Surface Mount Package for highly automated assembly Insensitive to the on state sensor impedance
Rev 1 1/18
www.st.com 18
November 2005
1 Characteristics
PCLT-2A
1
1.1
Characteristics
IEC61000-4 standard compliance application diagrams
Figure 1. Isolated digital input diagram with opto-coupler driving output
VI
2 wires sensor
VIN IN1 RI RI CI LED1 CI IN2 RC CC VC RREF REF COMP VC OUT2 LED2 MOD COMS OUT1
3 wires sensor
VCC
Reverse polarity 1N4007
PCLT -2A
Figure 2.
Un-isolated digital input diagram with programmable CMOS output
PCLT -2A
VI 2 wires sensor RI RI VC RC CC RREF
Supply voltage protection SM15T39
VIN IN1 CI CI IN2 VC REF COMP
Reverse polarity 1N4007
OUT1 LED1 OUT2 LED2 MOD COMS
IN1
3 wires sensor VCC
IN2 BUS CONTROLLER VDD VSS
VDD GND VCC
5V SUPPLY
2/18
PCLT-2A
1 Characteristics
1.2
PCLT-2A Pinout and current limited termination block diagram
Pinout
1 2 3 4 5 6 7 14 13 12 11 10 9 8 OUT OUT1 COMS OUT2
3 0 % . I LIM
Figure 3.
IN1 COMP IN2 COMP VC N.C. REF
Figure 4.
Termination block diagram
CURRENT LIMITER ILIM OUTPUT INTERFACE
IN1 6 0 % . I LIM LO
OPTO
LED1
OUT1
LO
COMS MOD
OVER VOLTAGE PROTECTION
1 0 % . I LIM EN MOD EN
V CC 50A
LED1 LED2
COMP
VMOD 1.4 V
VDD
CMOS
IN1 CHANNEL #1
LO
2mA 5V
N.C.: Not Connected
IN2 VC
BIASING CIRCUIT CURRENT REFERENCE
LED2 CHANNEL #2 OUT2 COMS
REF
1.3
Static characteristic of a type-2 digital input using PCLT-2A
30 25 20
D
VF = 0.7V; R I = 750W VI = V IN + V F + RI x IIN
RI
30 6.1 8.5 8
ON
11
VI (V)
15 10 5
11
OFF
2
0 0 2 6 IIN (mA) 30
3/18
1 Characteristics
PCLT-2A
1.4
Symbol VCC VC VIN
Absolute ratings
Pin VC VC IN IN Parameter name & conditions Power supply steady state voltage, RC = 2.2 k Supply steady state voltage, RC = 0 k Input steady state voltage, RI = 0 k Input steady state voltage, RI = 750 Input repetitive pulse voltage, RI = 750 Input maximum forward current RI = 750 RC = 2.2 k Input maximum reverse current RI = 750 RC = 2.2 k (Note 2) MOD OUT, LED OUT, LED ALL Maximum applied CMOS supply voltage Maximum applied output voltage, VMOD < 0.75 V Maximum applied output voltage, VMOD > 2.9 V Value - 0.3 to 35 - 0.3 to 30 - 0.3 to 30 -30 to 32 -30 to 35 10 20 14 2.5 14 - 4 to 7 - 25 to 150 Unit V V V V V mA mA V V V mA C
VI (Note: 1)
IIN
IN
VMOD VOM
IOM TJ
Output driver current Junction temperature range
1.5
Symbol VCC VC
Recommended operating conditions
Pin VC VC IN Parameter name & conditions Power supply steady state voltage, RC = 2.2 k Power supply voltage range Input repetitive pulse voltage RI = 750 RC = 2.2 k Operating CMOS mode voltage range MOD Maximum operating 12V Analog voltage Operating Ambient temperature range ALL Operating Junction temperature range - 25 to 150 C 13.5 - 25 to 85 V C Value 19 to 35 14 to 27 - 30 to 30 2.9 to 5.5 Unit V V V V
VI (Note1) VMOD TAMB TJ
Note: 1 VI = VIN + VF + RI x IIN with VIN = voltage at the PCLT-2A input pin; VCC = VC + RC x ICC with VC = voltage at the PCLT-2A power supply pin. 2 Respect to the reverse polarity test of one input as shown on Figure 12.
4/18
PCLT-2A
1 Characteristics
1.6
Electromagnetic compatibility ratings
TJ=25 C, RI = 750 RC = 2.2 k , & reverse diode connected (unless otherwise specified)
Value
Symbol
Node Parameter name & conditions ESD protection, IEC 61000-4-2, per input, in air
Unit kV kV kV kV kV V V V
15 8 3 3 4 500 1000 1000
VESD
IN VCC
ESD protection, IEC 61000-4-2, per input, in contact ESD protection, IEC 61000-4-2, per input, in air, RI = 0 ESD protection, IEC 61000-4-2, per input, in contact, RI = 0
VPPB VPP VPP VPP
VI VI VI VCC
Total Peak Pulse Voltage Burst, IEC61000-4-4 CC = 33 nF, CI = 22 nF, F = 5 kHz (Note 1) Peak Pulse Voltage Surge, IEC61000-4-5, R = 42 (Note 2) Peak Pulse Voltage Surge, IEC61000-4-5, R = 42 RI = 1200 (Note 2) Peak Pulse Voltage Surge, IEC61000-4-5, R = 2 (Note 2)
Note: 1 Test diagram described on Figure 1 using the application PCB with a normalized capacitive coupling clamp 2 Test diagram described on Figure 1
1.7
Symbol RTH JA
Thermal resistance
Parameter name & conditions Value Unit
Thermal resistance Junction to ambient Board copper surface = 1.25 cm², copper thickness = 35 m, single face
100
C/W
5/18
1 Characteristics
PCLT-2A
1.8
DC electrical characteristics
(TJ = 25 C, VCC = 24 V, RREF = 10 k RC = 2.2 k and referred to COM pin voltage, unless otherwise specified)
Symbol
Pin
Name
Conditions
Min
Typ
Max
Unit
Current limitation VIN = 4.5 to 26 V VOUT = 0.9 to 1.5 V VLED = 1.5 to 2.5 V TAMB =-25 to 85 C RREF = 10 k VIN = 5.5 to 26 V VOUT = 0.9 to 1.5 V VLED = 1.5 to 2.5 V TAMB =-25 to 85 C RREF = 22 k IIN = 100 A IIN=6 mA IIN=2 mA, RREF=22 k -
ILIM
IN
Input limiting current
6.1
7.6
8.8
mA
ILIM
IN
Input limiting current
2.8
3.6
4.3
mA
Low current input voltage VLOW IN Current limiter activation voltage
1.5 2.6 2.3
3 -
V V V
Input & Supply Protection VCL IN, VC Clamping voltage IIN = 7 mA, tP = 1 ms, RREF open 31 38 V
Output interface operation OUT LED LED VMOD = 0 V, VI = 5 V, (Note 1) VMOD = 0 V, IIN=2 mA, (Note 2) Off state LED voltage IIN = 2 mA VMOD = 0 V, IIN = 2 mA VOFF OUT Off state output voltage VMOD > 2.9 V, IIN = 2 mA VMOD = 0 V, VOUT = 1.5 V VIN =4.5 V VMOD = 0 V, VIN = 5.5 V, RREF = 22 k , VOUT = 1.5 V VMOD > 2.9 V RREF = 10 k , VIN > 4.5 V RREF = 22 k VIN > 5.5 V VIN = 4.5 V, VLED = 2.5 V (Note 3) ION LED On state LED current VIN = 5.5 V, RREF = 22 k VLED = 2.5 V 1.5 2 10 10 0.1 0.02 40 40 0 .2 0.1 20 % VMOD A A V V V mA
IOFF VOFF
Off state output current
ION
OUT
On state opto-coupler current
0.5
0.9
mA
VON
OUT
On state output voltage
80%. VMOD 3.5 1.4 4.4 2.1 mA mA
6/18
PCLT-2A
1 Characteristics
Symbol
Pin
Name
Conditions
Min
Typ
Max
Unit
Output operation selection circuit VTH MOD I OUT MOD OUT Opto-CMOS threshold CMOS output current VMOD = 12V 0 .75 35 50 2 .9 65 V A
Power supply circuit IC IDD VC MOD Supply current CMOS supply current VCC = 30V VMOD = 5V, VIN open VMOD = 12V, VIN open 1.5 0.25 0.4 2 0.35 0.8 mA mA mA
Note: 1 According to application diagram ( Figure 1) with the use of a RI = 750 resistor a reverse diode from COM to GND (VF = 0.7 V) and an opto-coupler (RLED (0V) = 15 k , VF=1.2 V). 2 Same as note 1 above, but RI= 0 . 3 When no LED diode is used, connect LED pin to the COMP ground.
1.9
Switching electrical characteristics
(TJ=25C, VCC = 24 V, RC = 2.2k, CI = 0 and COM pin voltage referred unless otherwise specified)
Symbol FMAX TPLH
Pin IN-OUT IN-OUT
Name Input to output operating frequency Input Lo to Hi propagation time
Conditions Duty cycle = 50% CI = 0 CI = 0, VMOD = 0 V
Min
Typ 5 16 0.1
Max
Unit kHz s
TPHL
IN-OUT
Input Hi to Lo propagation time
CI = 0, VMOD = 5 V COUT = 50 pF
s 7.6
7/18
1 Characteristics
PCLT-2A
1.10
Functional characteristics
Figure 5. Variation of the input-output propagation delay time TPLH at rising edge versus the supply voltage VCC with RC = 2.2 k
TPLH (s)
19 18.5 18 17.5 17 16.5 16 15.5 15 14.5
VC (V)
14 10 12 14 16 18 20 22 24 26 28
Figure 6.
Typical current limiter variation versus junction temperature
ILIM / ILIM at Tj = 25 C
1.01
1.00
0.99
0.98
Vin = 27.5 V
0.97
0.96
Vin = 5 V
0.95
0.94 -40 - 20 0 20
Tj (C)
40 60 80 100 120 14 0
8/18
PCLT-2A
Figure 7.
1 Characteristics
Typical current limiter variation versus reference resistance RREF
ILIM (mA)
10 9 8 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 Vc = 27 V, Vin = 25 v, Vout = 0.9 V, Vled = 1.5 V
RREF (k)
Figure 8.
Typical limiter activation voltage variation versus junction temperature
VLOW (V)
3.0
2.5
Iin = 6.1 mA Iin = 2.2 mA
2.0
Tj (C)
1.5 - 25 0 25 50 75 100 125 150
Figure 9.
Thermal resistance variation versus copper area (35 m layer thickness; 50vias/cm2 and 300 m via diameter in double layer)
150% 140% 130% 120% 110% 100% 90% 80% 70% 60% 0 0.5 1 1.5 2 2.5 3 3.5 4
Rth(j-a)/Rth(1.25 cm2)
PCB single layer PCB double layer Copper area (cm ² )
9/18
2 Functional description
PCLT-2A
2
Functional description
The PCLT-2A is a dual input termination device designed for 24 V DC automation applications. It achieves the front-end circuitry of a digital input module (I/O) in industrial automation. Available in a two channels configuration, it offers a high-density termination by minimizing the conducting dissipation and the external components count. It is housed in a surface mount package to reduce the printed board size. Made of an input voltage protection, a serial current limiting circuit and an output interface, each channel circuit terminates the connection between the logic input and its associated high side sensor or switch. The PCLT-2A is a current limited dual channel circuit compatible with the type 2 (7.5 mA) or type 3 (3 mA) characteristic of the IEC61131-2 standard. An external resistance RREF allows the limiting current value to be adjusted from 3 to 7.5 mA. The unique structure of the PCLT limiter allows its activation threshold to be low and insensitive to the output voltage up to 2.5 V. Each input voltage clamping block protects the module input against electromagnetic interferences such as those described in the IEC61131-2 standard and IEC61000-4-2 (ESD), 4-4 (transient burst), 4-5 (voltage surge) and 4-6 (conducted radio frequency interferences) standards. The supply input is also designed with such a protection structure. The current limiting circuit connected between the input and the output pins is compensated all over the temperature range. Thanks to its low tolerance, the current limitation allows reducing drastically the dissipation of the input compared to a resistive input. Furthermore, the PCLT2 is housed into a very low RTH exposed pad TSSOP14 package that allows the PCB cooling pad to be reduced: the overall module becomes smaller and the hot spot effect is reduced. The output block of each termination channel transfers the input logic state to a logic output and a Light Emitting Diode (LED) that allows this state to be checked visually.
2.1
The VMOD pin
The voltage VMOD applied to the selector pin MOD allows the output OUT to be configured either in an opto-coupler driver for VMOD less than 0.75 V or in a CMOS output able to interface directly a bus controller circuit for VMOD higher than 2.9 V. In CMOS mode, the VMOD pin activates a CMOS compatible buffer output, able to source up to a 50 A current powered by the MOD pin.
2.2
OFF state
In accordance with IEC61131-2 standard, for both opto-coupler and CMOS configuration modes when the input current is less than 2 mA (type 2) or 1.5 mA (type 3) the output circuits divert all the input current and maintain both LED and output in OFF state.
10/18
PCLT-2A
3 Surge voltage test circuit
2.3
ON state
When the module input voltage VI, including the 750 input resistor and the reverse diode, is higher than 11V corresponding to a PCLT input voltage VIN of 5V, both LED and output circuits are in ON state. The input current is then shared between the internal circuitry, the LED (about 60 %), and the driver output (about 30 %) in case of opto-coupler mode. In CMOS mode, the CMOS level is defined by the VMOD voltage that is equal the supply voltage VDD of the bus controller: it can be 3.3 V or 5 V. The output voltage is delivering 80 % of VDD for high state and 20 % VDD for low state. When no LED diode is used, the LED outputs pin must be connected to the ground COMP of the circuit to allow the current to flow back to the power supply.
3
Surge voltage test circuit
The input and supply pins are designed to withstand electromagnetic interferences. They are protected by a clamping diode that is connected to the common pin COM. Combined with the serial input resistance RI, this clamping diode is effective against the fast transient bursts (4 kV, IEC61000-4-4) and the voltage surges (1 kV,IEC61000-4-5). This topology allows the surge voltage to be applied from each input to other inputs, the ground and the supply contacts in differential or common modes (see figure 10). Thanks to its high resistance RC = 2.2 k and the conventional power supply protection that uses a clamping diode such as the SM15T39C TransilTM, the supply pin VC withstands 1000 V surge voltage according to IEC61000-4-5 (see figure 11).
Figure 10. Input pin IN voltage surge test circuit
VPP = 500 V with 42 VCC RC VC VPP I VPP RI IN1 RI RI VPP GND COMP IN2
Figure 11. Supply pin VC voltage surge test circuit
V CC RC VC RI IN1 1kV 2 SM15T39C 1 kV 42 GND COM 5 nF PE/FE RI IN2
PCLT -2
PCLT -2
5 nF PE/FE
TM: Transil is a trademark of STMicroelectronics
11/18
4 Input reverse polarity robustness
PCLT-2A
4
Input reverse polarity robustness
Each input of the PCLT circuit may be biased to a reverse polarity equal to - VCC. This case corresponds to a connection mistake or a reverse biasing that is generated by the demagnetization of a monitored inductive solenoid. The involved input withstands the high reverse current up to 20 mA; its opto-coupler is OFF and is protected by the conducting input diode. The input remains operational, and some extra dissipation should be take place in their clamping protections. Figure 12. Current sharing in the PCLT device when IN2 is biased at -30 V and IN1 at +30 V.
Vcc = + 30V
3.6mA
2.2 k
VC
IN1
9.7mA
I1 = + 30V 750
1N4007
VCL= 38 V
I REG N OUT1
OPTO 1
GND (0V) COM OPTO 2 750 I2 = -30V
13.3mA
IN2
I REG4
OUT2
PCLT -2
Considering the supply operation, a reverse blocking diode can be connected between the module ground and the common pin COM to protect the PCLT device against any spurious reverse supply connection. Then, the whole module supply voltage rating is extended to 30 V.
12/18
PCLT-2A
5 Programming of the PCLT-2A according to the input type requirement
5
Programming of the PCLT-2A according to the input type requirement
The operation of the PCLT-2 can be set to the various logic input types defined in the IEC61131-2 standard. The current reference of the input-limiting block of each channel is programmable thanks to an external resistor RREF. Moreover, because the operating current is different for each type, the external input resistor RI can be changed to improve the overvoltage robustness of the whole circuit. Table 1 describes the input characteristics requirements according to the IEC standard, and Table 2 the resistance values for the 1, 2, and 3 types and the corresponding performances of the PCLT input. Table 1. IEC61131-2 requirements for logic input
Type State OFF Parameter IOFF MAX VOFF MAX ON ION MIN VON MIN Unit mA V mA V 0.5 5 15 @ IOFF 2 15 1.5 5 11 @ IOFF 2 11 2 5 11 @ IOFF 6 11 1 3 2
Table 2.
PCLT-2A setting for each type of logic input
Type 1 3 22 1.2 2.2 2 10 0.75
Setting RREF RI RC PERFORMANCES IIN MIN IIN TYP IIN MAX ILED TYP SURGE w/RI ESD with RI
Unit k k k 22 2.2
mA mA mA mA kV kV
2.8 3.6 4.3 2.1 >1
2.8 3.6 4.3 2.1 1 8 in contact, 15 in air (class 4)
6.1 7.6 8.8 4.4 0.5
13/18
6 Unisolated ASI-interface bus application diagram
PCLT-2A
6
6.1
Unisolated ASI-interface bus application diagram
AS-Interface Bus application overview
The AS-Interface bus is a low-end field bus for actuators and sensors in manufacturing & industrial automation. Its electrical architecture uses an unshielded 2-wire yellow cable that transports both the 24 V power supply of the field nodes and the serial bi-directional data communication. Figure 13. Simplified architecture of AS-Interface bus.
AS-i MASTER
I/O SLAVE
I/O SLAVE
I/O SLAVE
AS-i SLAVES
The data communication is achieved with a current carrier modulation superimposed over the power wires. Therefore, the power bus terminals are filtered in order to maintain identical and calibrated differential and common mode impedances measured by both master and slave units.
6.2
Isolation of the sensor section and the supply from data/supply bus
The PCLT can be designed as an interface between a proximity sensor and its associated slave controller unit. The sensor power supply is generated from the bus power supply with a filter and a regulator that are inserted in the slave unit. In the same manner, the sensor logic signal is isolated from the AS- Interface power supply bus to avoid any degradation of the data transmission. A conventional way to achieve the interface with the PCLT and the AS- Interface controller is to insert an opto-coupler between the AS-Interface controller and the PCLT that runs in optocoupler mode as shown on figure 1 (MOD=0).
14/18
PCLT-2A
6 Unisolated ASI-interface bus application diagram
6.3
Un-isolated connection of the PCLT with AS-Interface controller
To remove the opto-coupler the operation of the PCLT has been extended to fit the AS-Interface application. A precaution is required on its interface with the bus controller: the impedance between the two circuits must be high in order to maintain the impedance isolation. To achieve this impedance isolation, the PCLT runs in CMOS mode (MOD=VCC) and the buffer operation is extended up to VCC = 12 V. In the application, the VCC voltage is generated with a Zener diode reference fed from the sensor bus. Because of the buffer voltage increase, it becomes possible to insert high impedance between the PCLT output and the AS-Interface bus controller input. Typically a 100k resistor is designed while keeping a 5 V CMOS operation on the input of the bus controller. Figure 14 shows the application diagram where the PCLT is connected to the slave bus controller through a 100 k resistor. The logic signal is transmitted with a low level of less than 20% of the VDD supply voltage and a high level of at least 3.5 V defined by the PCLT output buffer limiting its current to 35 A minimum and the 100 k pull down resistor (0.035 mA times 100 k). Figure 14. AS-Interface slave controller unit using the PCLT in an un-isolated manner.
28V
Vreg
30V
2.2 k
VCCsensor
750 22nF
2.2 k
VCC
1 14
ASiP
sensor
100 k
PCLT2
33nF
SLAVE AS-I CONTROLLER
10 10 9 7 LED
10 k
100 k
4.7nF
12V
ASiN
15/18
7 Package mechanical data
PCLT-2A
7
Package mechanical data
DIMENSIONS REF.
k C 0.25 mm Gauge plane L L1 E1
Millimeters Min. Typ. Max. 1 .2 0.05 0.8 0.19 0.09 4 .9 6 .2 4.3 5.0 6.4 4.4 0.65 0.45 0.6 1.0 0 8 0 .1 3.6 3.0 0 1.0 0.15 0.002 Min.
Inches Typ. Max. 0.047 0.006
A A1 A2 b
1.05 0.031 0.039 0.041 0 .3 0 .2 5 .1 6 .6 4.5 0.007 0.003 0.012 0.008
Seating plane
C
c D
E E2 A A2 A1
0.193 0.197 0.200 0.244 0.252 0.260 0.169 0.173 0.177 0.025
E E1 e L
7
8
e
b
0.75 0.018 0.024 0.029 0.039 8 0.004 0.142 0.118
D1
D
C
L1 k aaa D1 E2
1
14
PIN 1 INDENTIFICATION
Figure 15. Footprint
aaa
6.80 4.40 0.40
3.10 0.65
0.70
3.00
1.20
dimensions in mm
16/18
PCLT-2A
8 Ordering information scheme
8
Ordering information scheme
PCLT - 2
P = current limiter programmability from 3 mA to 7 mA 2 = Number of Integrated channels A = EMC level: 500v according to IEC61000-4-5 for type 2 1000v according to IEC61000-4-5 for type 3
A
T4
T4 = Package TSSOP14
9
Ordering information
Ordering Code PCLT-2AT4 PCLT-2AT4-TR Marking PCLT-2AT4 PCLT-2AT4 Package TSSOP14(1) TSSOP14(1) Weight 0.057g 0.057g 96 2500 Base Qty Delivery Mode Tube Tape & reel
1. Exposed pad version
10
Revision history
Da te 16-Nov-2005 Revision 1 Initial release. Cha nge s
17/18
10 Revision history
PCLT-2A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
18/18
|
